TPS65310A-Q1
SLVSC15H – MAY 2013 – REVISED DECEMBER 2021
TPS65310A-Q1 High-Voltage Power-Management IC For Automotive Safety
Applications
1 Features
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2 Applications
•
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Multiple rail DC power distribution systems
Safety-critical automotive applications
– Advanced driver assistance systems
3 Description
The TPS65310A-Q1™ device is a power-management
unit, meeting the requirements of digital signal
processor (DSP)-controlled automotive systems (for
example, Advanced Driver Assistance Systems).
With the integration of commonly used features, the
TPS65310A-Q1 device significantly reduces board
space and system costs.
PART NUMBER
TPS65310A-Q1
(1)
PACKAGE
VQFNP (56)(1)
BODY SIZE (NOM)
8.00 mm x 8.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
VBAT
Protection FET
VIN
Battery
Sense
IRQ
VBuck1
VINPROT
•
Qualified for automotive applications
AEC-Q100 test guidance with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature
– Device HBM ESD classification level H1B
– Device CDM ESD classification level C3B
Input Voltage Range: 4 V to 40 V, transients up to
60 V; 80 V when using external P-channel Metal
Oxide Semiconductor (PMOS)
Single output synchronous buck controller
– Peak gate drive current 0.6 A
– 490-kHz fixed switching frequency
– Pseudo-random frequency-hopping spread
spectrum or triangular mode
Dual synchronous buck converter
– Designed for output currents up to 2 A
– Out-of-phase switching
– Switching frequency: 0.98 MHz
Adjustable 350-mA linear regulator
Adjustable asynchronous boost converter
– 1-A integrated switch
– Switching frequency: 0.98 MHz
Soft-start feature for all regulator outputs
Independent voltage monitoring
Undervoltage (UV) detection and overvoltage (OV)
protection
Short-circuit, overcurrent, and thermal protection
on buck controller, gate drive, buck converters,
boost converter, and linear regulator outputs
Serial Peripheral Interface (SPI) for control and
diagnostic
Integrated Window Watchdog (WD)
Reference voltage output
High-Side (HS) driver for use with external Field
Effect Transistor (FET), Light-Emitting Diode (LED)
driver
Input for external temperature sensor, Integrated
Circuit (IC) shutdown at TA < –40°C
Thermally enhanced package
– 56-Pin QFN (RVJ)
I/O supply
Buck
Controller
VIO
RESN
PRESN
WD Trigger
Wake Up Input
SPI Interface
RESET
VBuck1
Watchdog
Wake
Buck
Converter
VBuck2
SPI
Reference Voltage
Reference
voltage
+
Comparator
Boost
Converter
HS PWM Input
VINPROT
Buck
Converter
High Side
LED Driver
Linear
Regulator
VBuck3
VBuck1
VBooster
VLDO
Figure 3-1. Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65310A-Q1
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SLVSC15H – MAY 2013 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (Continued)..................................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings .............................................................. 8
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................8
7.6 SPI Timing Requirements ........................................ 14
7.7 Typical Characteristics.............................................. 15
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 20
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................23
8.5 Programming ........................................................... 34
8.6 Register Maps...........................................................34
9 Application and Implementation.................................. 42
9.1 Application Information............................................. 42
9.2 Typical Applications ................................................. 42
10 Power Supply Recommendations..............................53
11 Layout........................................................................... 55
11.1 Layout Guidelines................................................... 55
11.2 Layout Example...................................................... 56
12 Device and Documentation Support..........................59
12.1 Documentation Support ......................................... 59
12.2 Receiving Notification of Documentation Updates..59
12.3 Support Resources................................................. 59
12.4 Trademarks............................................................. 59
12.5 Electrostatic Discharge Caution..............................59
12.6 Glossary..................................................................59
13 Mechanical, Packaging, and Orderable
Information.................................................................... 60
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (May 2019) to Revision H (December 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Globally changed instances of legacy terminology to controller and peripheral where SPI is mentioned.......... 1
• Shutdown comparator Reference voltage Min specification changed to 1mV from 10mV................................. 8
• High-side switch current limit specification for for BUCK2/3 changed: Min spec changed to 2.4A from 2.5A
and max spec changed to 3.5A from 3.3A..........................................................................................................8
Changes from Revision F (December 2018) to Revision G (May 2019)
Page
• Changed part number to "TPS65310ASQRWERQ1" ...................................................................................... 60
Changes from Revision E (October 2014) to Revision F (December 2018)
Page
• Deleted lead temperature from Absolute Maximum Ratings table .................................................................... 7
• Changed the Handling Ratings table to ESD Ratings and moved the storage temperature parameter to the
Absolute Maximum Ratings table ...................................................................................................................... 8
Changes from Revision D (July 2014) to Revision E (October 2014)
Page
• Added RWE Packaging Option ..........................................................................................................................1
• Added the following text to the paragraph after the Compensation Settings table in the Compensation of the
BUCK2 and BUCK3 Converters section: upper resistance and effective VBUCK2/3 at higher frequencies to
the ....................................................................................................................................................................46
2
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Changes from Revision C (January 2014) to Revision D (July 2014)
Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 5
Changes from Revision B (December 2013) to Revision C (January 2014)
Page
• Added new IOUT = 350 mA, TJ = 150°C test condition with higher typ and max values to the VDropout
parameter and changed test condition for lower typ and max values from TJ = 150°C to TJ = 125°C ............. 8
• Changed the min value for the VHSSC_HY parameter from 1.5 to 1 and deleted the typ (2.5) and max (3.5)
values................................................................................................................................................................. 8
• Changed the max value for the tVSSENSE_BLK parameter from 20 to 35....................................................... 8
Changes from Revision A (June 2013) to Revision B (November 2013)
Page
• Added reference to the TPS65310A-Q1 Efficiency Application Report to the TYPICAL CHARACTERISTICS
condition statement...........................................................................................................................................15
• Moved the component selection portion of the Buck Controller (BUCK1) section into the Typical Applications
section ............................................................................................................................................................. 43
• Changed R1 to R3 in the Compensation of the Buck Controller section.......................................................... 44
• Added the Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter to the Detailed Design
Procedure in the Synchronous Buck Converters BUCK2 and BUCK3 section................................................ 46
• Changed the inductance, capacitance and FLC values from 3.3 µH, 20 µF, and 12.9 kHz to 1.5 µH, 39 µF,
and 13.7 kHz (respectively) in the For example: section of the Compensation of the BOOST Converter
section.............................................................................................................................................................. 50
• Added the Linear Regulator application section .............................................................................................. 51
Changes from Revision * (May 2013) to Revision A (June 2013)
Page
• Changed VPOR rising VIN typ value from 4.1 to 4.2............................................................................................8
• Changed VPOR_hyst values from 0.37 min, 0.5 typ, 0.63 max to 0.47 min, 0.6 typ, and 0.73 max, respectively....
8
• Changed VDropout max value from 140 to 143.....................................................................................................8
• Changed VREF_OK threshold typ and max values from 3 to 3.07 and 3.09 to 3.12, respectively. ...................... 8
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5 Description (Continued)
The device includes one high-voltage buck controller for preregulation combined with two buck and one boost
converters for postregulation. A further integrated low-dropout regulator (LDO) rounds up the power supply
concept and offers a flexible system design with five independent voltage rails. The device offers a low power
state (LPM0 with all rails off) to reduce current consumption in case the system is constantly connected to the
battery line. All outputs are protected against overload and overtemperature.
An external PMOS protection feature makes the device capable of sustaining voltage transients up to 80 V. This
external PMOS can also be used in safety-critical applications to protect the system in case one of the rails
shows a malfunction (undervoltage, overvoltage, or overcurrent).
Internal soft start ensures controlled start-up for all supplies. Each power supply output has adjustable output
voltage based on the external resistor network settings.
4
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VT
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
43
56
VSSENSE
1
VIN
GPFET
VINPROT
HSCTRL
HSSENSE
WAKE
42
TOP VIEW
EXTSUP
VREG
BOOT1
GU
PH1
GL
29
VSUP3
PH3
PGND3
VMON3
COMP3
VSENSE3
VSENSE2
COMP2
VMON2
PGND2
PH2
VSUP2
BOOT2
IRQ
RESN
PRESN
VT_REF
VBOOST
PH5
PGND5
VSENSE5
COMP5
VSENSE1
COMP1
VMON1
S2
S1
BOOT3
28
14
15
PGND1
WD
CSN
SDI
SCK
SDO
VIO
HSPWM
VSUP4
LDO
VSENSE4
VREF
DVDD
GND
6 Pin Configuration and Functions
Figure 6-1. RVJ Package. 56-Pin VQFN With Exposed Thermal Pad. Top View.
Table 6-1. Pin Functions
PIN
TYPE(1)
PULLUP
PULLDOWN
DESCRIPTION
NAME
NO.
BOOT1
10
I
—
The capacitor on these pins acts as the voltage supply for the high-side MOSFET gate-drive circuitry.
BOOT2
29
I
—
The capacitor on these pins act as the voltage supply for the high-side MOSFET gate drive circuitry.
BOOT3
42
I
—
The capacitor on these pins act as the voltage supply for the BUCK3 high-side MOSFET gate drive
circuitry.
COMP1
18
O
—
Error amplifier output for the switching controller. External compensation network is connected to this node.
COMP2
34
I
—
Compensation selection for the BUCK2 switching converter
COMP3
37
I
—
Compensation selection for the BUCK3 switching converter.
COMP5
20
O
—
Error amplifier output for the boost switching controller. External compensation network is connected to this
node.
CSN
44
I
Pullup
DVDD
55
O
—
Internal DVDD output for decoupling
EXTSUP
8
I
—
Optional LV input for gate driver supply
GL
13
O
—
Gate driver – low-side FET
GND
56
O
—
Analog GND, digital GND and substrate connection
GPFET
3
O
—
Gate driver external protection PMOS FET.
GU
11
O
—
Gate driver – high-side FET
HSCTRL
5
O
—
High-side gate driver output
HSPWM
49
I
Pulldown
High side and LED PWM input
HSSENSE
6
I
—
Sense input high side and LED
IRQ
28
OD
—
Low battery interrupt output in operating mode
LDO
51
O
—
Linear regulated output (connect a low ESR ceramic output capacitor to this terminal)
SPI – Chip select
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Table 6-1. Pin Functions (continued)
PIN
TYPE(1)
PULLUP
PULLDOWN
14
O
—
Ground for low-side FET driver
32
O
—
Power ground of synchronous converter BUCK2
PGND3
39
O
—
Power ground of synchronous converter BUCK3
PGND5
22
O
—
Power ground boost converter
PH1
12
O
—
Switching node - BUCK1 (floating ground for high-side FET driver)
PH2
31
O
—
Switching node BUCK2
PH3
40
O
—
Switching node BUCK3
PH5
23
O
—
Switching node boost
PRESN
26
OD
—
Peripherals reset
RESN
27
OD
—
System reset
S1
15
I
—
Differential current sense inputs for BUCK1, S2 pull-down only active in RAMP and ACTIVE state
S2
16
I
Pulldown
SCK
46
I
Pulldown
SPI – Clock
SDI
45
I
Pulldown
SPI – controller out, peripheral in
SDO
47
O
—
SPI – controller in, peripheral out - push-pull output supplied by VIO
VBOOST
24
I
—
Booster output voltage
VIN
2
I
—
Unprotected supply input for the base functionality and band gap 1. Supplied blocks are: RESET, WD,
wake, SPI, temp sensing, voltage monitoring and the logic block.
VINPROT
4
I
—
Main input supply pin (gate drivers and bandgap2)
VIO
48
I
—
Supply input for the digital interface to the MCU. Voltage on this input is monitored. If VIO falls below UV
threshold a reset is generated and the part enters error mode.
VMON1
17
I
—
Input pin for the independent voltage monitor at BUCK1
VMON2
33
I
—
Input pin for the independent voltage monitor at BUCK2
VMON3
38
I
—
Input pin for the independent voltage monitor at BUCK3
VREF
53
O
—
Accurate reference voltage output for peripherals on the system (for example, ADC)
VREG
9
O
—
Internal regulator for gate driver supply (decoupling) and VREF
VSENSE1
19
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
VSENSE2
35
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
VSENSE3
36
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
VSENSE4
52
I
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
VSENSE5
21
I
—
Input for externally sensed voltage of the boost output using a resistor divider network from their respective
output line to ground.
VSSENSE
1
I
—
Input to monitor the battery line for undervoltage conditions. UV is indicated by the IRQ pin.
VSUP2
30
I
—
Input voltage supply for switch mode regulator BUCK2
VSUP3
41
I
—
Input voltage supply for switch mode regulator BUCK3
VSUP4
50
I
—
Input voltage supply for linear regulator LDO
VT
54
I
—
Input pin for the comparator with shutdown functionality. This input can be used to sense an external NTC
resistor to shutdown the IC in case the ambient temperature is too high or too low. Tie to GND if not in use.
VT_REF
25
O
—
Shutdown comparator reference output. Internally connected to DVDD, current-limited. When not in use
can be connected to DVDD or left open.
WAKE
7
I
Pulldown
Wake up input
WD
43
I
Pulldown
Watchdog input pin. WD is the trigger input coming from the MCU.
NAME
NO.
PGND1
PGND2
(1)
6
DESCRIPTION
Description of pin type: I = Input; O = Output; OD = Open-drain output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply inputs
Buck controller
MIN
MAX
VIN
–0.3
80
VINPROT
–0.3
60
VSUP2, 3 (BUCK2 and 3)
–0.3
20
VSUP4 (Linear Regulator)
–0.3
20
VBOOST
–0.3
20
EXTSUP
–0.3
13
VIO
–0.3
5.5
PH1
–1
–2 for 100 ns
60
VSENSE1
–0.3
20
COMP1
–0.3
20
GU-PH1, GL-PGND1, BOOT1-PH1
–0.3
8
S1, S2
–0.3
20
S1-S2
–2
2
BOOT1
–0.3
68
VMON1
–0.3
20
–1
20
–1(4)
20(4)
BOOT2, BOOT3
PH2, PH3
Buck controller
Linear regulator
Boost converter
Digital interface
Wake input
Protection FET
Battery-sense input
Temperature sense
Reference voltage
High-side and LED
driver
UNIT
V
V
–2 for 10 ns
VSENSE2, VSENSE3
–0.3
20
COMP2, COMP3
–0.3
20
VMON2, VMON3
–0.3
20
BOOTx – PHx
–0.3
8
LDO
–0.3
8
VSENSE4
–0.3
20
VSENSE5
–0.3
20
PH5
–0.3
20
COMP5
–0.3
20
CSN, SCK, SDO, SDI, WD, HSPWM
–0.3
5.5
RESN, PRESN, IRQ
–0.3
20
WAKE
–1 (3)
60
GPFET
–0.3
80
VIN – GPFET
–0.3
20
–1 (3)
60
Transients up to 80 V(2)
VT
–0.3
5.5
VT_REF
–0.3
20
VREF
–0.3
5.5
HSSENSE
–0.3
60
HSCTRL
–0.3
60
VINPROT-HSSENSE, VINPROT-HSCTRL
VSSENSE
V
V
V
V
V
V
V
V
V
V
–0.3
20
Driver-supply decoupling VREG
–0.3
8
V
Supply decoupling
–0.3
3.6
V
DVDD
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7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)
Temperature ratings
(1)
(2)
(3)
(4)
MIN
MAX
Junction temperature, TJ
–55
150
Operating temperature, TA
–55
125
Storage temperature, Tstg
–55
165
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Internally clamped to 60-V, 20-kΩ external resistor required, current into pin limited to 1 mA.
Imax = 100 mA
Maximum 3.5 A
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per
AEC Q100-011
UNIT
±1000
VT pin
±150
All pins except VT
±500
Corner pins (BOOT2, IRQ, S1, PGND1,
VSSENSE, GND, WD, and BOOT3)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX
Supply voltage at VIN, VINPROT, VSSENSE
4.8
40
All electrical characteristics in this specification
–40
125
TA
Operating free air
temperature
Shutdown comparator and internal voltage regulators in this specification
–55
125
TJ
Operating virtual junction All electrical characteristics in this specification
temperature
Shutdown comparator and internal voltage regulators in this specification
–40
150
–55
150
UNIT
V
°C
°C
7.4 Thermal Information
TPS65310A-Q1
THERMAL
METRIC(1)
(RVJ) (VQFN)
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
ψJB
RθJC(bot)
(1)
27
°C/W
11.2
°C/W
8
°C/W
Junction-to-top characterization parameter
0.8
°C/W
Junction-to-board characterization parameter
4.9
°C/W
Junction-to-case (bottom) thermal resistance
0.8
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953.
7.5 Electrical Characteristics
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE-CURRENT CONSUMPTION
VIN
8
Device operating range
Buck regulator operating range, Voltage on VIN and VINPROT pins
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
VPOR
Power-on reset threshold
VPOR_hyst
Power-on reset hysteresis on VIN
consumption(1)
ILPM0
LPM0 current
ILPM0
LPM0 current (commercial vehicle
application) consumption(1)
MIN
TYP
MAX
Falling VIN
TEST CONDITIONS
3.5
3.6
3.8
Rising VIN
3.9
4.2
4.3
0.47
0.6
UNIT
V
0.73
V
TA = 25°C, All off, wake active, VIN = 13 V, Total current into
VSSENSE, VIN and VINPROT
44
μA
TA = 130°C, All off, wake active, VIN = 24.5 V, Total current into
VSSENSE, VIN and VINPROT
60
μA
IACTIVE1
BUCK1 = on, VIN = 13 V, EXTSUP = 0 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into
VSSENSE, VIN and VINPROT
32
mA
IACTIVE123
BUCK1/2/3 = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into
VSSENSE, VIN and VINPROT
40
mA
IACTIVE1235
BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = 5 V from
BOOST, Total current into VSSENSE, VIN and VINPROT
31
mA
IACTIVE1235_noEXT
BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = open, Total
current into VSENSE, VIN and VINPROT
53
mA
ACTIVE total current consumption(2)
BUCK CONTROLLER (BUCK1)
VBUCK1
Adjustable output voltage range
VSense1_NRM
Internal reference voltage in operating
mode
VS1-2
VS1-2 for forward OC in CCM
ACS
Current-sense voltage gain
tOCBUCK1_BLK
RSTN and ERROR mode transition,
when overcurrent is detected for >
tOCBUCK1_BLK
tDEAD_BUCK1
Shoot-through delay, blanking time
ƒSWBUCK1
Switching frequency
DC
Duty cycle
VSENSE1 pin, load = 0 mA, Internal REF = 0.8 V
Maximum sense voltage VSENSE1 = 0.75 V (low duty cycle)
Minimum sense voltage VSENSE 1 = 1 V (negative current limit)
∆VCOMP1 / ∆ (VS1 - VS2)
3
11
–1%
1%
60
75
90
–65
–37.5
–23
4
8
12
1
25
ns
MHz
100
Maximum duty cycle
mV
ms
fOSC / 10
High-side minimum on time
V
ns
98.75%
EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGpeak
Gate driver peak current
VREG = 5.8 V
RDSON_DRIVER
Source and sink driver
IG current for external MOSFET = 200 mA, VREG = 5.8 V,
VBOOT1-PH1 = 5.8 V
VDIO1
Bootstrap diode forward voltage
IBOOT1 = –200 mA, VREG-BOOT1
0.6
5
0.8
A
10
Ω
1.1
V
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER
gmEA
Forward transconductance
AEA
Error amplifier DC gain
COMP1/2/3/5 = 0.8 V; source and sink = 5 µA, test in feedback
loop
0.9
m℧
60
dB
SYNCHRONOUS BUCK CONVERTER BUCK2/3
VSUP2/3
Supply voltage
VBUCK2/3
Regulated output voltage range
Iload = 0 to 2 A, VSUPx = VBUCK2/3 + Iload × 0.2 Ω
3
11
0.8
5.5
RDSON-HS
RDSON high-side switch
RDSON-LS
V
VBOOTx –PHx = 5.8 V
0.20
Ω
RDSON low-side switch
VREG = 5.8 V
0.20
Ω
High-side switch current limit
Static current limit test. In application L > 1 µH at IHS-Limit and
ILS-Limit to limit dI / dt
2.4
2.9
3.5
ILS-Limit
Low-side switch current limit
Static current limit test. In application L > 1 µH at IHS-Limit and
ILS-Limit to limit dI / dt
2
2.5
3
VSUPLkg
VSUP leakage current
VSUP = 10 V for high side, controller disabled, TJ = 100°C
1
2
ƒSWLBuck2/3
Buck switching frequency
VSense2/3
Feedback voltage
IHS-Limit
DCBUCK2/3
Duty cycle
tDEAD_BUCK2/3
Shoot-through delay
COMP2/3HTH
COMP2/3 input threshold low
COMP2/3LTH
COMP2/3 input threshold high
RTIEOFF COMP23
COMP2/3 internal tie-off
V
A
µA
fOSC/5
With respect to 800-mV internal reference
–1%
High-side minimum on time
1%
50
Maximum duty cycle
ns
99.8%
20
BUCK2/3 enabled. Resistor to VREG and GND, each
ns
0.9
1.5
VREG – 1.2
VREG – 0.3
V
130
kΩ
70
100
V
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
VDIO2 3
Bootstrap-diode forward voltage
TEST CONDITIONS
MIN
IBOOT1 = –200 mA, VREG-BOOT2, VREG-BOOT3
TYP
MAX
1.1
1.2
UNIT
V
V
BOOST CONVERTER
VBoost
Boost adjustable-output voltage range
Using 3.3-V input voltage, Ieak_switch ≤ 1 A
4.5
15
VBoost
Boost adjustable-output voltage range
Using 3.3-V input voltage Iloadmax = 20 mA, Ipeak_switch = 0.3 A
15
18.5
V
RDS-ON_BOOST
Internal switch on-resistance
VREG = 5.8 V
0.5
Ω
VSense5
Feedback voltage
With respect to 800-mV internal reference
fSWLBOOST
Boost switching frequency
DCBOOST
Maximum internal-MOSFET duty cycle
at fSWLBOOST
ICLBOOST
Internal switch current limit
0.3
–1%
1%
fOSC / 5
MHz
90%
1
1.5
A
LINEAR REGULATOR LDO
VSUP4
Device operating range for LDO
Recommended operating range
VLDO
Regulated output range
IOUT = 1 mA to 350 mA
VRefLDO
DC output voltage tolerance at
VSENSE4
Vstep1
VSense4
VDropout
3
7
V
0.8
5.25
V
VSENSE4 = 0.8 V (regulated at internal reference),
VSUP4 = 3 V to 7 V, IOUT = 1 mA to 350 mA
–2%
2%
Load step 1
VSENSE4 = 0.8 V (regulated at internal reference),
IOUT = 1 mA to 101 mA, CLDO = 6 to 50 µF, trise = 1 µs
–2%
2%
Feedback voltage
With respect to 800-mV internal reference
–1%
Dropout voltage
127
143
IOUT = 350 mA, TJ = 125°C
156
180
IOUT = 350 mA, TJ = 150°C
275
335
IOUT
Output current
VOUT in regulation
ILDO-CL
Output current limit
VOUT = 0 V, VSUP4 = 3 V to 7 V
PSRRLDO
Power-supply ripple rejection
1%
IOUT = 350 mA, TJ = 25°C
Vripple = 0.5 VPP, IOUT = 300 mA,
CLDO = 10 µF
mV
–350
–1
mA
–1000
–400
mA
Frequency = 100 Hz
60
Frequency = 4 kHz
50
Frequency = 150 kHz
25
dB
LDOns10-100
Output noise 10 Hz – 100 Hz
10-µF output capacitance, VLDO = 2.5 V
20
µV/√(Hz)
LDOns100-1k
Output noise 100 Hz – 10 kHz
10-µF output capacitance, VLDO = 2.5 V
6
µV/√(Hz)
CLDO
Output capacitor
Ceramic capacitor with ESR range, CLDO_ESR = 0 to 100 mΩ
50
µF
430
mV
60
V
6
LED AND HIGH-SIDE SWITCH CONTROL
VHSSENSE
Current-sense voltage
VINPROT – HSSENSE, high-side switch in current limit
VCMHSSENSE
Common-mode range for current
sensing
See VINPROT
VHSOL_TH
VINPROT – HSSENSE open load
threshold
VHSOL_HY
Open load hysteresis
10
18
28
mV
tHSOL_BLK
Open-load blanking time
70
100
140
µs
VHS SC
VINPROT – HSSENSE load short
detection threshold
Ramping positive
88
92.5
96
Ramping negative from load short condition
87
90
93
VHSSC_HY
VINPROT – HSSENSE short circuit
hysteresis
1
tHSS CL
Net time in current-limit to disable
driver
4
tS HS
Current-limit sampling interval
VHSCTRLOFF
Voltage at HSCTRL when OFF
VGS
Clamp voltage between HSSENSE –
HSCTRL
tON
Turn on time
VOS_HS
Overshoot during turnon
ICL_HSCTRL
HSCTRL current limit
RPU_HSCTRL
RPU_HSCTRLHSSENSE
10
370
400
4
Ramping negative
5
20
35
Ramping positive
26
38
50
5
6
100
7.7
Time from rising HSPWM until high-side switch in current limitation,
±5% settling
Time from rising HSPWM until high-side switch until voltage-clamp
between HSSENSE – HSCTRL active (within VGS limits)
% VHSSENSE
% VHSSENSE
VINPROT
–0.5
6.1
mV
30
VOS_HS = VINPROT - HSSENSE
ms
µs
VINPROT
V
8.5
V
30
µs
60
µs
400
mV
2
4.1
5
mA
Internal pullup resistors between
VINPROT and HSCTRL
70
100
130
kΩ
Internal pullup resistors between
HSCTRL and HSSENSE
70
100
130
kΩ
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
VI_high
High level input voltage
HSPWM, VIO = 3.3 V
VI_low
Low level input voltage
HSPWM, VIO = 3.3 V
VI_hys
Input voltage hysteresis
HSPWM, VIO = 3.3 V
fHS_IN
HSPWM input frequency
RSENSE
External sense resistor
CGS
External MOSFET gate source
capacitance
CGD
External MOSFET gate drain
capacitance
MIN
TYP
MAX
2
UNIT
V
0.8
V
150
500
mV
Design info, no device parameter
100
500
Hz
Design info, no device parameter
1.5
50
Ω
100
2000
pF
500
pF
REFERENCE VOLTAGE
VREF
Reference voltage
VREF-tol
Reference voltage tolerance
3.3
IREFCL
CVREF
REFns10-100
Output noise 10 Hz–100 Hz
2.2-µF output capacitance, IVREF = 5 mA
REFns100-1k
Output noise 100 Hz–10 kHz
2.2-µF output capacitance, IVREF = 5 mA
V
–1%
1%
Reference voltage current limit
10
25
Capacitive load
0.6
5
µF
20
µV/√(Hz)
6
µV/√(Hz)
VREF_OK
Reference voltage OK threshold
TREF_OK
Reference voltage OK deglitch time
IVREF = 5 mA
Threshold, VREF falling
Hysteresis
mA
2.91
3.07
3.12
V
14
70
140
mV
20
µs
10
SHUTDOWN COMPARATOR (TJ = –55°C TO +150°C)
IVT_REF = 20 µA. Measured as drop voltage with respect to VDVDD
1
17
500
IVT_REF = 600 µA. Measured as drop voltage with respect to
VDVDD. No VT_REF short-circuit detection.
200
420
1100
VT_REF = 0
0.6
1
1.4
mA
Threshold, VT_REF falling. Measured as drop voltage with respect
to VDVDD
0.9
1.2
1.8
V
VT_REF
Shutdown comparator reference
voltage
IVT_REFCL
Shutdown comparator reference
current limit
VVT_REF SH
VT_REF short circuit detection
VTTH-H
Input voltage threshold on VT, rising
edge triggers shutdown
This feature is specified by design to work down to –55°C.
0.48
0.50
0.52
VT_REF
VTTH-L
Input voltage threshold on VT, falling
voltage enables device operation
This feature is specified by design to work down to –55°C.
0.46
0.48
0.52
VT_REF
VTTOL
Threshold variation
VTTH-H – VT_REF / 2, VTTH-L – VT_REF / 2
Hysteresis
IVT_leak
Leakage current
VT_REFOV
VT_REF overvoltage threshold
130
TVT_REF_FLT
mV
–20
20
TJ = –20°C to +150°C
–400
–50
TJ = –55°C to –20°C
–200
–50
Threshold, VT_REF rising. Measured as drop voltage with respect
to VDVDD
0.42
Hysteresis
0.9
mV
1.2
100
mV
nA
V
mV
VT_REF fault deglitch time
Overvoltage or short condition on VT_REF
10
20
µs
VWAKE_ON
Voltage threshold to enable device
WAKE pin is a level sensitive input
3.3
3.7
V
tWAKE
Min. pulse width at WAKE to enable
device
VWAKE = 4 V to suppress short spikes at WAKE pin
10
20
µs
WAKE INPUT
VBAT UNDERVOLTAGE WARNING
VSSENSETH_L
VSSENSE falling-threshold low
SPI selectable, default after reset
4.3
4.7
V
VSSENSETH_H
VSSENSE falling-threshold high
SPI selectable
6.2
6.8
V
VSSENSE-HY
VSSENSE hysteresis
tVSSENSE_BLK
Blanking time
35
µs
LPM0 mode, VSSENSE 55 V
1
µA
LPM0 mode, VSSENSE 60 V
100
µA
25
mA
1.3
MΩ
IVSLEAK
IVSLEAK60
Leakage current at VSSENSE
IVSLEAK80
RVSSENSE
0.2
VVSENSE < VSSENSETH_xx → IRQ asserted
LPM0 mode, VSSENSE 80 V
Internal resistance from VSSENSE to
GND
10
5
VSSENSE = 14 V, disabled in LPM0 mode
0.7
1
V
VIN OVERVOLTAGE PROTECTION
VOVTH_H
VIN overvoltage-shutdown threshold 1
(rising edge)
Selectable with SPI
50
60
V
VOVTH_L
VIN overvoltage-shutdown threshold 2
(rising edge)
Selectable with SPI, default after reset
36
38
V
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
MIN
TYP
MAX
Threshold 1
TEST CONDITIONS
0.2
1.7
3
Threshold 2; default after reset
1.5
2
2.5
VOVHY
VIN overvoltage hysteresis
tOFF BLK-H
Overvoltage delay time
VIN > VOVTH_H → GPFET off
tOFF BLK-L
Overvoltage blanking time
VIN > VOVTH_L → GPFET off
1
10
UNIT
V
µs
20
µs
370
ms
WINDOW WATCHDOG
TESTSTART, TESTSTOP, VTCHECK , and RAMP mode:
Begins after entering each mode.
ACTIVE mode:
WD timeout begins with rising edge of RESN
ttimeout
Timeout
tWD
Watchdog window time
tWD_FAIL
Closed window time
tWD_BLK
WD filter time
VI_high
High level input voltage
WD, VIO = 3.3 V
VI_low
Low level input voltage
WD, VIO = 3.3 V
VI_hys
Input voltage hysteresis
WD, VIO = 3.3 V
Spread spectrum disabled
Spread spectrum enable
230
300
18
20
22
19.8
22
24.2
ms
tWD / 4
0.5
2
µs
V
150
0.8
V
500
mV
2.2
ms
RESET AND IRQ BLOCK
tRESNHOLD
RESN hold time
VRESL
Low level output voltage at RESN,
PRESN and IRQ
1.8
2
VIN ≥ 3 V, IxRESN = 2.5 mA
0
0.4
V
VRESL
Low level output voltage at RESN and
PRESN
VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA
0
0.4
V
IRESLeak
Leakage current at RESN, PRESN and
Vtest = 5.5 V
IRQ
1
µA
NRES
Number of consecutive reset events for
transfer to LPM0
tIRQHOLD
IRQ hold time
20
µs
tDR IRQ PRESN
Rising edge delay of IRQ to rising edge
of PRESN
2
µs
tDF RESN_PRESN
Falling edge delay of RESN to
PRESN / IRQ
2
µs
7
After VVSENSE < VSSENSETH for tVSSENSE_BLK
10
EXTERNAL PROTECTION
VCLAMP
Gate to source clamp voltage
VIN – GPFET, 100 µA
14
20
V
IGPFET
Gate turn on current
VIN = 14 V, GPFET = 2 V
15
25
µA
RDSONGFET
Gate driver strength
VIN = 14 V, turn off
25
Ω
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
TSDTH
Thermal shutdown
TSDHY
Hysteresis
tSD-BLK
Blanking time before thermal shutdown
TOTTH
Overtemperature flag
TOTHY
Hysteresis
tOT_BLK
Blanking time before thermal over
temperature
Junction temperature
160
175
°C
20
10
Overtemperature flag is implemented as local temp sensors and
expected to trigger before the thermal shutdown
150
°C
20
µs
165
°C
20
°C
10
20
µs
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
VMONTH_L
Voltage monitor reference, falling edge
REF = 0.8 V
90
92
94
%
VMONTH_H
Voltage monitor reference, rising edge
REF = 0.8 V
106
108
110
%
VMON_HY
Voltage monitor hysteresis
VVIOMON_TH
Undervoltage monitoring at VIO –
falling edge
VVIOMON_HY
UV_VIO hysteresis
tVMON_BLK
Blanking time between UV or OV
condition to RESN low
tVMONTHL_BLK
Blanking time between undervoltage
BUCK1/2/3 → ERROR mode LDO or BOOST → SPI bit set or turn
condition to ERROR mode transition or
off
corresponding SPI bit
tVMONTHL_BLK1
Blanking time between undervoltage
condition to ERROR mode transition
VIO only
10
20
µs
tVMONTHH_BLK1
Blanking time between overvoltage
condition to ERROR mode transition
BUCK1/2/3 → ERROR mode VIO has no OV protection
10
20
µs
12
2
3
%
3.13
V
20
µs
0.05
UV/OV = BUCK1/2/3 UV = VIO
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
tVMONTHH_BLK2
TEST CONDITIONS
Blanking time LDO and BOOST
LDO or BOOST (ACTIVE mode) → SPI bit set or turn off LDO
overvoltage condition to corresponding
(VTCHECK or RAMP mode) → ERROR mode
SPI bit or ERROR mode
MIN
TYP
20
MAX
UNIT
40
µs
GND LOSS
VGLTH-low
GND loss threshold low
GND to PGNDx
–0.31
–0.25
–0.19
V
VGLTH-high
GND loss threshold high
GND to PGNDx
0.19
0.25
0.31
V
tGL-BLK
Blanking time between GND loss
condition and transition to ERROR
state
5
20
µs
POWER-UP SEQUENCING
tSTART1
Soft start time of BOOST
From start until exceeding VMONTH_L + VMON_HY Level
0.7
2.7
ms
tSTART2
Soft start time of BUCK1/2/3 and LDO
From start until exceeding VMONTH_L + VMON_HY Level
0.5
2
ms
tSTART
Startup DVDD regulator
From start until exceeding VMONTH_L + VMON_HY Level
3
ms
tSEQ2
Sequencing time from start of BUCK1
to BUCK2 and BOOST
Internal SSDONE_BUCK1 signal
3
ms
tWAKE-RES
Startup time from entering
TESTSTART to RESN high
GPFET = IRFR6215
14
ms
tSEQ1
Sequencing time from start of BOOST
to BUCK3
Internal SSDONE_BOOST signal
4
ms
1
INTERNAL VOLTAGE REGULATORS (TJ = –55°C to +150°C)
VREG
Internal regulated supply
IVREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V and
EXTSUP = 6.3 V to 12 V
5.5
5.8
6.1
V
VEXTSUP-TH
Switch over voltage
IVREG = 0 mA to 50 mA and EXTSUP ramping positive,
ACTIVE mode
4.4
4.6
4.8
V
VEXTSUP-HY
Switch over hysteresis
100
200
300
mV
VREGDROP
IREG_CL
IREG_EXTSUP_CL
CVREG
Dropout voltage on VREG
Current limit on VREG
IVREG = 50 mA, EXTSUP = 5 V / VINPROT = 5 V and
EXTSUP = 0 V / VINPROT = 4 V
200
mV
EXTSUP = 0 V, VREG = 0 V
–250
–50
mA
EXTSUP ≥ 4.8 V, VREG = 0 V
–250
–50
mA
µF
Capacitive load
1.2
2.2
3.3
VREG rising
3.8
4
4.2
V
Hysteresis
350
420
490
mV
3.15
3.3
3.45
V
VREG-OK
VREG undervoltage threshold
VDVDD
Internal regulated low voltage supply
VDVDD UV
DVDD undervoltage threshold
DVDD falling
VDVDD OV
DVDD overvoltage threshold
DVDD rising
tDVDD OV
Blanking time from DVDD overvoltage
condition to shutdown mode transition
2.1
V
10
3.8
V
20
µs
GLOBAL PARAMETERS
RPU
Internal pullup resistor at CSN pin
70
100
130
kΩ
RPD
Internal pulldown resistor at pins:
HSPWM , SDI, SCK, WD, S2(3)
70
100
130
kΩ
RPD-WAKE
Internal pulldown resistor at WAKE pin
ILKG
Input pullup current at the VSENSE1–5
VTEST = 0.8 V
and VMON1–3 pins
fOSC
fspread
140
200
260
kΩ
–200
–100
–50
nA
Internal oscillator used for buck or
boost switching frequency
4.6
4.9
5.2
MHz
Spread-spectrum frequency range
0.8 × fOSC
fOSC
MHz
SPI
VI_high
High-level input voltage
CSN, SCK, SDI; VIO = 3.3 V
VI_low
Low-level input voltage
CSN, SCK, SDI; VIO = 3.3 V
VI_hys
Input voltage hysteresis
CSN, SCK, SDI; VIO = 3.3 V
VO_high
SDO-output high voltage
VIO = 3.3 V ISDO = 1 mA
VO_low
SDO-output low voltage
VIO = 3.3 V ISDO = 1 mA
CSDO
SDO capacitance
(1)
(2)
(3)
2
150
V
0.8
V
500
mV
3
V
0.2
V
50
pF
The quiescent current specification does not include the current flow through the external feedback resistor divider. Quiescent current
is non-switching current, measured with no load on the output with VBAT = 13 V.
Total current consumption measured on the EVM includes switching losses.
RAMP and ACTIVE only.
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7.6 SPI Timing Requirements
MIN
NOM
MAX
UNIT
tSPI
SCK period
240
ns
tSCKL
SCK low time
100
ns
tSCKH
SCK high time
100
ns
tFSIV
Time between falling edge of CSN and SDO output valid (FSI
bit)
Falling SDO < 0.8 V; Rising
SDO > 2 V
80
ns
tSDOV
Time between rising edge of SCK and SDO data valid
Falling SDO < 0.8 V; Rising
SDO > 2 V
55
ns
tSDIS
Setup time of SDI before falling edge of SCK
20
ns
tSDIH
Hold time for SDI after falling edge of SCK
20
ns
tHCS
Hold time of CSN after last falling edge of SCK
50
tSDOtri
Delay between rising edge of CSN and SDO tri-state
tmin2SPI
Minimum time between two SPI commands
ns
80
10
ns
µs
CSN
TSPI
tHcs
SCK
tFSIV
SDO
tSDOV
FSI
tSCKL
Bit15
tSDIS
SDI
tSCKH
tSDOtri
Bit14
Bit0
tSDIH
Bit15
Bit14
Bit0
Figure 7-1. SPI Timing
14
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7.7 Typical Characteristics
All parameters are measured on the TI EVM, unless otherwise specified. For efficiency measurement setup,
please see to SLVA610.
Buck 1 Characteristics
Figure 7-2. Reduction of Current Limit vs Duty Cycle
Buck 2 and 3 Characteristics
VSUP3 = 3.8 V, 25°C
VSUP3 = 3.3 V, 25°C
VSUP3 = 5 V, 25°C
VSUP3 = 3.8 V, 140°C
VSUP3 = 3.8 V, -40°C
810
808
VSUP2 = 5 V, 25°C
806
802
VSUP2 = 3.8 V, 140°C
804
VSUP2 = 3.8 V, -40°C
VSENSE3 (mV)
VSENSE2 (mV)
804
VSUP2 = 3.8 V, 25°C
802
800
798
796
800
798
796
794
794
792
792
790
790
0
0.5
1
1.5
2
0
Load Current (A)
0.5
1
1.5
2
Load Current (A)
Figure 7-3. Load Regulation Buck2 = 3.3 V EXTSUP Figure 7-4. Load Regulation Buck3 = 1.2 V EXTSUP
Pin Open
Pin Open
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805
805
804
25°C
804
803
-40°C
803
-40°C
140°C
140°C
802
VSENSE3 (mV)
802
VSENSE2 (mV)
25°C
801
800
799
801
800
799
798
798
797
797
796
796
795
795
2
4
6
8
10
2
12
4
6
8
10
12
VSUP3 (V)
VSUP2 (V)
Figure 7-5. Open-Load Line Regulation Buck2 = 3.3 Figure 7-6. Open-Load Line Regulation Buck3 = 1.2
V EXTSUP Pin Open
V EXTSUP Pin Open
10
6
9
5.5
5
8
4.5
4
I_VSUP3 (mA)
I_VSUP2 (mA)
7
6
5
4
3.5
3
2.5
2
3
25°C
25°C
1.5
-40°C
2
1
-40°C
0.5
140°C
125°C
1
0
0
3
5
7
9
11
2
4
6
VSUP2 (V)
Figure 7-7. Open-Load Supply Current Buck2 = 3.3
V EXTSUP Pin Open
10
12
Figure 7-8. Open-Load Supply Current Buck3 = 1.2
V EXTSUP Pin Open
801
802
800.5
801.5
801
800
VSENSE3 (mV)
VSENSE2 (mV)
8
VSUP3 (V)
799.5
799
800.5
800
799.5
798.5
VSUP2 = 3.8 V, NO LOAD
799
VSUP3 = 3.8 V, NO LOAD
798
-50
-30
-10
10
30
50
70
90
110
130
150
798.5
-50
-30
Temperature (°Celcius)
10
30
50
70
90
110
130
150
Temperature (°Celcius)
Figure 7-9. Buck2 = 3.3-V VSENSE2 vs
Temperature EXTSUP Pin Open
16
-10
Figure 7-10. Buck3 = 1.2-V VSENSE3 vs
Temperature EXTSUP Pin Open
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Boost Characteristics
0.81
0.81
0.805
VSENSE5 (V)
VSENSE5 (V)
0.805
0.8
0.8
0.795
0.795
0.79
0.79
0
3
3.2
3.4
3.6
3.8
0.1
0.2
0.3
0.4
0.5
4
Load Current (A)
VSUP5 (V)
Figure 7-11. Open-Load Line Regulation Boost = 5
V At 25°C Extsup Pin Open, Boost Supply Input =
3.8 V
Figure 7-12. Load Regulation Boost = 5 V At 25°C
Extsup Pin Open, Boost Supply Input = 3.8 V
805
804
803
VSENSE5 (mV)
802
801
800
799
798
797
796
795
-50
0
50
100
150
Temperature (°Celcius)
Figure 7-13. Boost = 5-V Vsense5 vs Temperature Extsup Pin Open, Input Supply = 3.8 V, 0.4 A Load
LDO Noise Characteristics
(2 × 3.3-µF output capacitance, LDO output = 2.5 V, VSUP4 = 3.8 V)
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10
9
Noise [LDO ON]
8
Noise [LDO OFF]
(Noisefloor)
NOISE (uV / sqrt [Hz])
7
6
5
4
3
2
1
0
10
100
1000
10000
Frequency (Hz)
Figure 7-14. LDO Noise Density
18
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8 Detailed Description
8.1 Overview
The device includes one high-voltage buck controller for pre-regulation combined with a two-buck and one-boost
converter for post regulation. A further integrated low-dropout (LDO) regulator rounds up the power-supply
concept and offers a flexible system design with five independent-voltage rails. The device offers a low power
state (LPM0 with all rails off) to reduce current consumption in case the system is constantly connected to the
battery line. All outputs are protected against overload and over temperature. An external PMOS protection
feature makes the device capable of sustaining voltage transients up to 80 V. This external PMOS is also used
in safety-critical applications to protect the system in case one of the rails shows a malfunction (undervoltage,
overvoltage, or overcurrent).
Internal soft-start ensures controlled startup for all supplies. Each power-supply output has an adjustable output
voltage based on the external resistor-network settings.
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8.2 Functional Block Diagram
IRQ
VBUCK1
VIO
EXTSUP
VINPROT
OV
Protection
DVDD
+
POR
UV
Monitoring
GND
VIN
DVDD
UV
Warning
GPFET
VINPROT
VSSENSE
VBAT
VEXTSUP-TH
5.8V
Bandgap1
Bandgap2
BOOT1
RESN
PRESN
WD
WAKE
VREG
VREG
RESET
/
Window
Watchdog
Digital
Logic
GU
PH1
Wake Up
circuit
GL
PGND1
CSN
COMP1
SPI
SDI
+
VREF
Bandgap3
DVDD
VT_REF
Short
Protection
VT
Shutdown
Comparator
VSUP2
VBUCK1
BOOT2
VBuck2
COMP2
HSSENSE
HSCTRL
VMON1
PH2
SMPS Voltage
Mode Control
GND
VBUCK1
S2
GND
LT
-
S1
VSENSE1
Voltage
Monitoring
Sync. Buck Converter
BUCK2
(low voltage)
+
VINPROT
SMPS Current
Mode Control
SDO
Sync. Buck Controller
BUCK1
(current mode)
SCK
LED Driver
HSPWM
PGND2
Voltage
Monitoring
VSENSE2
VMON2
VBUCK1
COMP5
Sync. Buck Converter
BUCK3
(low voltage)
Booster
LDO
(Low voltage)
PH5
SMPS Voltage
Mode Control
VSENSE5
+
-
VBuck3
COMP3
PGND3
Voltage
Monitoring
VSENSE3
VMON3
VLDO
VBUCK1
VSENSE4
Voltage
Monitoring
VSUP4
Voltage
Monitoring
LDO
VBooster
SMPS
Voltage
Mode
Control
VBUCK1
BOOT3
PH3
Charge
Pump
PGND5
VBOOST
VSUP3
Figure 8-1. Detailed Block Diagram
20
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8.3 Feature Description
8.3.1 Buck Controller (Buck1)
8.3.1.1 Operating Modes
Mode of Operation
Description
Normal Mode
(RAMP, ACTIVE)
Constant frequency current mode
Continuous or discontinuous mode
8.3.1.2 Normal Mode PWM Operation
The main buck controller operates using constant frequency peak current mode control. The output voltage is
programmable with external resistors.
The switching frequency is set to a fixed value of ƒSWBUCK1. Peak current-mode control regulates the peak
current through the inductor such that the output voltage VBUCK1 is maintained to its set value. Current mode
control allows superior line-transient response. The error between the feedback voltage VSENSE1 and the
internal reference produces an error signal at the output of the error amplifier (COMP1) which serves as target
for the peak inductor current. At S1–S2, the current through the inductor is sensed as a differential voltage and
compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at
VSENSE1, which causes COMP1 to rise or fall respectively, thus increasing or decreasing the current through
the inductor until the average current matches the load. In this way the output voltage VBUCK1 is maintained in
regulation.
Sense Resistor
VINPROT
L
RS
GU
HS
PWM
L
RL
RDCR
CDCR
PH
Gate
Drivers
Logic
DCR Sensing
VBUCK1
GL
LS
Current
Comparator
S1
VS1-S2, INT
VSLOPE
Current
Sensing
VS1-S2, EXT
S2
Slope
Compensation
gm
Error
Amp
Current Loop
(Inner Loop)
VSENSE1
C2
COMP1
R1
C1
Voltage Loop (Outer Loop)
Figure 8-2. Detailed Block Diagram Of Buck 1 Controller
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The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the
inductor current reaches its peak value as set by the voltage loop. Once the high external FET is turned OFF,
and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the
next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth period the duty
cycle is limited to 95% in order to charge the bootstrap capacitor at BOOT1. This allows a maximum duty cycle
of 98.75%.
The maximum value of COMP1 is clamped so that the maximum current through the inductor is limited to a
specified value. The BUCK1 controller output voltage is monitored by a central independent voltage-monitoring
circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition, BUCK1
is thermally protected with a dedicated temperature sensor.
8.3.2 Synchronous Buck Converters Buck2 And Buck3
Both regulators are synchronous converters operating with a fixed switching frequency ƒSW = 0.98 MHz. For
each buck converter, the output voltage is programmable with external resistors. The synchronous operation
mode improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216°
shift to BUCK3 to minimize input current ripple.
Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground.
In case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when
its current reaches IHS-Limit and the low-side FET is turned on until the end of the given cycle. When the current
limit is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is
forced low for eight cycles to prevent uncontrolled current build-up. In case the low-side current limit of ILS-Limit is
reached, for example, due an output short to VSUP2/3, the low-side FET is turned off until the end of the cycle. If
this is detected shortly after the high-low PWM transition (immediately after the low-side overcurrent comparator
blanking time), both FETs are turned off for eight cycles.
The output voltages of BUCK2/3 regulators are monitored by a central independent voltage-monitoring circuit,
which has an independent voltage-monitoring bandgap reference for safety reasons. In addition BUCK2 and
BUCK3 are thermally protected with a dedicated temperature sensor.
8.3.3 BOOST Converter
The BOOST converter is an asynchronous converter operating with a fixed switching frequency ƒSW = 0.98 MHz.
It switches in phase with BUCK1. At low load, the boost regulator switches to pulse skipping.
The output voltage is programmable with external resistors.
The internal low-side switch can handle maximum 1-A current, and is protected with a current limit. In case of
an overcurrent, the integrated cycle-by-cycle current-limit turns off the low-side FET when the current reaches
ICLBOOST until the end of the given cycle. When the current-limit is reached in the beginning of the cycle for five
consecutive cycles, the PWM is forced low for eight cycles to prevent uncontrolled current build-up.
The BOOST converter output voltage is monitored by a central independent voltage-monitoring circuit, which has
an independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE5 or VSENSE5
> VMONTH_H, the output is switched off and the BOOST_FAIL bit in the SPI PWR_STAT register is set. The
BOOST can be reactivated by setting BOOST_EN bit in the PWR_CONFIG register.
In addition, the BOOST converter is thermally protected with a dedicated temperature sensor. If TJ > TOTTH, the
BOOST converter is switched off and bit OT_BOOST in PWR_STAT register is set. Reactivation of the booster is
only possible if the OT_BOOST bit is 0, and the booster enable bit in the PWR_CONFIG register is set to 1.
8.3.4 Frequency-Hopping Spread Spectrum
The TPS65310A-Q1 features a frequency-hopping pseudo-random spectrum or triangular spreading
architecture. The pseudo-random implementation uses a linear feedback shift register that changes the
frequency of the internal oscillator based on a digital code. The shift register is designed in such a way that
the frequency shifts only by one step at each cycle to avoid large jumps in the buck and BOOST switching
frequencies. The triangular function uses an up-down counter. Whenever spread spectrum is enabled (SPI
command), the internal oscillator frequency is varied from one BUCK1 cycle to the next within a band of 0.8 x
fOSC ... fOSC from a total of 16 different frequencies. This means that BUCK3 and BOOST also step through 16
22
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frequencies. The internal oscillator can also change its frequency during the period of BUCK2, yielding a total of
31 frequencies for BUCK2.
8.3.5 Linear Regulator LDO
The LDO is a low drop out regulator with an adjustable output voltage through an external resistive divider
network. The output has an internal current-limit protection in case of an output overload or short circuit to
ground. In addition, the output is protected against overtemperature. If TJ > TOTTH, the LDO is switched off and
bit OT_LDO in PWR_STAT register is set. Reactivation of the LDO is only possible through the SPI by setting
the LDO enable bit in the PWR_CONFIG register to 1 if the OT_LDO bit is 0.
The LDO output voltage is monitored by a central independent voltage-monitoring circuit, which has an
independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE4 or VSENSE4
> VMONTH_H, the output is switched off and the LDO_FAIL bit in the SPI PWR_STAT register is set. The LDO can
be reactivated through the SPI by setting the LDO_EN bit in the PWR_CONFIG register. In case of overvoltage
in VTCHECK and RAMP mode, the GPFET is turned off and the device changes to ERROR mode.
8.3.6 Gate Driver Supply
The gate drivers of the BUCK1 controller, BUCK2 and BUCK3 converters and the BOOST converter are
supplied from an internal linear regulator. The internal linear regulator output (5.8-V typical) is available at the
VREG pin and must be decoupled using a typical 2.2-μF ceramic capacitor. This pin has an internal current-limit
protection and must not be used to power any other circuits.
The VREG linear regulator is powered from VINPROT by default when the EXTSUP voltage is lower than 4.6 V
(typical).
If the VINPROT is expected to go to high levels, there can be excessive power dissipation in this regulator when
using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin,
which can be connected to a supply lower than VINPROT but high enough to provide the gate drive. When
EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP
as its input to provide this advantage. This automatic switch-over to EXTSUP can only happen once the
TPS65310A-Q1 device reaches ACTIVE mode. Efficiency improvements are possible when one of the switching
regulator rails from the TPS65310A-Q1 device, or any other voltage available in the system is used to power
EXTSUP. The maximum voltage that must be applied to EXTSUP is 12 V.
8.4 Device Functional Modes
8.4.1 RESET
RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in Table 8-1
are valid. RESN active (low) is extended for tRESNHOLD after a reset is triggered. RESN is the main processor
reset and also asserts PRESN as a peripheral signal.
PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at WD
pin).
RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and
power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages
the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and
PRESN are asserted, even if VIN falls below VPOR or the device is in SHUTDOWN mode.
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Loss of LPM clock
Thermal Shutdown
RESN
WD_RESET
POR
Loss of GND
Mono
Flop
•1
Voltage Monitor Buck1-3 fail
Voltage Monitor VIO fail
•1
PRESN
RESET
Over Temperature BUCK1-3, VREG
Over Voltage LDO
S
WD Trigger
Q
R
Over-Current BUCK1
Figure 8-3. RESET Functionality
Table 8-1. RESET Conditions
RESET CONDITIONS
POR, Loss of LPM Clock, and Thermal Shutdown
The device reinitializes all registers with their default values. Error counter
is cleared.
Voltage Monitor BUCK 1-3
Input voltage at VMON1-3 pin out-of-bounds:
VVMON1-3 < VMONTH_L or VVMON1-3 > VMONTH_H
Over Voltage LDO
Vsense4 > VMONTH_H
Voltage Monitor VIO
Input voltage at VIO pin out-of-bounds: VVIO < VVIOMON TH
Loss of GND
Open at PGNDx or GND pin
OT BUCK1-3, VREG
Overtemperature on BUCK1–3 or VREG
WD_RESET
Watchdog window violation
Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by
one. After a reset is consecutively triggered NRES times, the device transfers to the LPM0 state, and the EC is
reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can
be put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated
again by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device
in case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal
shutdown or a loss of LPM clock. Once the device is locked, a voltage below VPOR at the VIN pin or a thermal
shutdown condition are the only ways to unlock the device.
8.4.2 Soft Start
The output voltage slopes of BUCK, BOOST and LDO regulators are limited during ramp-up (defined by tSTARTx).
During this period the target output voltage slowly settles to its final value, starting from 0 V. In consequence,
regulators that offer low-side transistors (BUCK1, BUCK2 and BUCK3) actively discharge their output rails to the
momentary ramp-value if previously charged to a higher value.
8.4.3 INIT
Coming from a power-on reset the device enters INIT mode. The configuration data from the EEPROM is loaded
in this mode. If the checksum is valid and the internal VREG monitor is indicating an undervoltage condition
(self-test VREG comparator), the device enters TESTSTART.
8.4.4 TESTSTART
TESTSTART mode is entered:
• After the INIT state (coming from power on)
• After detecting that VT > VTTH-H
• After ERROR mode and the fail condition is gone
• After a wake command in LPM0
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In this mode the OV/UV comparators of BUCK1-3, BOOST, LDO and VIO are tested. The test is implemented in
such a way that during this mode all comparators have to deliver a 1 (fail condition). If this is the case the device
enters TESTSTOP mode.
If this is not the case, the device stays in TESTSTART. If the WAKE pin is low, the device enters LPM0 after
ttimeout. If the WAKE pin is high, the part stays in TESTSTART.
8.4.5 TESTSTOP
In this mode the OV/UV comparators are switched to normal operation. It is expected that only the UV
comparators give a fail signal. In case there is an OV condition on any rail or one of the rails has an
overtemperature the device stays in TESTSTOP. If the WAKE pin is low the device enters LPM0 mode after
ttimeout. If the WAKE pin is high, the part stays in TESTSTOP. If there is no overvoltage and overtemperature
detected, the part enters VTCHECK mode.
8.4.6 VTCHECK
VTCHECK mode is used to:
1. Switch on the external GPFET in case VIN < VOVTH_L
2. Turn on the VREG regulator and VT_REF
3. Check if the voltage on pin VT < VTTH-L
4. Check if the SMPS clock is running correctly
5. Check if the VREG,VT_REF exceeds the minimum voltage
If all checks are valid the part enters the RAMP state. In case the device is indicating a malfunction and the
WAKE pin is low, the device enters LPM0 after ttimeout to reduce current consumption.
In case the voltage monitors detect an overvoltage condition on BUCK1-3/LDO, a loss of GND or an
overtemperature condition on BUCK1-3 / VREG the device enters ERROR mode and the error counter is
increased.
8.4.7 RAMP
In this mode the device runs through the power-up sequencing of the SMPS rails (see Power-Up Sequencing).
8.4.8 Power-Up Sequencing
After the power-up sequence (described in Figure 8-4), all blocks are fully functional. BUCK1 starts first. After
tSEQ2 elapses and BUCK1 is above the undervoltage threshold, BUCK2 and BOOST start. BUCK3 and VREF
start one tSEQ1 after BUCK2. After the release of RESN pin, the µC can enable the LDO per SPI by setting bit 4
LDO_EN in PWR_CONFIG register to 1 (per default, this LDO_EN is set to 0 after each reset to the µC).
In case any of the conditions listed below happen during power-up sequencing, the device enters ERROR mode
and the error counter (EC) is increased:
• Overtemperature on BUCK1-3 or VREG
• Overvoltage on BUCK1-3 or LDO
• Overcurrent on BUCK1
• SMPS clock fail
• VT_REF/VREG undervoltage
• Loss of GND
In case VT > VTTH-H, the device transitions to TESTSTART.
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WakeUp event through WAKE pin
VPOR
VIN
tSTART
VINPROT
VREG-OK / VVT_REF_SH
VREG/
VT_REF
VMONTH_L + VMON_HY
BUCK1
BUCK1 > VMONTH_L + VMON_HY AND tSEQ2 elapsed before BUCK2 and BOOST are enabled
tSTART2
VMONTH_L + VMON_HY
tSEQ2
BOOSTER
tSTART1
VMONTH_L + VMON_HY
BUCK2
tSTART2
VREF_OK
VREF
VMONTH_L + VMON_HY
BUCK3
LDO enabled through SPI by PC
tSEQ1
tSTART2
VMONTH_L + VMON_HY
LDO
tSTART2
tRESNHOLD
RESN
tWAKE-RES
WD
PRESN
Only when device
is in ACTIVE state
With the device in LPM0 mode, the start point of VREG/VT_REF is with the rising edge of WAKE. When input
voltage is first applied, the rising edge of the VIN pin initiates the start-up sequence even if WAKE is low, and
enters LPM0 mode if WAKE remains low through NRES timeout events.
Figure 8-4. Power-Up Sequencing
After the power-up sequence is completed (except LDO) without detecting an error condition, the device enters
ACTIVE mode.
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8.4.9 Power-Down Sequencing
There is no dedicated power-down sequencing. All rails are switched off at the same time. The external
FETs of BUCK1 are switched off and the outputs of BUCK2/3/BOOST (PHx) and the LDO are switched in a
high-impedance state.
8.4.10 Active
This is the normal operating mode of the device. Transitions to other modes:
→ ERROR
The device is forced to go to ERROR in case of:
• Any RESET event (without watchdog reset)
• VREG/VREF/VT_REF below undervoltage threshold
• SMPS clock fail
During the transition to ERROR mode the EC is incremented.
→ LOCKED
In case a dedicated SPI command (SPI_LOCK_CMD) is issued.
→ TESTSTART
The device moves to TESTSTART after detecting that VT < VTTH-L.
→ LPM0
The device can be forced to enter LPM0 with a SPI LPM0 command. During this transition the EC is
decremented.
If the EC reaches the NRES value, the device transitions to LPM0 mode and EC is cleared. Depending on the
state of the WAKE pin, the device remains in LMP0 (WAKE pin low) or restart to TESTSTART (WAKE pin high).
To indicate the device entered LPM0 after EC reached NRES value, a status bit EC_OF (error counter overflow,
SYS_STAT bit 3) is set. The EC_OF bit is cleared on read access to the SYS_STAT register.
A watchdog reset in ACTIVE mode only increases the EC, but it does not change the device mode.
8.4.11 ERROR
In this mode all power stages and the GPFET are switched off. The devices leave ERROR mode and enter
TESTSTART if:
• All rails indicate an undervoltage condition
• No GND loss is detected
• No overtemperature condition is detected
When the EC reaches the NRES value, the device transitions to LPM0 and the EC is cleared. To indicate the
device entered LPM0 after EC reached NRES, a status bit EC_OF (error counter overflow, SYS_STAT bit 3) is
set. The EC_OF bit is cleared on read access to the SYS_STAT register.
8.4.12 LOCKED
Entering this mode disables the device. The only way to leave this mode is through a power-on reset, thermal
shutdown, or the loss of an LPM clock.
8.4.13 LPM0
Low-power mode 0 is used to reduce the quiescent current of the system when no functionality is needed. In this
mode the GPFET and all power rails except for DVDD are switched off.
In case a voltage > VWAKE_ON longer than tWAKE is detected on the WAKE pin, the part switches to TESTSTART
mode.
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8.4.14 Shutdown
The device enters and stays in this mode, as long as TJ > TSDTH - TSDHY or VIN < VPOR or DVDD under or
overvoltage, or loss of low power clock is detected. Leaving this mode and entering INIT mode generates an
internal POR.
8.4.14.1 Power-On Reset Flag
The POR flag in the SYS_STAT SPI register is set:
• When VIN is below the VPOR threshold
• System is in thermal shutdown
• Over or undervoltage on DVDD
• Loss of low power clock
8.4.15 Wake Pin
Only when the device is in LPM0 mode, it can be activated by a positive voltage on the WAKE pin with a
minimum pulse width tWAKE. A valid wake condition is latched. Normal deactivation of the device can only occur
through the SPI Interface by sending an SPI command to enter LMP0. Once in LMP0, the device stays in LPM0
when the WAKE pin is low, or restarts to TESTSTART when the WAKE pin is high.
The WAKE pin has an internal pulldown resistance RPD-WAKE, and the voltage on the pin is not allowed to
exceed 60 V. A higher voltage compliance level in the application can be achieved by applying an external series
resistor between the WAKE pin and the external wake-up signal.
The device cannot be re-enabled by toggling the WAKE pin when the device is in LOCKED state (by SPI
command).
28
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PowerOn
Reset
VIN > VPOR
(EC==0)
VT>VTTH-H (if enabled)
VT_ref_ok = µ1¶
& VT TOTTH
(BUCK1-3,VREG)
OR vreg_ok = µ0¶
OR VT_ref_ok = µ0¶
OR no SMPS clock
OR BUCK1 OC
OR GND LOSS
(EC++)
& Tj < TOTTH
Timeout**
& WAKE
pin low
INIT
TESTSTOP
CRC=O.K.
& EE ready
& Vreg_ok = 0
READY****
UV and OV
Timeout**
& WAKE
pin low
Independet voltage
monitors
& VIO
Timeout**
& WAKE
pin low
OV (BUCK1, LDO)
OR Tj > TOTTH
(BUCK1-3,VREG)
OR GND LOSS
(EC++)
Voltage Monitors < VMONTHL
& Tj < TOTTH
TESTSTART
ERROR
EC=NRES (ECm0, EC_OFm )
Timeout**
& WAKE
pin low
WD Reset
(EC++)
VT>VTTH-H
Wake
(WAKE pin
high)
(if enabled)
EC=NRES
(ECm0, EC_OFm )
OR SPI LPM0 CMD
(EC--)
ACTIVE
All RESET events*** (w/o WD)
OR vreg_ok = µ0¶
OR vref_ok = µ0¶
OR VT_REF_ok = µ0¶
OR no SMPS clock
(EC++)
LPM0
SPI LOCK CMD
LOCKED
Tj>TSDTH OR VIN < VPOR
OR DVDD UV/OV
OR loss of low power clock
* GPFET is turned on in VTCHECK, RAMP, ACTIVE and if
VIN VTTH is detected on the VT pin, the
main switch (external PMOS driven by GPFET) is switched off. This functionality can be used to monitor over
and under temperature (using a NTC resistor) to avoid operation below or above device specifications.
If the voltage at VT_REF falls below VVT_REF SH while the shutdown comparator is enabled, an ERROR transition
occurs. The shutdown comparator is enabled in VTCHECK state, and can be turned off by SPI. Disabling the
comparator saves power by also disabling the VT_REF output.
8.4.25 LED And High-Side Switch Control
This module controls an external PMOS in current-limited high-side switch.
The current levels can be adjusted with an external sense resistor. Enable and disable is done with the HS_EN
bit. The switch is controlled by the HSPWM input pin. Driving HSPWM high turns on the external FET.
The device offers an open load diagnostic indicated by the HS_OL flag in the SPI register PWR_STAT. Open
load is also indicated in case the voltage on VINPROT–VSSENSE does not drop below the threshold when
PWM is low (self-test).
A counter monitors the overcurrent condition to detect the risk of overheating. While HSPWM = high and HS_EN
= high the counter is incremented during overcurrent conditions, and decremented if the current is below the
overcurrent threshold at a sampling interval of tS HS (shown in Figure 8-9). When reaching a net current limit
time of tHSS CL, the driver is turned off and the HS_EN bit is cleared. This feature can be disabled by SPI bit
HS_CLDIS. When HS_EN is cleared, the counter is reset.
VINPROT
VINPROT
HSPWM
VHSSENSE
VHSOL_TH
OL
HSSENSE
VHS_SC
HSCTRL
SC
ECU
Connector
Figure 8-8. High-Side Control Circuit
32
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VHSPWM
PWM
VVINPROT - VHSSENSE
VHSSENSE
VHS_SC
countermax ) WHSS_CL
HS_EN
HS_CLDIS
Figure 8-9. HS Overcurrent Counter
Note
In case the LED or High-Side Switch Control is not used in the application, HSSENSE must be
connected to VINPROT
8.4.26 Window Watchdog
WD in Operating Mode:
The WD is used to detect a malfunction of the MCU and DSP. Description:
• Timeout trigger mode with long timing starts on the rising edge at RESN
• Window trigger mode with fixed timing after the first and each subsequent rising edge at the WD pin
• Watchdog is triggered by rising edge at the WD pin
A watchdog reset happens by:
• A trigger pulse outside the WD trigger open window
• No trigger pulse during window time
After the RESN pin is released (rising edge) the DSP and MCU must trigger the WD by a rising edge on the WD
pin within a fixed time ttimeout. With this first trigger, the window watchdog functionality is released.
Start of tWD time with a
rising edge of WD
VWD
WD Trigger fail
WD Trigger open window
tWD_FAIL_min
t
tWD_FAIL_max
tWD1_min
tWD_min
tWD_max
Figure 8-10. WD Window Description
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8.4.27 Timeout In Start-Up Modes
A timer is used to limit the time during which the device can stay in each of the start-up modes: TESTSTART,
TESTSTOP, VTCHECK and RAMP. If the device enters one of these start-up modes and VIN or VT is not in a
proper range, the part enters LPM0 after ttimeout is elapsed and the WAKE pin is low.
8.5 Programming
8.5.1 SPI
The SPI provides a communication channel between the TPS65310A-Q1 device and a controller. The
TPS65310A-Q1 device is always the peripheral. The processor/MCU is always the controller . The SPI controller
selects the TPS65310A-Q1 device by setting CSN (chip select) to low. SDI (peripheral in) is the data input, SDO
(peripheral out) is the data output, and SCK (serial clock input) is the SPI clock provided by the controller. If chip
select is not active (high), the data output SDO is high impedance. Each communication consist of 16 bits.
1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])
1 bit R/W; read = 0 and write = 1
6 bits CMD identifier
8 bits data
Bit15
Bit14
Parity
R/W
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
CMD_ID5 CMD_ID4 CMD_ID3 CMD_ID2 CMD_ID1 CMD_ID0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 8-11. SPI Bit-Frame
Each command is valid if:
• A valid CMD_ID is sent
• The parity bit (odd) is correct
• Exactly 16 SPI clocks are counted between falling and rising edge of CSN
The response to each controller command is given in the following SPI cycle. The response address is the
CMD_ID of the previous sent message and the corresponding data byte. The response data is latched with the
previous cycle such that a response to a write command is the status of the register before the write access.
(Same response as a read access.) The response to an invalid command is the original command with the
correct parity bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication
(CMD_ID = 0x03). Write access to a read-only register is not reported as an SPI error and is treated as a read
access. The initial answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.
8.5.1.1 FSI Bit
The peripheral transmits an FSI bit between the falling edge of CSN and the rising edge of SCK. If the SDO line
is high during this time, a failure occurred in the system and the MCU must use the PWR_STAT to get the root
cause. A low level of SDO indicates normal operation of the device.
The FSI bit is set when: PWR_STAT ! = 0x00, or (SYS_STAT and 0x98) ! = 0x00, or SPI_STAT ! = 0x00. The FSI
is cleared when all status flags are cleared.
8.6 Register Maps
8.6.1 Register Description
Table 8-2. Register Description
CMD_ID
Name
Bit7
Bit6
Bit5
Bit4
Bit3
0x00
NOP
0x03
SPI_SCK_FAIL
0x11
LPM0_CMD
0xAA
0x12
LOCK_CMD
0x55
34
Bit2
Bit1
Bit0
SCK[2]
SCK[1]
SCK[0]
0x00
1
0
0
SCK_OF
SCK[3]
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Table 8-2. Register Description (continued)
CMD_ID
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x21
PWR_STAT
BUCK_FAIL
VREG_FAIL
OT_BUCK
OT_LDO
OT_BOOST
LDO_FAIL
BOOST_FAIL
HS_OL
0x22
SYS_STAT
WD
POR
TestMode
SMPCLK_FAIL
EC_OF
0x23
SPI_STAT
0x24
COMP_STAT
0x29
Serial Nr 1
0x2A
Serial Nr 2
Bit [15:8]
0x2B
Serial Nr 3
Bit [23:16]
0x2C
Serial Nr 4
Bit [31:24]
0x2D
Serial Nr 5
Bit [39:32]
0x2E
Serial Nr 6
0x2F
DEV_REV
0x31
PWR_CONFIG
0x32
DEV_CONFIG
0x33
CLOCK_CONFIG
BUCK3-1
EC2
EC1
EC0
CLOCK_FAIL
CMD_ID FAIL
PARITY FAIL
BUCK3-0
BUCK2-1
BUCK2-0
Bit [7:0]
Bit [47:40]
Major3
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
HL_CLDIS
VT_EN
RSV
RSV
SS_EN
SS_MODE
F4
F3
F2
F1
F0
F_EN
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2 NOP0X00
Figure 8-12. NOP0X00
NOP 0x00
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
After RESET
Read
0
0
0
0
0
0
0
0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.1 SPI_SCK_FAIL 0x03
Figure 8-13. SPI_SCK_FAIL 0x03
SPI_SCK_FAIL 0x03
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
0
0
0
0
0
Default after
RESET
Read
1
0
0
SCK_OF
SCK[3]
SCK[2]
SCK[1]
SCK[0]
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Between a falling and a rising edge of CSN, the number of SCK was greater than 16.
SCK_OF
4
0:
1:
Number of SCK cycles was > 16
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
SCK[3:0]
3:0
Description
The number of rising edges on SCK between a falling and a rising edge of CSN minus 1. Saturates at 0xF if
16 or more edges are received.
Comment: This flag is cleared after its content is transmitted to the controller.
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8.6.2.2 LPMO_CMD 0x11
Figure 8-14. LPMO_CMD 0x11
LPM0_CMD 0x11
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Write
0xAA
This command is used to send the device into LPM0 mode.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.3 LOCK_CMD 0x12
Figure 8-15. LPMO_CMD 0x12
LOCK_CMD 0x12
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Write
0x55
Sending a lock command (0x55) brings the device into LOCK mode. Only a POR brings the device out of this state.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.4 PWR_STAT 0x21
Figure 8-16. PWR_STAT 0x21
PWR_STAT 0x21
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Read
BUCK_FAIL
VREG_FAIL
OT_BUCK
OT_LDO
OT_BOOST
LDO_FAIL
BOOST_FAIL
HS_OL
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Default after
POR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
BUCK_FAIL
7
Description
BUCK power fail flag
0:
1:
Power stages shutdown detected caused by OC BUCK1, UV, OV, loss of GND (BOOST + all bucks)
BUCK_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
Internal voltage regulator too low
VREG_FAIL
6
0:
1:
VREG fail
VREG_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
OT_BUCK
5
Description
BUCK1-3 overtemperature flag
0:
1:
36
IC power stages shutdown due to overtemperature
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Bit Name
Bit No.
Description
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
OT_LDO
4
Description
LDO overtemperature flag
0:
1:
LDO shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
BOOST overtemperature flag
OT_BOOST
3
0:
1:
BOOST shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
LDO_FAIL
2
Description
LDO under or overvoltage flag
0:
1:
LDO out of regulation
LDO_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag is transmitted to the controller.
Bit Name
Bit No.
BOOST_FAIL
1
Description
Booster under or overvoltage flag or loss of GND
0:
1:
Booster out of regulation
BOOST_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag was transmitted to the controller.
Bit Name
Bit No.
Description
High-side switch open load condition
HS_OL
0
0:
1:
Open load at high side
Bit indicates current OL condition of high side (no flag)
8.6.2.5 SYS_STAT 0x22
Figure 8-17. SYS_STAT 0x22
SYS_STAT 0x22
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
1
Read
WD
POR
Testmode
SMPCLK_FAIL
0
EC2
EC1
EC0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Default after
POR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Watchdog reset flag
WD
7
0:
1:
Last reset caused by watchdog
Comment: This flag is cleared after its content is transmitted to the controller.
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Bit Name
Bit No.
Description
Power-on reset flag
POR
6
0:
1:
Last reset caused by a POR condition
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
If this bit is set, the device entered test mode
Testmode
5
0:
1:
Device in Testmode
Comment: This flag is cleared after its content is transmitted to the controller and the device left the test mode.
Bit Name
Bit No.
SMPCLK_
FAIL
4
Description
If this bit is set, the clock of the switch mode power supplies is too low.
0:
Clock OK
1:
Clock fail
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
Actual error flag counter
EC [2:0]
0-2
0:
-
1:
-
*Error Counter is only deleted with a POR
8.6.2.6 SPI_STAT 0x23
Figure 8-18. SPI_STAT 0x23
SPI_STAT 0x23
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default after RESET
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
CLOCK_FAIL
CMD_ID FAIL
PARITY FAIL
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
CLOCK_FAIL
2
Description
Between a falling and a rising edge of CSN, the number of SCK does not equal 16
0:
1:
Wrong SCK
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
Last received CMD_ID in a reserved area
CMD_ID FAIL
1
0:
1:
Wrong CMD_ID
Comment: This flag is cleared after its content is transmitted to the controller and is not set if the number of SCK cycles is incorrect.
Bit Name
Bit No.
Description
Last received command has a parity bit failure
PARITY_FAIL
0
0:
1:
38
Parity bit error
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Bit Name
SLVSC15H – MAY 2013 – REVISED DECEMBER 2021
Bit No.
Description
Comment: This flag is cleared after its content is transmitted to the controller and is not set if the number of SCK cycles is incorrect.
8.6.2.7 COMP_STAT 0x24
Figure 8-19. COMP_STAT 0x24
COMP_STAT 0x24
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default after
RESET
0
0
0
0
0
1
1
0
Read
0
0
0
0
BUCK3-1
BUCK3-0
BUCK2-1
BUCK2-0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Register to read back the actual BUCK2 and BUCK3 compensation settings on COMP2 and COMP3. 0x1 ≥ 0 V 0 x 2 ≥ VREG 0 x 3 ≥ open
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.8 DEV_REV 0x2F
Figure 8-20. DEV_REV 0x2F
DEV_REV 0x2F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
After RESET
Major3
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
Read
Major3
Major2
Major1
Major0
Minor3
Minor2
Minor1
Minor0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
Hard coded device revision can be read from this register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.9 PWR_CONFIG 0x31
Figure 8-21. PWR_CONFIG 0x31
PWR_CONFIG 0x31
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Default after RESET
0
1
1
0
1
0
0
Bit0
0
Read
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
Write
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
This register contains all power rail enable bits.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
BUCK2 enable flag
BUCK2_EN
6
0:
1:
Enable BUCK2
After reset, BUCK2 is enabled
Bit Name
Bit No.
Description
BUCK3 enable flag
BUCK3_EN
5
0:
1:
Enable BUCK3
After reset, BUCK3 is enabled
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Bit Name
Bit No.
Description
LDO enable flag
LDO_EN
4
0:
1:
LDO enabled
After reset, LDO is disabled
Bit Name
Bit No.
Description
BOOST enable
BOOST_EN
3
0:
1:
BOOST enabled
After reset, BOOST is enabled
Bit Name
Bit No.
HS_EN
2
Description
LED and high-side switch enable
0:
High side disabled
1:
High side enabled
After reset, high side is disabled
Bit Name
Bit No.
Description
Protection FET overvoltage shutdown
GPFET_OV_HIGH
1
0:
Protection FET switches off at VIN > VOVTH-L
1:
Protection FET switches off at VIN > VOVTH-H
After reset, the lower VIN protection threshold is enabled
Bit Name
Bit No.
Description
VSSENSE IRQ low voltage interrupt threshold select
IRQ_THRES
0
0:
Low threshold selected (VSSENSETH_L)
1:
High threshold selected (VSSENSETH_H)
After reset, the lower VBAT monitoring threshold is enabled
8.6.2.10 DEV_CONFIG 0x32
Figure 8-22. DEV_CONFIG 0x32
DEV_CONFIG 0x32
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default after RESET
0
0
0
0
0
1
1
0
Read
0
0
0
0
0
VT_EN
RSV
RSV
Write
d.c.
d.c.
d.c.
d.c.
d.c.
VT_EN
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
LED and high-side switch current limit counter disable bit
HS_CLDIS
3
Bit Name
Bit No.
VT_EN
2
0:
LED and high-side switch current limit counter enabled
1:
LED and high-side switch current limit counter disabled
Description
VT enable bit
40
0:
VT monitor disabled
1:
VT monitor enabled
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Bit Name
SLVSC15H – MAY 2013 – REVISED DECEMBER 2021
Bit No.
Description
The VT monitor cannot be turned on after it was turned off. Turn on only happens during power up in the VTCHECK state.
Bit Name
Bit No.
RSV
1
Description
Voltage reference enable bit
Bit Name
Bit No.
RSV
0
0:
not recommended setting
1:
default setting
Description
Reserved - keep this bit at 1
0:
default setting
1:
not recommended setting
8.6.2.11 CLOCK_CONFIG 0x33
Figure 8-23. CLOCK_CONFIG 0x33
CLOCK_CONFIG 0x33
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
1
0
0
0
0
Read
F_EN
SS_EN
SS_MODE
F4
F3
F2
F1
F0
Write
F_EN
SS_EN
SS_MODE
F4
F3
F2
F1
F0
Default after
RESET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
F_EN
7
Description
Frequency tuning enable register
Bit Name
0:
Off – Setting of Bit4…Bit0 are not effective, setting of Bit6 and Bit5 become effective
1:
On – Setting of Bit4…Bit0 become effective, setting of Bit6 and Bit5 are not effective
Bit No.
Description
Spread spectrum mode enable
SS_EN
6
0:
Spread spectrum option for all switching regulators disabled
1:
Spread spectrum option for all switching regulators enabled (only when F_EN = 0)
When enabled, the switching frequency of BUCK1, BUCK2, BUCK3 and BOOST is modulated between 0.8 × fosc and fosc
Bit Name
Bit No.
SS_MODE
5
Description
Spread spectrum mode select (effective only when F_EN = 0)
0:
Pseudo random
1:
Triangular
Bit Name
Bit No.
F4, F3, F2, F1, F0
4-0
Description
Frequency tuning register (effective only when F_EN = 1)
0x10 is default value, trim range is 25% for 0x00 setting to –20% for 0x1F setting. Frequency tuning influences the switching frequency of
BUCK1, BUCK2, BUCK3 and BOOST as well as the watchdog timing.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS65310A-Q1 device is a multi-rail power supply including one buck controller, two buck converters, one
boost converter and one linear regulator (LDO). The buck controller is typically used to convert a higher car
battery voltage to a lower DC voltage which is then used as pre-regulated input supply for the buck converters,
boost converter, and the linear regulator. Use the following design procedure and application example to select
component values for the TPS65310A-Q1 device.
9.2 Typical Applications
9.2.1 Buck Controller 1
D1
4 V to 40 V (typ. 12 V)
VINPROT
PF
9
PGND1
14
COMP1
18
TPS65310A-Q1
Q3
R3
S2
16
VSENSE1
19
VMON1
17
VBUCK1
R1
R2
15
C1
47 pF
0.1 PF
C2
S1
nF
8.25 k
VBUCK1
50 PF
13
PH
GL
60.4 k
12
16 k:
PH1
Q2
PF
11
60.4 k 22 m:
GU
16 k:
10
C3
BOOT1
0.1 PF
VREG
8
EXTSUP
4
VINPROT
3
GPFET
2
VSSENSE
VIN
1
0.1 PF
10 k:
VBAT
Figure 9-1. Buck Controller Schematic
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
42
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
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Table 9-1. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage (VBUCK1)
3.8 V
Maximum output current (Imax_peak_coil)
2.5 A
Load Step ΔIOUT
1.25A
Output current ripple IL_ripple
500 mA
Output voltage ripple
3 mV
Allowed voltage step on output ΔVOUT
0.228 (or 6%)
Switching frequency (fSWBUCK1)
490 kHz
Bandwidth (FBW)
≈ 60 kHz
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
A resistor divider from the output node to the VSENSE1 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with 16 kΩ for the R1 resistor and use Equation 1 to calculate R2 (see
Figure 9-1).
R2 =
R1 ´ (VBUCK1 - 0.8 V)
0.8 V
(1)
Therefore, for the value of VBUCK1 to equal to 3.8V, the value of R2 must be 60.4 kOhms.
For voltage monitoring of the BUCK1 output voltage, placing an additional resistive divider with the exact same
values from the output node to the VMON1 pin is recommended for safety reasons (see Figure 9-1). If no safety
standard must be fulfilled in the application, the VMON1 pin can be directly connected to VSENSE1 pin without
the need for this additional resistive divider.
9.2.1.2.2 Output Inductor, Sense Resistor and Capacitor Selection for the BUCK1 Controller
An external resistor senses the current through the inductor. The current sense resistor pins (S1 and S2) are
fed into an internal differential amplifier which supports the range of VBUCK1 voltages. The sense resistor RS
must be chosen so that the maximum forward peak current in the inductor generates a voltage of 75 mV across
the sense pins. This specified typical value is for low duty cycles only. At typical duty-cycle conditions around
28% (assuming 3.8-V output and 12-V input), 60 mV is a more reasonable value, considering tolerances and
mismatches. The typical characteristics (see Reduction of Current Limit vs Duty Cycle) provide a guide for using
the correct current-limit sense voltage.
RS =
60 mV
I max_ peak
(2)
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
at all conditions. In order to specify optimal performance of this circuit, the following condition must be satisfied in
the choice of inductor and sense resistor:
L = 410 ´ Rs
(3)
where
•
•
L = inductor in µH
Rs = sense resistor in Ω
The current sense pins S1 and S2 are high impedance pins with low leakage across the entire VBUCK1 range.
This allows DCR current sensing (see Detailed Block Diagram Of Buck 1 Controller) using the DC resistance of
the inductor for better efficiency.
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For selecting the output capacitance and its ESR resistance, the following set of equations can be used:
COUT >
2 ´ DIOUT
ƒSW ´ DVOUT
COUT >
IL _ ripple
1
´
8 ´ ƒSW Vo _ ripple
RESR <
Vo _ ripple
IL _ ripple
(4)
where
•
•
•
•
•
ƒsw is the 490-kHz switching frequency
ΔIOUT is the worst-case load step from the application
ΔVOUT is the allowed voltage step on the output
Vo_ripple is the allowed output voltage ripple
IL_ripple is the ripple current in the coil
9.2.1.2.3 Compensation of the Buck Controller
The main buck controller requires external type 2 compensation on pin COMP1 for normal mode operation. The
components can be calculated as follows.
1. Select a value for the bandwidth, FBW, to be between fSWBUCK1 / 6 (faster response) and fSWBUCK1 / 10 (more
conservative)
2. Use Equation 5 to select a value for R3 (see Figure 8-2).
R3 =
2p ´ FBW ´ VOUT1 ´ COUT1
gm ´ K CFB ´ VrefBUCK
(5)
where
• COUT1 is the load capacitance of BUCK1
• gm is the error amplifier transconductance
• KCFB = 0.125 / Rs
• VrefBUCK is the internal reference voltage
3. Use Equation 6 to select a value for C1 (in series with R3, see Figure 8-2) to set the zero frequency close to
FBW / 10.
C1 =
10
2p ´ R3 ´ FBW
(6)
4. Use Equation 7 to select a value for C2 (parallel with R3, C1, see Figure 8-2) to set the second pole below
fSWBUCK1 / 2
C2 =
1
2p ´ R3 ´ FBW ´ 3
(7)
For example:
fSWBUCK1 = 490 kHz, VrefBUCK = 0.8 V, FBW = 60 kHz
VOUT1 = 3.8 V, Cout 1 = 50 µF, Rs = 22 mΩ
Assuming capacitor de-rating, we select the below values:
C2 = 47pF
C1 = 0.0047uF
R3 = 8.25kOhms
44
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Resulting in FBW: 57 kHz
Resulting in zero frequency: 4.2 kHz
Resulting in second pole frequency: 193 kHz
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components.
9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
The BUCK1 controller requires a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The bootstrap
capacitor is located between the PH1 pin and the BOOT1 pin (see Buck Controller Schematic). The bootstrap
capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
9.2.1.3 BUCK 1 Application Curve
100
90
80
Efficiency (%)
70
60
50
VBAT = 5 V
VBAT = 10 V
VBAT = 18 V
VBAT = 26 V
VBAT = 34 V
VBAT = 37 V
40
30
20
10
0
0.0
0.3
0.6
0.9
1.2
1.5
VBAT = 8.1 V
VBAT = 14 V
VBAT = 22 V
VBAT = 30 V
VBAT = 36 V
1.8
2.1
2.4
Iload (A)
2.7
C001
Figure 9-2. Efficiency Results Of Buck1
9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
VBUCK1
VSUP3
41
BOOT3
42
PH3
40
COMP3
37
VBUCK1
PGND3
39
VSENSE3
36
VMON3
38
0.1 µF
20 µF
33
3.3 V, 2 A max
5V
3.3 µH
VBuck3
1.2 V, 2 A max
20 µF
VMON2
4.99 k:
35
1.6 k:
VSENSE2
806 :
32
1.6 k:
PGND2
4.99 k:
34
VBuck2
1.6 k:
COMP2
3.3 µH
806 :
PH2
31
0.1 PF
29
10 µF
TPS65310A-Q1
BOOT2
5V
1.6 k:
30
PF
VSUP2
Figure 9-3. Synchronous Buck Converter Schematic
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9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-2.
Table 9-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.8 V
Output voltage (VBUCK2/3)
3.3 V
1.2 V
Maximum output current (Imax_peak)
2A
Output current ripple ΔIL_PP
300 mA
Switching frequency (fSWBUCK2/3)
0.98 MHz
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
A resistor divider from the output node to the VSENSE2 to ground respectively between the VSENSE3 to ground
pin sets the output voltage (see Figure 9-3). TI recommends using 1% tolerance or better divider resistors. Start
by selecting 1.6 kΩ for the value of the Rx resistor between the VSENSE2 to ground respectively between the
VSENSE3 to ground pin VSENSE3 pin and use Equation 8 to calculate the value for the Ry resistor between
BUCK2 and BUCK3 output and the VSENSE2 to ground respectively between the VSENSE3 to ground pin.
Ry =
R x ´ (VBUCK2/3 - 0.8 V)
0.8 V
(8)
Therefore, for VBUCK2 to equal to 3.3 V, the value of Ry must be 4.99k. For VBUCK3 to equal to 1.2 V, the value of
Ry must be 806 Ohms.
For voltage monitoring of the BUCK2 and BUCK3 output voltage, placing an additional resistive divider with
exact same values from the output node to the VMON2 and VMON3 pins is recommended for safety reasons
(see Figure 9-3). If no safety standard must be fulfilled in the application, the VMON2 and VMON3 pins can be
directly connected to VSENSE2 and VSENSE3 pins without the need for this additional resistive divider.
9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
L=
VOUT ´ (VIN - VOUT )
DIL _ PP ´ VIN ´ fsw
(9)
For example:
VIN = 5 V
VOUT = 3.3 V
ΔIL_PP = 0.35 mA
fsw = 0.98 MHz
→ L ≈ 3.3 μH
9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
The regulators operate in forced continuous mode, and have internal frequency compensation. The frequency
response can be adjusted to the selected LC filter by setting the COMP2 and COMP3 pin low, high, or floating.
After selecting the output inductor value as previously described, the output capacitor must be chosen so that
the L × COUT × VBUCK2/3 product is equal to or less than one of the three values, as listed in Table 9-3.
46
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Table 9-3. Compensation Settings
COMP 2/3
L × COUT × VBUCK2/3
EXAMPLE COMPONENTS
=0V
125 µF × µH × V
40 µF × 2.7 µH × 1.2 V
= OPEN
250 µF × µH × V
30 µF × 3.3 µH × 2.5 V
= VREG
500 µF × µH × V
200 µF × 2.2 µH × 1.2 V
Larger output capacitors can be used if a feed-forward capacitor is placed across the upper resistance, Ry, of
the feedback divider. This works effectively for output voltages > 2 V. With an RC product greater than 10 µs, the
effective VBUCK2/3 at higher frequencies can be assumed as 0.8 V, thus allowing an output capacitor increase by
a factor equal to the ratio of the output voltage to 0.8 V.
9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
The BUCK2 and BUCK3 converters require a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF.
The bootstrap capacitor is located between the PH2 pin and the BOOT2 pin and between the PH3 pin and
the BOOT3 pin (see Synchronous Buck Converter Schematic). The bootstrap capacitor must be a high-quality
ceramic type with X7R or X5R grade dielectric for temperature stability.
9.2.2.3 Application Curves
100
0.9
100
90
0.8
90
0.9
80
0.8
70
0.7
60
0.6
0.7
60
0.5
50
EFF VSUP2 = 3.8 V
40
0.4
EFF VSUP2 = 5 V
0.3
LOSS VSUP2 = 3.8 V
30
Efficiency (%)
0.6
Power Loss (W)
Efficiency (%)
70
0.5
50
EFF VSUP3 = 3.8 V
EFF VSUP3 = 3.3 V
40
0.4
Power Loss (W)
80
1
EFF VSUP3 = 5 V
0.3
30
LOSS VSUP3 = 3.8 V
LOSS VSUP2 = 5 V
20
0.2
20
0.1
10
0.2
LOSS VSUP3 = 3.3 V
LOSS VSUP3 = 5 V
10
0
0.001
0
0.01
0.1
1
10
0
0.001
0.1
0
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 9-4. Efficiency Buck2 = 3.3 V At 25°C L = 3.3
uH, C = 20 uF, COMP2 Pin Open EXTSUP Pin Open,
Measured Buck2 Output Power With Respect To
VSUP2 Input Power
Figure 9-5. Efficiency Buck3 = 1.2 V At 25°C L =
3.3 uH, C = 30 uF, COMP2 Pin To Ground EXTSUP
Pin Open, Measured Buck3 Output Power With
Respect To VSUP3 Input Power
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100
100
95
VSUP3 = 3.8 V, 1-A LOAD
Peak Efficiency (%)
Peak Efficiency (%)
95
90
VSUP2 = 3.8 V, 0.5-A LOAD
90
85
85
80
75
80
-50
0
50
100
-50
150
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 9-6. Buck2 = 3.3-V Efficiency At 0.5 A vs
Temperature L = 3.3 uH, C = 20 uF, Comp2 Pin
Open EXTSUP Pin Open, Measured Buck2 Output
Power With Respect To VSUP2 Input Power
Figure 9-7. Buck3 = 1.2-V Efficiency At 1 A vs
Temperature L = 3.3 uH, C = 30 uF, COMP2 Pin
To Ground EXTSUP Pin Open, Measured Buck3
Output Power With Respect To VSUP3 Input Power
100
100
95
95
Peak Efficiency (%)
Peak Efficiency (%)
VSUP3 = 3.8 V
90
VSUP2 = 3.8 V
90
85
85
80
80
-50
0
50
100
150
-50
Temperature (°C)
0
50
100
150
Temperature (°C)
Figure 9-8. Buck2 = 3.3-V Peak Efficiency vs
Temperature L = 3.3 uH, C = 20 uF, COMP2 Pin
Open EXTSUP Pin Open, Measured Buck2 Output
Power With Respect To VSUP2 Input Power
Figure 9-9. Buck3 = 1.2-V Peak Efficiency vs
Temperature L = 3.3 uH, C = 30 uF, COMP2 Pin
To Ground EXTSUP Pin Open, Measured Buck3
Output Power With Respect To VSUP3 Input Power
9.2.3 BOOST Converter
VBUCK1
2.7 nF
4.7 µH
10 µF
3.8 V
D2
8.4 k:
1.6 k:
5 V,
300 mA
54 µF
VBOOST
20
COMP5
23
PH5
22
PGND5
24
VBOOST
21
VSENSE5
12 k
TPS65310A-Q1
Figure 9-10. BOOST Converter Schematic
48
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9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 9-4.
Table 9-4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.8 V
Output voltage (VBOOST)
5V
Peak coil current (Ipeak_coil)
1A
Maximum output current IOUT
≈ 400 mA
Output current ripple ΔIL_PP
200 mA
Switching frequency (fSWBOOST)
0.98 MHz
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
A resistor divider from the output node to the VSENSE5 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with a value of 1.6 kΩ for the Rx resistor and use Equation 10 to
calculate Ry (see Figure 9-10).
Ry =
R x ´ (VBOOST - 0.8 V)
0.8 V
(10)
Therefore, for the value of VBOOST to equal to 5 V, the value of Ry must be 8.4 kΩ.
9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
L=
VIN ´ (VOUT - VIN )
DIL _ PP ´ VOUT ´ fsw
(11)
For example:
VIN = 3.3 V (from BUCK1)
VOUT = 5 V
ΔIL_PP = 200 mA (20% of 1-A peak current)
ƒsw = 0.98 MHz
→ L ≈ 4.7 μH
The capacitor value COUT must be selected such that the L-C double-pole frequency FLC is in the range of
10 kHz–15 kHz. The FLC is given by Equation 12:
FLC =
VIN
2 ´ p ´ VOUT ´ L ´ COUT
(12)
The right half-plane zero FRHPZ, as given in Equation 13, must be > 200 kHz:
FRHPZ =
2
VIN
> 200 kHz
2 ´ p L ´ IOUT ´ VOUT
(13)
where
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•
IOUT represents the load current
If the condition FRHPZ > 200 kHz is not satisfied, L and therefore COUT have to be recalculated.
9.2.3.2.3 Compensation of the BOOST Converter
The BOOST converter requires an external R-C network for compensation (see Figure 9-10, COMP5). The
components can be calculated using Equation 14 and Equation 15:
æF ö
R = 120 ´ VIN ´ ç BW ÷
è FLC ø
C=
2
(14)
1
2 ´ p ´ R ´ FLC
(15)
where
•
•
FBW represents the bandwidth of the regulation loop, and must be set to 30 kHz
FLC represents the L-C double-pole frequency, as mentioned previously
For example:
VIN = 3.8 V
VOUT = 5 V
L = 4.7 μH
C = 54 uF
→ FLC = 7.6 kHz
FBW = 30 kHz
→R≈8k
→ C ≈ 2.7 nF
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components. Like in this case, while fine tuning, it was observed on the EVM that using 12k as the compensation
resistance gave better load transient results and stability response than using 8k. The equations serve as a good
starting point for calculating compensation values.
9.2.3.2.4 Output Diode for the BOOST Converter
The BOOST converter requires an external output diode between the PH5 pin and VBOOST pin (see BOOST
Converter Schematic, component D2). The selected diode must have a reverse voltage rating equal to or greater
than the VBOOST output voltage. The peak current rating of the diode must be greater than the maximum
inductor current. The diode must also have a low forward voltage in order to reduce the power losses. Therefore,
Schottky diodes are typically a good choice for the catch diode.
Also, select a diode with an appropriate power rating, because the diode conducts the output current during the
off-time of the internal power switch.
50
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9.2.3.3 BOOST Converter Application Curves
100
250
100
90
80
200
Efficiency
50
Power Loss
100
40
30
Power Loss (mW)
Efficiency (%)
150
60
Peak Efficiency (%)
95
70
90
85
50
20
10
0
0.001
80
0
0.01
0.1
-50
1
0
50
100
150
Temperature (°C)
Load Current (A)
Figure 9-11. Efficiency BOOST = 5 V At 25°C
EXTSUP Pin Open, BOOST Supply Input = 3.8 V,
Measured BOOST Output Power With Respect To
Supply Input Power
Figure 9-12. Boost = 5-V Peak Efficiency vs
Temperature EXTSUP Pin Open, BOOST Supply
Input = 3.8 V, Measured Boost Output Power With
Respect To Supply Input Power
9.2.4 Linear Regulator
51
1 µF
820 :
3.3 V
VBUCK1
1.74 k:
VLDO_OUT
2.5 V, max 350 mA
10 µF
52
50
VSUP4
VSENSE4
LDO_OUT
TPS65310A-Q1
Figure 9-13. Linear Regulator Schematic
9.2.4.1 Design Requirements
For this design example, use the parameters listed in Table 9-5.
Table 9-5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Output voltage (VLDO_OUT)
2.5 V
Maximum output current (IOUT)
350 mA
9.2.4.2 Detailed Design Procedure
9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
A resistor divider from the output node to the VSENSE4 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. In order to get the minimum required load current of 1 mA for the linear
regulator, start with a value of 820 Ω for the Rx resistor and use Equation 16 to calculate Ry (see Figure 9-13).
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Ry =
R x ´ (VLDO _ OUT - 0.8 V)
(16)
0.8 V
Therefore, for the value of VLDO_OUT to equal to 2.5 V, the value of Ry must be 1.74 kΩ.
9.2.4.2.2 Output Capacitance for the Linear Regulator
The linear regulator requires and external output capacitance with a value between 6 µF and 50 µF.
9.2.4.3 Linear Regulator Application Curve
10
9
Noise [LDO ON]
8
Noise [LDO OFF]
(Noisefloor)
NOISE (uV / sqrt [Hz])
7
6
5
4
3
2
1
0
10
100
1000
10000
Frequency (Hz)
Figure 9-14. LDO Noise Density
52
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 40 V (see Figure 10-1
for reference). This input supply must be well regulated. In case the supply voltage in the application is likely
to exceed 40 V, the external PMOS protection device as explained in Section 8.4.19 must be applied between
VIN and VINPROT pins. Furthermore, if the supply voltage in the application is likely to reach negative voltage
(for example, reverse battery), a forward diode must be placed between the VSSENSE and VIN pins. A ceramic
bypass capacitor with a value of 100 μF (typical) is recommended to be placed close to the VINPROT pin.
For the VIN pin, a small ceramic capacitor of typical 1 µF is recommended. Also place 1-µF (typical) bypass
capacitors to the DVDD and VREF pins, and 100-nF (typical) bypass capacitors to VIO pin. Furthermore, the
VREG pin requires a bypass capacitor of 2.2 µF (typical).
The BUCK1 output voltage is the recommended input supply for the BUCK2, BUCK3, and BOOST regulators.
Place local, 10-µF (typical) bypass capacitors at the VSUP2 and VSUP3 pins and at the supply input of the
BOOST in front of the BOOST-inductor. Also place a local, 1-µF (typical) bypass capacitor at the VSUP4 pin.
The EXTSUP pin can be used to improve efficiency. For the EXTSUP pin to improve efficiency, a voltage of more
than 4.8 V is required in order to have VREG regulator supplied from EXTSUP pin. If the EXSUP pin is not used,
the VINPROT pin supplies the VREG regulator. The EXTSUP pin requires a 100-nF (typical) bypass capacitor.
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VINPROT
2.2 µF
9
13
Q3
WAKE
PGND1
14
44
CSN
COMP1
18
46
SCK
R3
SDO
C2
SDI
53
VREF
S1
15
S2
16
VSENSE1
19
VMON1
17
VSUP2
30
BOOT2
29
PH2
31
VT_REF
54
VT
TPS65310A-Q1
VBUCK1
34
49
HSPWM
PGND2
32
VSENSE2
35
VMON2
33
COMP5
VSUP3
41
23
PH5
BOOT3
42
22
PGND5
24
VBOOST
21
VSENSE5
10 µF
VBUCK1
820 :
1.74 k:
36
VMON3
38
1.2 V, 2 A
20 µF
39
806 :
PGND3
VSENSE3
1.6 k:
37
806 :
COMP3
3.3 µH
1.6 k:
PH3
40
VLDO_OUT
2.5 V, maximum 350 mA
10 µF
1 µF
VBUCK1
56 GND
LDO_OUT
51
VSENSE4
52
50
1.6 k:
8.4 k:
VSUP4
D2
µF
20
12 k
0.1 µF
4.7 µH
2.7 nF
3.3 V, 2 A
20 µF
COMP2
4.99 k
HSCTRL
VBUCK1
10 µF
3.8 V, 2.5 A
VBuck2
1.6 k:
5
3.3 µH
4.99 k
HSSENSE
1.6 k:
6
0.1 µF
VINPROT
VBOOST
5 V,
300 mA
VBUCK1
10 µF
25
R1
R2
1 µF
45
C1
47 pF
0.1 µF
47
8.25 k 4.7 nF
50 µF
GL
10 µH
12
0.1 µF
VINPROT 4
3
2
GPFET
VREG
PH1
Q2
2.2 µF
WD
11
60.4 k
43
10 k:
GU
16 k:
PRESN
10
60.4 k 22 m:
RESN
26
BOOT1
C3
27
VIN
VIO
DVDD
48
10 k:
10 k:
0.1 µF
VBUCK1
VSSENSE 1
IRQ
10 k:
28
55
1 µF
0.1 µF
Q1
16 k:
D1
4 V to 40 V (typ. 12 V)
EXTSUP 8
VBAT
Figure 10-1. Typical Application Schematic
54
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11 Layout
11.1 Layout Guidelines
11.1.1 Buck Controller
•
•
•
•
•
•
Connect a local decoupling capacitor between the drain of Q3 and the source of Q2. The length of this trace
loop should be short.
The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitor for noise near the S1-S2 pins.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
Connect the boot-strap capacitance between the PH1 and BOOT1 pins, and keep the length of these trace
loops as short as possible.
Connect the compensation network between the COMP1 pin and GND pin (IC signal ground).
Connect a local decoupling capacitor between the VREG and PGDN1 pin, and between the EXTSUP and
PGND1 pin. The length of this trace loop should be short.
11.1.2 Buck Converter
•
•
•
•
Connect a local decoupling capacitor between VSUP2 and PGND2 respectively VSUP3 and PGND3 pins.
The length of this trace loop should be short.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
Connect the boot-strap capacitance between the PH2 and BOOT2 respectively PH3 and BOOT3 pins, and
keep the length of this trace loop as short as possible.
If COMP2 and/or COMP3 are chosen to be connected to ground, use the signal ground trace connected to
GND pin for this.
11.1.3 Boost Converter
•
•
•
The path formed from the input capacitor to the inductor and the PH5 pin should have short trace length. The
same applies for the trace from the inductor to Schottky diode D2 to the output capacitor and the VBOOST
pin. Connect the negative pin of the input capacitor and the PGND5 pin together with short trace lengths.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
Connect the compensation network between the COMP5 pin and GND pin (IC signal ground).
11.1.4 Linear Regulator
•
•
Connect a local decoupling capacitor between VSUP4 and GND (IC signal ground) pins. The length of this
trace loop should be short.
The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
11.1.5 Other Considerations
•
•
Short PGNDx and GND to the thermal pad.
Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the
compensation-network ground, voltage-sense feedback ground, and local biasing bypass capacitor ground
networks to this star ground.
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WD
CSN
SDI
SCK
VIO
SDO
HSPWM
VSUP4
LDO_OUT
VT_REF
VSENSE4
VT
VREF
GND
Analog Signal Ground trace
Sense resistors LDO
DVDD
Input supply voltage
Analog Signal Ground trace
LDO output
voltage
11.2 Layout Example
VSSENSE
BOOT3
D1
VIN
VSUP3
GPFET
PH3
VINPROT
PGND3
HSCTRL
VMON3
HSSENSE
COMP3
BUCK3 output voltage
Q1
WAKE
VSENSE2
VREG
COMP2
BOOT1
VMON2
GU
PGND2
PH1
PH2
GL
VSUP2
PGND1
BOOT2
Q2
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
Sense and
Monitoring
resistors
BUCK2
Sense and
Monitoring
resistors
BUCK1
IRQ
RESN
PRESN
VT_REF
PH5
VBOOST
VSENSE5
PGND5
VT_REF
Compensation network BOOST
COMP5
VSENSE1
COMP1
Compensation network BUCK1
BUCK1 output voltage
S1
plane
BOOST output
voltage
Analog Signal Ground trace
ground
VMON1
BUCK2 output voltage
S2
Q3
Power
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
VSENSE3
Exposed Thermal
Pad area
EXTSUP
Sense and
Monitoring
resistors
BUCK3
Sense resistors
BOOST
Analog Signal Ground trace
Figure 11-1. TPS65310-Q1 Layout Example
56
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Note
(1) There’s very high dI/dt in path where the switching current flows. Any inductance in this path
results in ringing on switched node. It’s very important to minimize these loop areas.
Figure 11-2. EVM Top Layer
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Figure 11-3. EVM Bottom Layer
58
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• TPS65310A-Q1 Efficiency SLVA610
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
60
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65310AQRVJRQ1
ACTIVE
VQFN
RVJ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS65310A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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