TPS65642
www.ti.com
SLVSBX6 – JULY 2013
LCD Bias with Integrated Gamma Reference for Notebook PCs, Tablet PCs and Monitors
Check for Samples: TPS65642
1 Introduction
1.1
Features
1
• 2.6 V to 6 V Input Voltage Range
• Synchronous Boost Converter (AVDD)
• Non-Synchronous Boost Converter with
Temperature Compensation (VGH)
• Synchronous Buck Converter (VCORE)
• Synchronous Buck Converter (VIO1)
• Low Dropout Linear Regulator (VIO2)
• Programmable VCOM Calibrator with Two
Integrated Buffer Amplifiers
• Gate Voltage Shaping
1.2
•
•
•
• Panel Discharge Signal (XAO)
• System Reset Signal (RST)
• 14-Channel, 10-Bit Programmable Gamma
Voltage Correction
• On-Chip EEPROM with Write Protect
• I2C™ Interface
• Thermal Shutdown
• Supports GIP and Non-GIP Displays
• 56-Ball, 3.16 mm x 3.45 mm 0.4 mm Pitch
DSBGA
Applications
Notebook PCs
Tablet PCs
Monitors
1.3
Description
The TPS65642 is a compact LCD bias solution primarily intended for use in Notebook and Tablet PCs.
The device comprises two boost converters to supply the LCD panel's source driver and gate driver/level
shifter; two buck converters and an LDO linear regulator to supply the system's logic voltages; a
programmable VCOM generator with two high-speed amplifiers; 14-channel gamma voltage correction; and
a gate voltage shaping function.
VIN
VIO1
AVDD
Boost Converter 1
AVDD
Buck Converter 1
VCORE
Buck Converter 2
VIO1
LDO Regulator
VIO2
Boost Converter 2
VGH
RST
Reset Generator
VGH
2
IC
XAO
Gate Voltage Shaping
VGHM
Programmable
Gamma Voltages
14
Programmable
VCOM + Buffers
2
VGAM
VCOM
2
I C Interface
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS65642
SLVSBX6 – JULY 2013
www.ti.com
2 Electrical Specifications
ORDERING INFORMATION (1)
2.1
(1)
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65642YFF
3.16 mm × 3.45 mm DSBGA, 0.4 mm pitch
TPS65642
The device is supplied taped and reeled, with 3000 devices per reel.
ABSOLUTE MAXIMUM RATINGS (1)
2.2
over operating free-air temperature range (unless otherwise noted)
Pin voltage
MIN
MAX
UNIT
VIN, SW2, VCORE, SW3, VIO1, VIO2 RSET, COMP, SCL, SDA,
EN, FLK, WP, TCOMP, XAO, RST
–0.3
7
V
AVDD, SW1, OUT1, OUT2, OUTA-OUTN
–0.3
12
V
V
SW4
–0.3
36
POS1, NEG1, POS2, NEG2
–0.3
12 (3)
V
2
V
|POS1-NEG1| (4), |POS2-NEG2| (4)
(5)
V
Human Body Model
2000
V
Machine Model
200
V
VGH, VGHM, RE
ESD Rating
(2)
–0.3
Charged Device Model
40
700
V
-40
85
°C
Junction temperature, TJ
-40
150
°C
Storage temperature, TSTG
–65
150
°C
Ambient temperature, TA
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VGH supplies up to 40 V can be generated, but require an external cascode transistor or charge pump.
For supply voltages less than 12 V, the absolute maximum input voltage is equal to the supply voltage.
Differential input voltage.
The combination of low temperatures and high VGH voltages can cause increased leakage current through the RE pin. In GIP
applications that do not use the gate-voltage shaping function it is recommended to leave the RE pin open to minimize this effect.
THERMAL INFORMATION (1)
2.3
TPS65642
THERMAL METRIC
YFF
UNITS
56 PINS
θJA
Junction-to-ambient thermal resistance
45
θJCtop
Junction-to-case (top) thermal resistance
0.2
θJB
Junction-to-board thermal resistance
6.4
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
6.1
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Electrical Specifications
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2.4
SLVSBX6 – JULY 2013
RECOMMENDED OPERATING CONDITIONS
MIN
VIN
Input voltage range
TYP
2.6
MAX
UNIT
6
V
BOOST CONVERTER 1
AVDD
Boost converter 1 output voltage range
9.1
V
IAVDD
Boost converter 1 output current when 6 V ≥ VIN ≥ 4 V
6
700 (1)
mA
Boost converter 1 output current when 3.63 V ≥ VIN ≥ 2.64 V
400 (1)
mA
10
µH
L
Boost converter 1 inductor range
2.2
COUT
Boost converter 1 output capacitance
10
4.7
µF
BOOST CONVERTER 2
AVDD
Input voltage range
6
8.1
9.1 (2)
VGH
Output voltage range
16
24
40 (3)
V
IGH
Output current
15
40
mA
L
Inductor
10
15
COUT
Output capacitance
1
4.7
µF
RNTC
Thermistor resistance at 25°C
10
kΩ
V
µH
BUCK CONVERTER 1 (VCORE)
VCORE
Output voltage
ICORE
Output current
L
Inductor
COUT
Output capacitance
1
1.1
1.3
V
600
mA
1
2.2
4.7
µH
4.7
10
22
µF
2.5
V
BUCK CONVERTER 2 (VIO1)
VIO1
Output voltage
IIO1
Output current
L
Inductor
COUT
Output capacitance
1.7
200
(4)
mA
1
2.2
4.7
µH
4.7
10
22
µF
LDO Regulator (VIO2)
VIO2
Output voltage
IIO
Output current
COUT
Output capacitance
1.7
4.7
1.8
V
200
mA
10
µF
PROGRAMMABLE VCOM
ISET
Programmable VCOM set current
50
µA
PROGRAMMABLE GAMMA CORRECTION
IGAM
Output current per channel
CGAM
Output capacitance
(1)
(2)
(3)
(4)
-100
100
µA
50
pF
This value includes the current that must be supplied to the input of boost converter 2.
VGH−AVDD must be greater than 9 V.
Output voltages greater than 36 V require an external cascode transistor.
This value includes the current supplied to the input of the linear regulator.
Electrical Specifications
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TPS65642
SLVSBX6 – JULY 2013
2.5
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ELECTRICAL CHARACTERISTICS
VIN = 3.3 V, VCORE = 1.1 V, VIO1 = 1.7 V, VIO2 = 1.8 V (1), AVDD = 8.1 V, VGH = 24 V, TA = −40°C to 85°C. Typical values are at
25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Converters not switching
1.9
3
mA
Pin G5.
0.1
1
Pin B7. No load on gamma reference outputs
4.3
6
Pin F4. No load on op-amp outputs
4.0
7.5
No load on VGHM
0.1
1
POWER SUPPLY
Supply current into VIN pins
IIN
Supply current into AVDD pins
Supply current into VGH
mA
mA
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
VIN rising
2.3
2.42
2.5
VIN falling
2.1
2.19
2.4
Hysteresis
V
0.23
CONTROL PINS (EN, FLK, WP)
VIH
EN high-level input voltage threshold
VIL
EN low-level input voltage threshold
EN rising
EN falling
VIN = 2.64 V
1.0
1.8
VIN = 3.3 V
1.1
1.8
VIN = 6 V
1.7
1.8
VIN = 2.64 V
0.7
0.9
VIN = 3.3 V
0.7
1.0
VIN = 6 V
0.7
1.6
V
V
IIH
EN high-level input current
EN = 2.5 V
–100
100
nA
IIL
EN low-level input current
EN = 0 V
–100
100
nA
VIN = 2.64 V
FLK high-level input voltage
threshold
VIH
FLK rising
VIN = 3.3 V
VIN = 6 V
VIL
FLK low-level input voltage threshold
FLK falling
0.9
1.8
1
1.8
1.4
1.8
VIN = 2.64 V
0.6
0.8
VIN = 3.3 V
0.6
0.9
VIN = 6 V
0.6
1.3
V
V
IIH
FLK high-level input current
FLK = 2.5 V
–100
100
nA
IIL
FLK-low-level input current
FLK = 0 V
–100
100
nA
VIH
WP high-level input voltage threshold
VIL
WP low-level input voltage threshold
RPULL-UP
WP rising
WP falling
VIN = 2.64 V
1
1.8
VIN = 3.3 V
1.1
1.8
VIN = 6 V
1.7
1.8
VIN = 2.64 V
0.7
VIN = 3.3 V
0.7
1
VIN = 6 V
0.7
1.6
30
52
WP internal pull-up resistance
V
0.9
V
75
kΩ
BOOST CONVERTER 1 (AVDD)
AVDD
Output voltage range
Tolerance
6
9.1
–1%
1%
V
VUVP
Undervoltage protection threshold
AVDD falling
65
70
75
% of AVDD
VSCP
Short-circuit threshold
AVDD falling
25
30
35
% of AVDD
ILK
Switch leakage current
VSW = VIN = 3.3 V, EN = 0 V, TJ = –40°C to 85°C
rDS(ON)
Switch ON resistance
ISW = 1 A
ILIM
Switch current limit
rDS(ON)
Rectifier ON resistance
ISW = 1 A
fSW
Switching frequency (see Figure 415)
FREQ = 0
750
FREQ = 1
1200
rDS(ON)
Discharge ON resistance
IAVDD = 10 mA
(1)
4
114
2.5
10
µA
250
mΩ
3.0
3.5
A
242
400
mΩ
76
kHz
100
Ω
When VIO1= 1.7 V or 1.8 V, the LDO regulator is disabled. When VIO1 = 2.5 V, the LDO regulator is enabled.
Electrical Specifications
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SLVSBX6 – JULY 2013
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VCORE = 1.1 V, VIO1 = 1.7 V, VIO2 = 1.8 V(1), AVDD = 8.1 V, VGH = 24 V, TA = −40°C to 85°C. Typical values are at
25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
1
1.1
MAX
UNIT
BUCK CONVERTER 1 (VCORE)
VCORE
Output voltage
Tolerance
–3%
1.3
V
3%
VUVP
Undervoltage protection threshold
VCORE falling
65
70
75
% of VCORE
VSCP
Short-circuit threshold
VCORE falling
25
30
35
% of VCORE
ILIMA
Switch current limit
ISW ramps from 0 A to 2 A
0.8
1.0
1.2
A
High-side, ISW = ILIM
183
310
Low-side, ISW = 1 A
95
150
rDS(ON)
Switch ON resistance
tOFF
Off time
VIN = 3.3 V
260
370
480
VIN = 5 V
380
560
750
Output voltage
1.7
1.8
Tolerance
–3%
mΩ
ns
BUCK CONVERTER 2 (VIO1)
VIO1
2.5
V
3%
VUVP
Undervoltage protection threshold
VIO1 falling
65
70
75
% of VIO1
VSCP
Short-circuit threshold
VIO1 falling
25
30
35
% of VIO1
ILIM
High-side switch current limit
High-side, ISW ramps from 0 A to 2 A
0.8
1
1.2
A
High-side switch ON resistance
ISW = ILIM
183
350
Low-side switch ON resistance
ISW = 1 A
255
400
rDS(ON)
tOFF
Off time
rDS(ON)
Discharge ON resistance
VIN = 3.3
170
250
330
VIN = 5 V
250
370
500
14.6
50
Measured with 10 mA
mΩ
μs
Ω
LINEAR REGULATOR (VIO2) (2)
Output voltage
VIO2
Tolerance
1.7
IIO2 = 1 mA
1.8
–3%
1.8
V
3%
VUVP
Undervoltage protection threshold
VIO2 falling
65
70
75
% of VIO2
VSCP
Short circuit threshold
VIO2 falling
25
30
35
% of VIO2
BOOST CONVERTER 2 (VGH)
Output voltage range
VGH
Tolerance
16
40 (3)
–3%
3%
V
VUVP
Undervoltage protection threshold
VGH falling
65
70
75
% of VGH
VSCP
Short-circuit threshold
VGH falling
25
30
35
% of VGH
ILK
Switch leakage current
VEN=0 V; VSW4=36 V
10
µA
rDS(ON)
Switch ON resistance
ISW=1 A
0.41
1
Ω
tON(MAX)
Maximum tON time
1
1.67
2.5
µs
tOFF
tOFF time
1.5
2.11
3
µs
ITCOMP
Thermistor reference current
ISET = 50 μA, VTCOMP = 1 V
85°C
48
25 °C
54
50
µA
RESET (RST)
Reset pulse duration range
Tolerance
Measured from end of VCORE's ramp to 50% of RST's
rising edge with a 10k pull-up resistor.
VOL
Low output voltage
IRST = 1 mA (sinking)
IOH
High output current
VRST=2.5 V
tRESET
2
16
–20%
30%
0.27
–1
ms
0.5
V
1
µA
PROGRAMMABLE GAMMA CORRECTION
VDROPH
High-side output voltage drop
VDROPL
Low-side output voltage drop
Code = 1023; load = 10 µA, sourcing
5.6
100
Code = 1023; load = 100 µA, sourcing
44.2
200
Code = 0; load = 10 µA, sinking
49.1
100
Code = 0; load = 100 µA, sinking
65.5
200
(2)
LDO is enabled, when VIO1 = 2.5 V.
(3)
Output voltages greater than 36V require an external cascode transistor or charge pump circuit.
Electrical Specifications
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mV
5
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VCORE = 1.1 V, VIO1 = 1.7 V, VIO2 = 1.8 V(1), AVDD = 8.1 V, VGH = 24 V, TA = −40°C to 85°C. Typical values are at
25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Offset
Code = 512
–25
25
mV
INL
Integral nonlinearity
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
–3.6
5.9
LSB
DNL
Differential nonlinearity
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
–1
1.5
LSB
PROGRAMMABLE VCOM CALIBRATOR
SETZSE
Set zero-scale error
–1
1
LSB
SETFSE
Set full-scale error
–7
7
LSB
VRSET
Voltage on RSET pin
DNL
Differential nonlinearity
AVOL
Open loop gain
VCM = AVDD/2, VOUT1 = 2 V, VOUT2 = AVDD – 2 V, RL=
∞
VIO
Input offset voltage
VCM = AVDD/2, VOUT = AVDD/2
–15
15
mV
IB
Input bias current
VCM = AVDD/2, VOUT = AVDD/2
–150
150
nA
VDROPH
High-side voltage drop
VPOS = AVDD/2, VNEG = AVDD/2–1 V,
IOUT = 10 mA sourcing
0.05
0.1
V
VDROPL
Low-side voltage drop
VPOS = AVDD/2, VNEG = AVDD/2+1 V,
IOUT = 10 mA sinking
0.03
0.1
V
–2%
1.25
–1
70
2%
V
1.5
LSB
91
dB
VCM = AVDD/2, VSIGNAL = 2 VPP, open-loop,
RL = ∞, CL = 1 µF
200
Low-side peak output current
CMRR
Common-mode rejection ratio
VCM1 = 2 V, VCM2 = AVDD–2 V, VOUT = AVDD/2
40
78
dB
PSRR
Power supply rejection ratio
AVDD1 = 6 V, AVDD2 = 9.1 V, VCM = 3 V, VOUT = 3 V
40
110
dB
Slew rate
Open-loop,
VPOS = AVDD/2±1 V
TA = –40°C
18
30
TA = 25°C to 85°C
25
38
IPK
SR
High-side peak output current
IRSET=50 µA
294
–349
–200
mA
V/μs
GATE VOLTAGE SHAPING
VGH to VGHM ON resistance
rDS(ON)
VGHM to RE ON resistance
tPLH
Propagation delay
tPHL
VGH = 24 V, IGHM = 10 mA, FLK = 2.5 V
12
25
VGHM = 24 V, IGHM = 10 mA, FLK = 0 V
12
25
VGHM = 6 V, IGHM = 10 mA, FLK = 0 V
12
25
VGHM rising, 2.5 V, 50% thresholds, COUT = 150 pF, RE
=0Ω
72
175
VGHM falling, 2.5 V, 50% thresholds, COUT = 150 pF,
RE = 0 Ω
81
200
0.23
0.5
V
1
µA
Ω
ns
PANEL RESET / LCD BIAS READY (XAO)
VOL
Low output voltage
IXAO = 1 mA (sinking)
IOH
High output current
VXAO = 2.5 V
XAO threshold voltage
VDET
Tolerance
Hysteresis
XAO falling
XAO rising
2.2
3.9
–2.5%
2.5%
3%
6.3%
V
11%
TIMING
tDLY1
tDLY6
Boost converter 1 delay range
Tolerance
Gate voltage shaping / LCD bias
ready delay range
Tolerance
tSS1
tSS2
tUVP
Soft-start ramp time
Tolerance
Soft-start ramp time
Tolerance
VCORE, VIO1, VIO2
AVDD, VGH
Undervoltage protection timeout
0
70
–20%
30%
0
35
–20%
30%
0.5
4
–20%
30%
4.0
7.5
–20%
30%
40
50
ms
ms
ms
ms
65
ms
0.75
V
I2C INTERFACE
ADDR
Configuration parameters slave
address
74h
Programmable VCOM slave address
VIL
6
Low level input voltage
4Fh
Rising Edge, standard and fast mode
Electrical Specifications
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VCORE = 1.1 V, VIO1 = 1.7 V, VIO2 = 1.8 V(1), AVDD = 8.1 V, VGH = 24 V, TA = −40°C to 85°C. Typical values are at
25°C (unless otherwise noted).
TEST CONDITIONS
MIN
VIH
High level input voltage
PARAMETER
Rising edge, standard and fast modes
1.75
TYP
MAX
V
VHYS
Hysteresis
Applicable to fast mode only
125
mV
VOL
Low level output voltage
Sinking 3 mA
CI
Input capacitance
500
mV
10
pF
Standard mode
100
Fast mode
400
fSCL
Clock frequency
tLOW
Clock low period
tHIGH
Clock high period
tBUF
Bus free time between a STOP and a Standard mode
START condition
Fast mode
thd:STA
Hold time for a repeated START
condition
Standard mode
tsu:STA
Set-up time for a repeated START
condition
Standard mode
tsu:DAT
Data set-up time
thd:DAT
Data hold time
tRCL1
Rise time of SCL after a repeated
START condition and after an ACK
bit
tRCL
Rise time of SCL
tFCL
Fall time of SCL
tRDA
Rise time of SDA
tFDA
Fall time of SDA
tsu:STO
Set-up time for STOP condition
CB
Capacitive load on SDA and SCL
Standard mode
4.7
Fast mode
1.3
Standard mode
4.0
Fast mode
0.6
Fast mode
UNIT
kHz
µs
µs
4.7
µs
1.3
4
µs
0.6
4
µs
Fast mode
0.6
Standard mode
250
Fast mode
100
Standard mode
0.05
3.45
Fast mode
0.05
0.9
Standard mode
20+0.1CB
1000
Fast mode
20+0.1CB
1000
Standard mode
20+0.1CB
1000
Fast mode
20+0.1CB
300
Standard mode
20+0.1CB
300
Fast mode
20+0.1CB
300
Standard mode
20+0.1CB
1000
Fast mode
20+0.1CB
300
Standard mode
20+0.1CB
300
Fast mode
20+0.1CB
300
Standard mode
4.0
Fast mode
0.6
ns
µs
ns
ns
ns
ns
ns
µs
Standard mode
400
Fast mode
400
pF
EEPROM
NWRITE
Number of write cycles
tWRITE
Write time
Data retention
1000
100
Storage temperature=150 °C
100
ms
1000 hrs
THERMAL SHUTDOWN
TSD (4)
(4)
Thermal shutdown threshold
120
150
180
°C
Once triggered, thermal shutdown will remain in the shutdown state until the device is powered down.
Pin Description
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3 Pin Description
3.1
Pin Assignment
NEG2
OUT2
AVDD
SW1
GND
GND
SW4
SW4
OUT1
AVDD
SW1
GND
EN
GND
GND
EN
NEG1
OUTD
AVDD
OUTH
WP
COMP
VGH
VGH
F2
OUTC
OUTG
OUTN
OUTK
SCL
VGHM
VGHM
SCL
OUTB
POS1
OUTF
OUTM
OUTJ
SDA
RE
RE
RSET
OUTA
OUTI
OUTE
OUTL
GND
FLK
FLK
GND
VIO1
VIN
XAO
RST
TCOMP
VCORE
VIO2
SW3
GND
VIN
SW2
GND
GND
VIN
SW2
XAO
SW3
A3
C7
AVDD
B6
B7
GND
VIO2
A6
A7
BOTTOM VIEW
TOP VIEW
3.2
RSET
VIO1
A5
D7
C6
B5
GND
A4
POS1
OUTA
RST
E7
D6
C5
B4
POS2
OUTB
OUTE
F7
E6
D5
C4
B3
VIN
A2
A1
OUTI
NEG1
OUTC
OUTF
G7
F6
E5
D4
C3
B2
B1
GND
OUTL
TCOMP
VCORE
OUTJ
G6
OUTD
OUTG
H7
GND
OUT1
F5
E4
D3
C2
C1
AVDD
OUTM
H6
G5
OUTH
OUTK
E3
D2
AVDD
F4
NEG2
OUT2
H5
G4
AVDD
OUTN
SDA
D1
SW1
F3
E2
E1
AVDD
H4
G3
WP
COMP
F1
POS2
GND
G2
G1
SW1
H3
H2
H1
GND
GND
GND
Pin Assignment
Table 3-1. PIN DESCRIPTIONS
PIN
8
I/O
DESCRIPTION
NAME
NO.
GND
A1
P
Ground.
SW2
A2
O
Buck converter 1 (VCORE) switch pin.
VIN
A3
P
Supply voltage.
SW3
A4
O
Buck converter 2 (VIO1) switch pin.
GND
A5
P
Ground.
VIO2
A6
O
Linear regulator (VIO2) output and output sense.
GND
A7
P
Ground.
VCORE
B1
I
Buck converter 1 (VCORE) output sense.
TCOMP
B2
I
Boost converter 2 (VGH) thermistor network connection.
VIN
B3
P
Supply voltage.
XAO
B4
O
Panel discharge.
RST
B5
O
System reset.
VIO1
B6
I
Buck converter 2 (VIO1) output sense. (Internally connected as supply voltage for LDO
regulator.)
AVDD
B7
I
Boost converter 1 (AVDD) output sense. (Internally connected as supply voltage for
programmable gamma correction.)
FLK
C1
I
Gate voltage shaping flicker clock.
GND
C2
P
Ground.
OUTL
C3
O
Gamma correction.
Pin Description
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SLVSBX6 – JULY 2013
Table 3-1. PIN DESCRIPTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
OUTI
C4
O
Gamma correction.
OUTE
C5
O
Gamma correction.
OUTA
C6
O
Gamma correction.
RSET
C7
O
Reference current-setting resistor connection.
RE
D1
O
Gate voltage shaping discharge resistor connection.
SDA
D2
I/O
I2C serial data.
OUTM
D3
O
Gamma correction.
OUTJ
D4
O
Gamma correction.
OUTF
D5
O
Gamma correction.
OUTB
D6
O
Gamma correction.
POS1
D7
I
VCOM 1 non-inverting input.
VGHM
E1
O
Gate voltage shaping output.
SCL
E2
I/O
I2C serial clock.
OUTN
E3
O
Gamma correction.
OUTK
E4
O
Gamma correction.
OUTG
E5
O
Gamma correction.
OUTC
E6
O
Gamma correction.
POS2
E7
I
VCOM2 non-inverting input.
VGH
F1
I
Boost converter 2 (VGH) output sense. (Internally connected as supply voltage for the gate
voltage shaping.)
COMP
F2
O
Boost converter 1 (AVDD) compensation network connection.
WP
F3
I
EEPROM write protect.
AVDD
F4
I
VCOM1 and VCOM2 supply voltage.
OUTH
F5
O
Gamma correction.
OUTD
F6
O
Gamma correction.
NEG1
F7
I
VCOM1 inverting input.
GND
G1
P
Ground.
EN
G2
I
Boost converter 1 (AVDD) enable.
GND
G3
P
Ground.
SW1
G4
O
Boost converter 1 (AVDD) switch pin.
AVDD
G5
O
Boost converter 1 (AVDD) rectifier output.
OUT1
G6
O
VCOM1 output.
GND
G7
P
Ground.
SW4
H1
O
Boost converter 2 (VGH) switch pin.
GND
H2
P
Ground
GND
H3
P
Ground.
SW1
H4
O
Boost converter 1 (AVDD) switch pin.
AVDD
H5
O
Boost converter 1 (AVDD) rectifier output.
OUT2
H6
O
VCOM2 output.
NEG2
H7
I
VCOM2 inverting input.
Pin Description
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www.ti.com
4 Typical Characteristics
4.1
Table of Graphs
PARAMETER
Boost Converter 1 (AVDD) Efficiency
VIN = 2.6 V to 6.0 V, AVDD = 8 V, IAVDD = 100 mA
Load Regulation
VIN = 3.4 V, 5.0 V, AVDD = 8 V, IAVDD = 1 mA to 500 mA
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.1 V
Output Voltage Ripple
Switching Waveforms
Switching Frequency
Buck Converter 1 (VCORE) Efficiency
Figure 4-1
VIN = 5 V
Figure 4-2
Figure 4-3
AVDD = 8.1 V, IAVDD = 20 mA – 200 mA
AVDD = 8.1 V, RL = 82 Ω
Figure 4-4
RL = 82 Ω
Figure 4-5
RL = 33 Ω
Figure 4-6
VIN = 3.3 V
Figure 4-7
VIN = 5.0 V
Figure 4-8
VIN= 3.3 V
Figure 4-9
VIN = 5.0 V
Figure 4-10
VIN = 3.3 V, AVDD = 8.1 V
FREQ = 0
RL = 820 Ω
Figure 4-11
RL = 82 Ω
Figure 4-12
VIN= 3.3 V, AVDD= 8.1 V
FREQ = 1
RL = 820 Ω
Figure 4-13
RL = 82 Ω
Figure 4-14
VIN = 2.6 V to 6 V, AVDD = 6 V, 8 V, 9.1 V
RL = 82 Ω
Figure 4-15
VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500 mA
VIN = 3.4 V
Figure 4-16
VIN = 5.0 V
Figure 4-17
VIN = 2.6 V to 6.V, VCORE = 1.1 V, ICORE = 300 mA
Figure 4-18
Load Regulation
VIN = 3.4 V, 5 V, VCORE = 1.1 V, ICORE = 1 mA to 700 mA
Figure 4-19
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VCORE = 1.1 V, Load = 3.9 Ω
Figure 4-20
Load Transient Response
VCORE = 1.1 V, ICORE = 50 mA to 200 mA
VIN = 3.3 V
Figure 4-20
VIN = 5 V
Figure 4-22
VIN = 3.3 V
Figure 4-23
VIN = 5 V
Figure 4-24
RL = 120 Ω
Figure 4-25
RL = 3.9 Ω
Figure 4-26
Switching Waveforms
VCORE = 1.1 V, RL = 3.9 Ω
VIN = 3.3 V, VCORE = 1.1 V
Switching Frequency
VIN = 2.6 V to 6 V, VCORE = 1.1 V
RL = 12 Ω
Figure 4-27
Efficiency
VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
VIN = 3.3 V
Figure 4-28
VIN = 5 V
Figure 4-29
Line Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
Figure 4-30
Load Regulation
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 400 mA
Figure 4-31
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 1.7 V,RL = 27 Ω
Load Transient Response
VIO1 = 1.7 V, IIO1 = 50 mA to 100 mA
Output Voltage Ripple
Switching Waveforms
10
VIN = 3.3 V
Line Regulation
Output Voltage Ripple
LDO Regulator (VIO2)
FIGURE
Line Regulation
Load Transient Response
Buck Converter 2 (VIO1)
TEST CONDITIONS
AVDD = 6 V, 8 V, 9.1 V
FREQ = 0, FREQ = 1
VIO1 = 1.7 V, RL = 27 Ω
VIN =3 .3 V, VIO1 = 1.7 V
Figure 4-32
VIN = 3.3 V
Figure 4-33
VIN = 5 V
Figure 4-34
VIN = 3.3 V
Figure 4-35
VIN = 5 V
Figure 4-36
RL = 270 Ω
Figure 4-37
RL = 27Ω
Figure 4-38
RL = 27 Ω
Figure 4-39
Switching Frequency
VIN = 2.6 V to 6 V, VIO1 = 1.7 V
Load Regulation
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
Figure 4-40
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
Figure 4-41
Load Transient Response
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA to 150 mA
Figure 4-42
Output Voltage Ripple
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
Figure 4-43
Typical Characteristics
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PARAMETER
Boost Converter 2 (VGH)
Figure 4-44
Line Regulation
AVDD = 6 V to 9.1 V, IGH = 10 mA
Figure 4-45
Load Regulation
AVDD = 8.1 V, VGH = 24 V, IGH = 1 mA to 50 mA
Line Transient Response
VIN = 3V to 4.8 V (dV/dt = 7.5 V/ms), VGH = 24 V
Output Voltage Ripple
Switching Waveforms
Power-Down Behavior
FIGURE
AVDD = 8.1 V, VGH = 20 V, 24 V, 28 V, 31 V
Load Transient Response
Power-Up Behavior
TEST CONDITIONS
Efficiency
VIN = 5 V, AVDD = 8.1 V, VGH = 24 V
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V
VIN = 3.3 V, AVDD = 8.1 V, Load = 82 Ω, VGH = 24 V
Figure 4-46
RL = 4.8 kΩ
Figure 4-47
RL = 1.2 kΩ
Figure 4-48
IGH = 5 mA to 10 mA
Figure 4-49
IGH = 10 mA to 30
mA
Figure 4-50
RL = 4.8 kΩ
Figure 4-51
RL = 1.2 kΩ
Figure 4-52
RL = 4.8 kΩ
Figure 4-53
RL = 1.2 kΩ
Figure 4-54
Switching Frequency
VIN = 3.3 V, AVDD = 7 V, 8 V, 9 V, VGH = 16 V to 31 V
VIN, VIO1, VIO2, VCORE
VIN = 3.3 V, tSS1 = 0.5 ms, VIO1 = 2.5 V, RL = 27 Ω, VIO2 =
1.8 V, RL = ∞, VCORE = 1.1 V
Figure 4-55
EN, AVDD, VGH
VIN = 3.3 V, tSS2 = 4.0 ms, AVDD = 8.1 V, RL = 33 Ω, VGH = 24 tDLY1 = 0 ms
V, 1.2 kΩ
tDLY1 = 10 ms
Figure 4-57
XAO, AVDD, VGH, VGHM
VIN = 3.3 V, AVDD = 8.1 V, RL = 33 Ω, VGH = 24 V, RL =
1.2 kΩ, GIP = 0
tDLY6 = 0 ms
Figure 4-59
tDLY6 = 10 ms
Figure 4-60
XAO, AVDD, VGH, VGHM
VIN = 3.3 V, AVDD = 8.1 V, RL = 33 Ω, VGH = 24 V, RL =
1.2 kΩ, GIP = 1
tDLY6 = 0 ms
Figure 4-61
tDLY6 = 10 ms
Figure 4-62
RL = 3.9 Ω
Figure 4-56
Figure 4-58
AVDD, VGH, VCOM, VGAMA
VIN = 3.3 V, AVDD = 8.1 V, VGH = 24 V, VCOM = 4.05 V, VGAMA = 4.05 V
Figure 4-63
RST, VIO1, VIO2, VCORE
VDET = 2.5 V
RMODE = 0
Figure 4-64
RMODE = 1
Figure 4-65
VIN, XAO, AVDD, VGHM
GIP = 0
AVDD, VGH, VCOM, VGAMA
Figure 4-66
SMODE = 0
Figure 4-67
SMODE = 1
Figure 4-68
Gate Voltage Shaping
FLK, VGHM
VIN = 3.3 V, RE = 1 kΩ, CL = 10 nF, AVDD = 8.1 V, RL= 33 Ω, VGH = 24 V, RL = 1.2
kΩ
Figure 4-69
Op-Amp
Large-Signal Response
VPOS = 3.8 V ± 0.5 V
Figure 4-70
Small-Signal Bandwidth
AVDD = 8.1 V, VPOS2 = 63 mVPP, AV = +1, RF = 0 Ω
Figure 4-71
Gain Bandwidth
AVDD = 8.1 V, VPOS2 = 63 mVPP, AV = +1, RF = 0 Ω
Figure 4-72
Peak Output Current
AVDD = 8.1 V, RL = 2 kΩ to AVDD/2, CL = 1 μF
Figure 4-73
Line Transient Response
VIN = 3.0 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.1 V, VCOM = 4 V, RL = ∞
Figure 4-74
Output Voltage Ripple and
Noise
VIN = 3.3 V, 8.1 V, RL = 82 Ω, VCOM = 4 V, RL = ∞
Figure 4-75
Dynamic Response
AVDD = 8.1 V, RL = 909 kΩ, CL = 55 pF
Programmable Gamma
Line Transient Response
Output Voltage Ripple and
Noise
VIN = 3.0 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.1 V
VIN = 3.3 V, 8.1 V, RL = 82 Ω
GAMA = 0x0ff/0x2ff
Figure 4-76
GAMA = 0x2ff/0x0ff
Figure 4-77
GAMA = 0x0ff
Figure 4-78
GAMA = 0x1ff
Figure 4-79
GAMA = 0x2ff
Figure 4-80
GAMA = 0x1ff
Figure 4-81
Typical Characteristics
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Boost Converter 1 — Efficiency
VIN = 5 V, AVDD = 6 V, 8 V, 9.1 V
100
100
90
90
80
80
70
70
60
50
40
AVDD = 6.0 V (FREQ=0)
60
50
40
AVDD = 6.0 V (FREQ=0)
30
AVDD = 8.0 V (FREQ=0)
30
AVDD = 8.0 V (FREQ=0)
20
AVDD = 9.1 V (FREQ=0)
20
AVDD = 9.1 V (FREQ=0)
AVDD = 6.0 V (FREQ=1)
10
0
50
100
150
200
250
300
350
400
450
Iout - Output Current - mA
AVDD = 8.0 V (FREQ=1)
L=Toko 1269AS-H-4R7M
AVDD = 9.1 V (FREQ=1)
0
AVDD = 6.0 V (FREQ=1)
10
AVDD = 8.0 V (FREQ=1)
L=Toko 1269AS-H-4R7M
AVDD = 9.1 V (FREQ=1)
0
500
0
50
100
150
200
250
300
350
400
450
G402
Figure 4-1.
spacer
Figure 4-2.
spacer
Boost Converter 1 — Line Regulation
VIN = 2.6 V to 6 V, AVDD = 8 V, IAVDD = 100 mA
Boost Converter 1 — Load Regulation
VIN = 3.3 V, 5 V, AVDD = 8 V, IAVDD = 1 mA to 500 mA
8.15
8.15
8.10
8.10
8.05
8.00
7.95
7.90
500
Iout - Output Current - mA
G401
AVDD - Output Voltage - V
AVDD - Output Voltage - V
Efficiency - %
Efficiency - %
Boost Converter 1 — Efficiency
VIN = 3.3 V, AVDD = 6 V, 8 V, 9.1 V
8.05
8.00
7.95
7.90
VIN = 3.3 V
L=Toko 1269AS-H-4R7M
L=Toko 1269AS-H-2R2M
7.85
3
3.5
4
4.5
5
5.5
VIN - Input Voltage - V
12
VIN = 5.0 V
7.85
2.5
6
0
50
100
150
200
250
300
350
400
450
IAVDD - Output Current - mA
G403
Figure 4-3.
spacer
Figure 4-4.
spacer
Boost Converter 1 — Line Transient Response
VIN = 3/4.8 V, AVDD = 8.1 V, RL = 82 Ω
Boost Converter 1 — Line Transient Response
VIN = 3/4.8 V, AVDD = 8.1 V, RL= 33 Ω
Figure 4-5.
Figure 4-6.
Typical Characteristics
500
G404
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Boost Converter 1 — Load Transient Response
VIN = 3.3 V, AVDD = 8.1 V, IAVDD = 20 mA - 200 mA
Boost Converter 1 — Load Transient Response
VIN = 5 V, AVDD = 8.1 V, IAVDD = 20 mA - 200 mA
Figure 4-7.
spacer
Figure 4-8.
spacer
Boost Converter 1 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω
Boost Converter 1 — Output Voltage Ripple
VIN = 5 V, AVDD = 8.1 V, RL = 82 Ω
Figure 4-9.
spacer
Figure 4-10.
spacer
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL = 820 Ω, FREQ = 0
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL= 82 Ω, FREQ = 0
Figure 4-11.
Figure 4-12.
Typical Characteristics
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Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL = 820 Ω, FREQ = 1
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, FREQ = 1
Figure 4-13.
Figure 4-14.
VIN
Buck Converter 1 — Efficiency
VIN = 3.4 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500
mA
Boost Converter 1 — Switching Frequency
= 2.6 V to 6 V, AVDD = 6 V, 8 V, 9.1 V, RL = 82 Ω
100
90
80
1,300
70
Efficiency - %
fSW - Switching Frequency - kHz
1,500
1,100
900
700
1269AS-H-2R2M
L=Toko 1269AS-H-4R7M
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
40
30
AVDD = 6.0 V (FREQ=1)
AVDD = 8.0 V (FREQ=1)
AVDD = 9.1 V (FREQ=1)
AVDD = 6.0 V (FREQ=0)
AVDD = 8.0 V (FREQ=0)
AVDD = 9.1 V (FREQ=0)
500
60
VCORE = 1.0 V
20
VCORE = 1.1 V
10
VCORE = 1.2 V
L=Toko 1269AS-H-2R2M
VCORE = 1.3 V
0
0
6.0
VIN - Input Voltage - V
50
100
150
200
250
300
350
400
450
ICORE - Output Current - mA
G415
G416
Figure 4-15.
spacer
Figure 4-16.
spacer
Buck Converter 1 — Efficiency
VIN = 5 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, 1.3 V, ICORE = 1 mA to
500 mA
Buck Converter 1 — Line Regulation
VIN = 2.6 V to 6 V, VCORE = 1.1 V, ICORE = 300 mA
1.15
90
1.14
80
1.13
VCORE - Output Voltage - V
100
Efficiency - %
70
60
50
40
30
VCORE = 1.0 V
20
500
1.12
1.11
1.10
1.09
1.08
1.07
VCORE = 1.1 V
10
1.06
VCORE = 1.2 V
L=Toko 1269AS-H-2R2M
0
50
100
150
L=Toko 1269AS-H-4R7M
VCORE = 1.3 V
0
200
250
300
350
ICORE - Output Current - mA
400
450
1.05
500
2.5
G417
Figure 4-17.
spacer
14
3
3.5
4
4.5
VIN - Input Voltage - V
5
5.5
6
G418
Figure 4-18.
spacer
Typical Characteristics
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Buck Converter 1 — Load Regulation
VIN = 3.4 V, 5 V, VCORE = 1.1 V, ICORE = 0 mA to 500 mA
Buck Converter 1 — Line Transient Response
VIN = 3 V/4.8 V, VCORE = 1.1 V, RL = 3.9 Ω
1.15
VCORE - Output Voltage - V
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
VIN = 3.4 V
1.06
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
1.05
0
50
100
150
200
250
300
350
400
450
ICORE - Output Current - mA
500
G419
Figure 4-19.
spacer
Figure 4-20.
Buck Converter 1 — Load Transient Response
VIN = 3.3 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
Buck Converter 1 — Load Transient Response
VIN = 5 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
Figure 4-21.
Figure 4-22.
spacer
Buck Converter 1 — Output Voltage Ripple
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
Buck Converter 1 — Output Voltage Ripple
VIN = 5 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-23.
spacer
Figure 4-24.
spacer
Typical Characteristics
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Buck Converter 1 — Switching Waveforms
VIN = 3.3 V, VCORE = 1.1 V, RL = 120 Ω
Buck Converter 1 — Switching Waveforms
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-25.
spacer
Figure 4-26.
Buck Converter 1 — Switching Frequency
VCORE = 1.1 V, RL = 12 Ω
Buck Converter 2 — Efficiency
VIN = 3.3 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
100
90
80
1,300
70
Efficiency - %
fSW - Switching Frequency - kHz
1,500
1,100
900
700
60
50
40
30
20
500
VIO1 = 1.7 V
10
VIO1 = 1.8 V
L=Toko 1269AS-H-2R2M
L=Toko 1269AS-H-2R2M
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN - Input Voltage - V
0
50
100
150
200
250
300
350
400
450
IIO1 - Output Current - mA
G427
Figure 4-28.
spacer
Buck Converter 2 — Efficiency
VIN = 5 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
Buck Converter 2 — Line Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
1.80
90
1.78
80
1.76
VIO1 - Output Voltage - V
100
Efficiency - %
60
50
40
30
20
L=Toko 1269AS-H-2R2M
0
50
100
150
250
300
350
IIO1 - Output Current - mA
400
450
1.70
1.68
1.66
L=Toko 1269AS-H-2R2M
VIO1 = 2.5 V
200
1.72
1.62
VIO1 = 1.8 V
0
1.74
1.64
VIO1 = 1.7 V
10
500
G428
Figure 4-27.
70
1.60
500
2.5
G429
Figure 4-29.
spacer
16
VIO1 = 2.5 V
0
3
3.5
4
4.5
VIN - Input Voltage - V
5
5.5
6
G430
Figure 4-30.
spacer
Typical Characteristics
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Buck Converter 2 — Load Regulation
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 500 mA
Buck Converter 2 — Line Transient Response
VIN = 3/4.8 V, VIO1 = 1.7 V, RL = 27 Ω
1.80
VIO1 - Output Voltage - V
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
VIN = 3.4 V
1.62
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
1.60
0
50
100
150
200
250
300
350
400
450
IIO1 - Output Current - mA
500
G431
Figure 4-31.
spacer
Figure 4-32.
Buck Converter 2 — Load Transient Response
VIN = 3.3 V, VIO1 = 1.7 V, IIO1 = 50 mA to 100 mA
Buck Converter 2 — Load Transient Response
VIN= 5 V, VIO1 = 1.7 V, IIO1 = 50 mA to 100 mA
Figure 4-33.
Figure 4-34.
spacer
Buck Converter 2 — Output Voltage Ripple
VIN = 3.3 V VIO1 = 1.7 V, RL = 27 Ω
Buck Converter 2 — Output Voltage Ripple
VIN = 5 V VIO1 = 1.7 V, RL = 27 Ω
Figure 4-35.
spacer
Figure 4-36.
spacer
Typical Characteristics
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Buck Converter 2 — Switching Waveforms
VIN= 3.3 V, VIO1 = 1.7 V, RL = 270 Ω
Buck Converter 2 — Switching Waveforms
VIN = 3.3 V, VIO1 = 1.7 V, RL = 27 Ω
Figure 4-37.
spacer
Figure 4-38.
Buck Converter 2 — Switching Frequency
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, RL = 27 Ω
LDO Regulator — Load Regulation
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
1.85
2,000
1,800
VIO2 - Output Voltage - V
fSW - Switching Frequency - kHz
1,900
1,700
1,600
1,500
1,400
1,300
1.83
1.81
1.79
1.77
1,200
1,100
L=Toko 1269AS-H-2R2M
1.75
1,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN - Input Voltage - V
18
6.0
0
10
20
30
40
50
60
70
IIO2 - Output Current - mA
G439
80
90
100
G440
Figure 4-39.
Figure 4-40.
spacer
LDO Regulator — Line Transient Response
VIN = 3/4.8 V, VIO2 = 1.8 V, RL = 27 Ω
LDO Regulator — Load Transient Response
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA - 100 mA
Figure 4-41.
Figure 4-42.
Typical Characteristics
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LDO Regulator — Output Voltage Ripple
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
100
Boost Converter 2 — Efficiency
AVDD = 8.1 V, VGH = 20 V, 24 V, 28 V, 31 V
90
Efficiency – %
80
70
60
50
40
30
VGH=20V
VGH=24V
VGH=28V
VGH=31V
20
10
0
L=Murata LQH3NPN150NG0
0
10
20
30
40
50
G041
Figure 4-43.
Figure 4-44.
Boost Converter 2 — Line Regulation
AVDD = 6 V to 9.1 V, VGH = 24 V, IGH = 10 mA
Boost Converter 2 — Load Regulation
AVDD = 8.1 V, VGH = 24 V, IGH = 1 mA to 50 mA
24.20
24.20
24.15
24.15
24.10
VGH - Output Voltage - V
IO – Output Voltage – V
IO – Output Current – mA
24.05
24.00
23.95
23.90
23.85
6.5
7.0
7.5
24.05
24.00
23.95
23.90
23.85
L=Murata LQH3NPN150NG0
23.80
6.0
24.10
L=Murata LQH3NPN150NG0
8.0
IO – Input Voltage – V
8.5
23.80
9.0
0
G042
5
10
15
20
25
30
35
40
45
IGH - Output Current - mA
50
G446
Figure 4-45.
spacer
Figure 4-46.
spacer
Boost Converter 2 — Line Transient Response
VIN = 3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 4.8 kΩ
Boost Converter 2 — Line Transient Response
VIN = 3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 1.2 kΩ
Figure 4-47.
spacer
Figure 4-48.
Typical Characteristics
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Boost Converter 2 — Load Transient Response
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, IGH = 5-10 mA
Boost Converter 2 — Load Transient Response
VIN = 3.3 V, AVDD = 8.1 V, RL= 82 Ω, VGH = 24 V, IGH = 10-30 mA
Figure 4-49.
Figure 4-50.
Boost Converter 2 – Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 4.8 kΩ
Boost Converter 2 – Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 1.2 kΩ
Figure 4-51.
Figure 4-52.
Boost Converter 2 – Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 4.8 kΩ
Boost Converter 2 – Switching Waveforms
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VGH = 24 V, RL = 1.2 kΩ
Figure 4-53.
Figure 4-54.
20
Typical Characteristics
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Boost Converter 2 – Switching Frequency
AVDD = 7 V, 8 V, 9 V, VGH = 16 V to 24 V, RL = 4.8 kΩ
Power-up Sequencing
VIN, VIO1, VIO2, VCORE
fSW - Switching Frequency - kHz
550
500
450
400
350
AVDD=7V
300
AVDD=8V
L=Murata LQH3NPN150NG0
AVDD=9V
250
16
18
20
22
24
26
28
VGH - Output Voltage - V
30
G455
Figure 4-55.
Figure 4-56.
Power-up Sequencing
EN, AVDD, VGH (tDLY1 = 0 ms)
Power-up Sequencing
EN, AVDD, VGH (tDLY1 = 10 ms)
Figure 4-57.
Figure 4-58.
Power-up Sequencing – GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-up Sequencing – GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-59.
Figure 4-60.
Typical Characteristics
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Power-up Sequencing – GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-up Sequencing – GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-61.
Figure 4-62.
Power-up Sequencing
AVDD, VGH, VCOM, VGAMA
Power-down Sequencing — RMODE = 0
RST, VIO1, VIO2, VCORE
Figure 4-63.
Figure 4-64.
Power-down Sequencing – RMODE = 1, VDET = 2.5 V
RST, VIO1, VIO2, VCORE
Power-down Sequencing – GIP = 0
VIN, XAO, AVDD, VGHM
Figure 4-65.
Figure 4-66.
Typical Characteristics
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Power-down Sequencing – SMODE = 0
AVDD, VGH, VCOM, VGAMA
Power-down Sequencing – SMODE = 1
AVDD, VGH, VCOM, VGAMA
Figure 4-67.
Figure 4-68.
Gate Voltage Shaping — FLK, VGHM
AVDD = 8.1 V, RL = 33 Ω, VGH = 24 V, RL = 1.2 kΩ, RE = 1 kΩ, CL =
10 nF
VCOM Buffer — Large Signal Response
AVDD = 7.6 V, RL= 82 Ω, VPOS = 3.8 V + 0.5 VPP
Figure 4-69.
Figure 4-70.
VCOM Buffer — Small-Signal Bandwidth
AVDD = 8.1 V, VPOS = 4 V + 65 mVpp
VCOM Buffer — Gain-Bandwidth Product
AVDD = 8.1 V, VPOS = 4 V + 65 mVpp
Figure 4-71.
Figure 4-72.
Typical Characteristics
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VCOM Buffer — Peak Output Current
VIN = 3.3 V, AVDD = 8.1 V, RL = 2 kΩ to AVDD/2, CL = 1 μF
VCOM Buffer — Line Transient Response
VIN = 3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, VCOM= 4 V, RL = ∞
Figure 4-73.
Figure 4-74.
VCOM Buffer — Output Voltage Ripple & Noise
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, VCOM = 4 V, RL = ∞
Programmable GAMMA — Dynamic Response
GAMA = 0x0ff to 0x2ff, RL = 909 kΩ, CL = 55 pF
Figure 4-75.
Figure 4-76.
GAMMA Voltage — Dynamic Response
GAMA = 0x2ff to 0x0ff, RL = 909 kΩ, CL = 55 pF
Programmable GAMMA — Line Transient Response
VIN = 3.3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, GAMA = 0x0ff
Figure 4-77.
Figure 4-78.
Typical Characteristics
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Programmable GAMMA — Line Transient Response
VIN = 3.3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, GAMA = 0x1ff
Programmable GAMMA — Line Transient Response
VIN = 3.3/4.8 V, AVDD = 8.1 V, RL = 82 Ω, GAMA = 0x2ff
Figure 4-79.
Figure 4-80.
Programmable GAMMA — Output Voltage Ripple & Noise
VIN = 3.3 V, AVDD = 8.1 V, RL = 82 Ω, GAMA = 0x1ff
Figure 4-81.
Typical Characteristics
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5 Detailed Description
An internal block diagram of the TPS65642 is shown in Figure 5-1.
EN
Internal
VUVLO
+
–
VDET
XAO
Sequencing
RST
+
–
SW2
VIN
Buck 1
VCORE
SW3
Buck 2
VIO1
LDO
SW1
Boost 1
COMP
VIO2
AVDD
TCOMP
Temperature
Compensation
SW4
Boost 2
VGH
Gate Voltage
Shaping
FLK
VGHM
RE
OUTA
Programmable
Gamma
AVDD
OUTN
RSET
Programmable
VCOM
AVDD
POS1
+
NEG1
–
POS2
+
NEG2
–
OUT1
OUT2
SCL
2
SDA
IC
Interface
Internal
WP
Figure 5-1. Internal Block Diagram
26
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5.1
SLVSBX6 – JULY 2013
BOOST CONVERTER 1 (AVDD)
Boost converter 1 is synchronous and uses a virtual current mode topology that:
• achieves high efficiencies
• allows the converter to work in continuous conduction mode under all operating conditions, simplifying
compensation
• provides a better drive signal for the negative charge pump connected to the switch node (because the
converter always runs in continuous conduction mode, even at low output currents)
• provides true input-output isolation when the boost converter is disabled
VIN
AVDD
VIN
SW1
Q1B
AVDD
AVDD
FREQ
VREF
AVDD
PWM
Control
+
–
SMODE
&
Q1A
Q2
UVLO
GND
COMP
Figure 5-2. Boost Converter 1 Internal Block Diagram
5.1.1
Switching Frequency (Boost Converter 1)
Boost converter 1's nominal switching frequency can be programmed to 750 kHz or 1200 kHz using the
FREQ bit in the MISC register.
5.1.2
Compensation (Boost Converter 1)
Boost converter 1 uses an external compensation network connected to the COMP pin to stabilize its
feedback loop. A simple series R-C network connected between the COMP pin and ground is sufficient to
achieve good performance, that is, stable and with good transient response. Good starting values, which
will work for most applications, are 100 kΩ and 1 nF for 1200 MHz AVDD switching frequency and 56 kΩ
and 1.5 nF for 750 kHz AVDD switching frequency.
In some applications (e.g. those using electrolytic output capacitors), it may be necessary to include a
second compensation capacitor between the COMP pin and ground (typically 22 pF). This has the effect
of adding an additional pole in the feedback loop's frequency response, which cancels the zero introduced
by the output capacitor's ESR.
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The COMP pin is directly connected to the input of the converter's current comparator, which means that
any noise present on this pin can directly affect converter operation. In practical applications the most
likely source of noise is the converter's switch pin, and for proper operation it is essential that the stray
capacitance between the SW1 and the COMP pins is minimized. This can be ensured using good PCB
layout practices, such as:
•
•
•
locating the compensation components close to the COMP pin
removing the GND plane from underneath the SW1 PCB tracks (to prevent this high dV/dt signal from
inducing currents locally in the GND plane)
connecting the ground side of the compensation components to a noise-free GND location, that is,
away from noisy power ground signals
For the most robust operation, it is recommended to ensure that the parasitic capacitance between the
SW1 and COMP is below 0.1 pF.
5.1.3
Power-Up (Boost Converter 1)
Boost converter 1 starts tDLY1 milliseconds after EN or RST goes high, whichever occurs later. Delay time
tDLY1 can be programmed from 0 ms to 70 ms using the DLY1 register. Once asserted, the EN signal must
remain high to ensure normal device operation. Once disabled (EN = 0), boost converter 1 remains
disabled until the device is powered down (even if EN is re-asserted).
To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS2 milliseconds.
Start-up time tSS2 can be programmed from 4 ms to 7.5 ms using the SS2 register. Longer soft-start times
generate lower inrush currents.
The same ramp rate is also used for boost converter 2 – changing the SS2 register affects both boost
converters.
The soft-start function is not implemented if boost converter 1's output voltage is re-programmed during
operation. This is not a problem during normal operation (when AVDD remains constant), however, it may
cause problems during production if AVDD is changed while the converter is enabled. Problems can occur
under such conditions because, without a soft-start, the converter draws a high inrush current when its
output voltage is changed. If the converter is supplied from a high-impedance source, this inrush current
can, under certain circumstances, pull VIN below the UVLO threshold, disabling the IC and interrupting the
writing of the configuration parameters. One or more of the following recommendations can be used to
ensure trouble-free configuration during production:
•
•
•
•
5.1.4
program the configuration parameters before the IC is soldered to the PCB
supply the PCB with a voltage high enough to ensure that the voltage on the VIN pin remains above
the UVLO threshold when the value of AVDD is changed
ensure that the supply impedance is low enough to ensure that the voltage on the VIN pin remains
above the UVLO threshold when the value of AVDD is changed
disable boost converter 1 while the value of AVDD is changed
Power-Down (Boost Converter 1)
Boost converter 1 is disabled when EN=0 or VIN VUVLO (the same time the LDO regulator starts), and implements
the same voltage ramping as buck converter 1.
5.3.3
Power-Down (Buck Converter 2)
Buck converter 2 is disabled and actively discharges its output when VIN < VUVLO.
5.4
LDO REGULATOR (VIO2)
In applications in which the timing controller and source drivers use different I/O voltages, the LDO
regulator can be used to generate the lower I/O supply voltage VIO2. The LDO regulator is supplied from
the VIO1 pin, which is the output of buck converter 2.
30
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VIO1
VIO2
+
–
DAC
VIO2
Figure 5-5. Linear Regulator Block Diagram
5.4.1
Output Voltage (LDO Regulator)
When VIO1 = 2.5 V, the LDO regulator's output voltage can be programmed to 1.7 V or 1.8 V using the
VIO register. To ensure reliable LDO programming, EN has to be "high" and the power-up sequence must
be over (tDLY6). When VIO1 = 1.7 V or 1.8 V, the LDO regulator is disabled.
5.4.2
Power-Up (LDO Regulator)
At power up, the LDO regulator starts as soon as VIN > VUVLO (the same time buck converter 1 and buck
converter 2 starts). It ramps its output linearly from zero to VIO2 in tSS1 milliseconds. Soft-start time tSS1 can
be programmed from 0.5 ms to 4 ms using the SS1 register.
The same ramp rate is used for both buck converters and the LDO regulator. Changing the SS1 register
affects all three regulators.
When the LDO is turned on/off during normal device operation (that is, programming VIO1 from 1.7V to
2.5V or vice versa), the ramp or discharge characteristic is defined by the load connected.
5.4.3
Power-Down (LDO Regulator)
The LDO regulator is supplied from the VIO1 pin, which is actively discharged during power-down. The
LDO regulator's output therefore discharges through transistor Q1's body diode as long as VIO2 is high
enough to forward bias it. Thereafter, VIO2 continues to discharge through the load connected to it.
5.5
BOOST CONVERTER 2 (VGH)
Boost converter 2 is non-synchronous, and uses a constant off-time topology. The converter's switching
frequency is not constant, but adapts itself to VIN and VGH. Boost converter 2 uses peak current control
and is designed to operate permanently in discontinuous conduction mode (DCM), thereby allowing the
internal compensation circuit to achieve stable operation over a wide range of output voltages and
currents, that is, when temperature compensation is used.
A simplified block diagram of boost converter 2 is shown in Figure 5-6.
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AVDD
VGH
AVDD
VGH
SW4
PWM
Control
Q1
–
27:1
+
Temperature
Compensation
VGHCOLD
VGHHOT
GND
TCOMP
RT1
RNTC
RT2
Figure 5-6. Boost Converter 2 Block Diagram
Boost converter 2 can be temperature compensated, allowing its output voltage to transition from a higher
voltage at low temperatures VGH(COLD) to a lower voltage at high temperatures VGH(HOT) (see Figure 5-7
and Figure 5-8). The values of VGH(HOT) and VGH(COLD) are programmed using the VGHHOT and
VGHCOLD registers. The values of THOT and TCOLD are programmed by selecting the appropriate resistor
values for the thermistor network connected to the TCOMP pin.
VGH
VGH(COLD)
VGH(HOT)
TCOLD
THOT
Temperature
Figure 5-7. Boost Converter 2 Temperature Compensation Characteristic
32
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1.429V
TCOMP
RT1
+
DAC1
A1
Q1
−
ISET
0.893V
1.107V
RNTC
RT2
R1
R2
+
DAC2
A2
−
PWM
Controller
0.571V
VGH
R4
R3
R2 = 2∙R1
R4 = 27∙R3
Figure 5-8. Boost Converter 2 Temperature Compensation Block Diagram
Referring to Figure 5-8, temperature compensation works as follows:
The thermistor network formed by RT1, RT2 and RNTC (1) generates a voltage at the TCOMP pin whose
value decreases with increasing temperature.
With proper selection of the external components RT1, RT2 and RNTC, temperatures THOT and TCOLD can
be configured to suit each display's characteristics. A Microsoft Excel® spreadsheet allowing easy
calculation of component values is available from Texas Instruments free of charge.
5.5.1
Power-Up (Boost Converter 2)
Boost converter 2 is enabled when AVDD has finished ramping up. To minimize inrush current during startup, boost converter 2 ramps VGH linearly to its programmed value in tSS2 seconds. Soft-start time tSS2 can
be programmed from 4 ms to 7.5 ms using the SS2 register. The same ramp rate is also used for boost
converter 1. Changing SS2 affects both boost converters.
5.5.2
Power-Down (Boost Converter 2)
Boost converter 2 is disabled when EN = 0 or VIN < VUVLO. The converter's output is not actively
discharged when the converter is disabled. Once disabled (EN = 0), boost converter 1 remains disabled
until the device is powered down (even if EN is re-asserted).
5.5.3
Setting the Output Voltage (Boost Converter 2)
The output voltage of boost converter 2 at cold temperatures can be programmed from 25 V to 40 V (2)
using the VGHCOLD register. The output voltage of boost converter 2 at hot temperatures can be
programmed from 16 V to 31 V using the VGHHOT register.
Note that if the VGHCOLD register is programmed with a lower voltage than the VGHHOT register, the
output voltage VGH will be regulated at VGH(HOT), regardless of the temperature.
In applications that do not require temperature compensation, the TCOMP pin should be tied to ground
and the VGHHOT register used to set the voltage of VGH.
From Figure 5-8, it can be seen that, between VGHHOT and VGHCOLD, boost converter 2's output voltage is
given by
VGH = 28 ´ (VDAC2 + 3 ´ ( VTCOMP - VDAC2 ))
(1)
(1)
(2)
RT should be a negative temperature coefficient (NTC) type whose resistance at 25°C is 10 kΩ.
Output voltages greater than 36 V require an external cascode transistor.
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Equation 1 can be used to calculate the voltage required on the TCOMP pin at temperatures THOT and
TCOLD.
V
VTCOMPHOT = GHHOT
28
(2)
2 ´ VGHHOT + VGHCOLD
VTCOMPCOLD =
84
(3)
Equation 4 can be used to calculate the appropriate value for RT2
2
R T2 =
- b ± b - 4ac
2a
(4)
Where
V
- VTCOMPHOT
a = RNTCCOLD - RNTCHOT - TCOMPCOLD
ISET
(5)
æV
- VTCOMPHOT ö
b = (RNTCCOLD + RNTCHOT ) ´ ç TCOMPCOLD
÷
I
è
ø
SET
(6)
æV
- VTCOMPHOT ö
c = (R NTCCOLD ´ RNTCHOT ) ´ ç TCOMPCOLD
÷
ISET
è
ø
(7)
and RNTCCOLD and RNTCCOLD are the resistances of the thermistor at temperatures TCOLD and THOT
respectively.
Once the value of RT2 has been calculated, Equation 8 can be used to calculate the appropriate value of
RT1.
æV
ö æR
´ RT2 ö
RRT1 = ´ ç TCOMPCOLD ÷ - ç NTCCOLD
÷
ISET
è
ø è R NTCCOLD + R T2 ø
(8)
5.5.4
Protection (AVDD, VCORE, VIO1, VIO2, VGH)
Each voltage regulator is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if a regulator output falls below 70% of its programmed voltage for longer than
50 ms, in which case the IC is disabled. To recover normal operation following an undervoltage condition,
the cause of the error condition must be removed and the supply voltage VIN cycled. A short-circuit
condition is detected if a regulator output falls below 30% of its programmed voltage, in which case the IC
is disabled immediately. To recover normal operation following a short-circuit condition, the cause of the
error must be removed and the supply voltage VIN cycled.
5.6
RESET GENERATOR
The RST pin generates an active-low reset signal for the timing controller. During power-up, the reset
timer starts when VCORE has finished ramping. The reset pulse duration tRESET can be programmed from 2
ms to 16 ms using the RESET register. The RST signal is latched when it goes high and will not be taken
low again until the device is powered down (even if VCORE temporarily falls out of regulation). The active
power-down threshold (VUVLO or VDET) can be selected using the RMODE bit in the CONFIG register.
The RST output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in
the range 10 kΩ to 100 kΩ are recommended for most applications.
5.7
GATE VOLTAGE SHAPING
The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the
LCD panel's gate ON voltage (VGH). Figure 5-9 shows a block diagram of the gate voltage shaping
function and Figure 5-10 shows the typical waveforms during operation.
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VGH
VGH
Q1
FLK
VGHM
Control
Logic
FLK
VGHM
Q2
RE
RE
Figure 5-9. Gate Voltage Shaping Block Diagram
VPG4
VIO2
FLK
Don’t Care
tDLY6
VGHM
VGH
Figure 5-10. Gate Voltage Shaping Waveforms
Gate voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2 is off, and VGHM is
equal to VGH. On the falling edge of FLK, Q1 is turned off, Q2 is turned on, and the LCD panel load
connected to the VGHM pin discharges through the external resistor connected to the RE pin.
During power-up Q2 is held permanently on and Q1 permanently off, regardless of the state of the FLK
signal, until tDLY6 milliseconds after boost converter 2 (VGH) has finished ramping. The value of tDLY6 can
be programmed from 0ms to 35ms using the DLY6 register.
During power-down Q1 is held permanently on and Q2 permanently off, regardless of the state of the FLK
signal.
5.7.1
Recommended Connection when Gate Voltage Shaping not Used
Non-GIP/Non-ASG panels that do not use the gate voltage shaping function should leave the RE pin
floating and connect the FLK pin to either VIN or GND.
5.8
PANEL RESET / LCD BIAS READY (XAO)
The TPS65642 provides an output signal via its XAO pin that can be used to reset a level shifter or gate
driver IC during power-up and power-down. The GIP bit in the CONFIG register defines whether the XAO
pin works in GIP mode or non-GIP mode.
The primary purpose of the XAO signal in non-GIP applications is to drive the outputs of the display
panel's gate driver IC high during power-down by generating an active-low signal. When the GIP = 0, the
XAO pin is pulled low whenever VIN < VDET. The VDET threshold voltage can be configured using the VDET
register.
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When the GIP = 1, the XAO output is used to delay the start of level shifter activity during power-up. The
delay time tDLY6 starts when VGH has finished ramping up, and can be configured using the DLY6 register.
The XAO output is an open-drain type and requires an external pull-up, typically in the range 10 kΩ to
100 kΩ.
5.9
PROGRAMMABLE VCOM CALIBRATOR (VCOM)
The programmable VCOM calibrator uses a digital-to-analog converter (DAC) to generate an offset current
IDAC for an external resistor divider connected to AVDD (see Figure 5-11 and Figure 5-12). Higher values of
the 7-bit digital word N written to the DAC generate higher IDAC sink currents, and therefore lower VCOM
voltages.
Figure 5-11 shows the recommended circuit for the most commonly used application, when the LCD panel
requires only one VCOM supply voltage. The second op-amp is shown wired as a unity-gain buffer whose
input is tied to GND (the recommended configuration if it is not used), however, it is perfectly acceptable
to use it for other things, such as generating a half-AVDD supply rail.
AVDD
R3
IDAC
POS1
POS1
DAC
VCOM
+
OUT1
VCOM1
NEG1
–
R5
ISET
SMODE
&
VIN < VUVLO
VREF
VFB1
+
POS2
–
+
NEG2
–
OUT2
VCOM2
RSET
RSET
Figure 5-11. Single Programmable VCOM Supply
The external resistor RSET generates a reference current ISET for the DAC. Since this reference current is
also used by boost converter 2's temperature compensation function, care should be taken to ensure that
a suitable value is chosen. For most applications, a value of 24.9 kΩ is recommended, which generates a
reference current given by
V
ISET = REF
RSET
ISET =
1.25 V
24.9 kW
= 50.2 m A
(9)
The output current IDAC sunk by the DAC is given by:
(N + 1)´ ISET
IDAC =
128
(10)
where N is the 7-bit word written to the DAC, and ranges from 0 to 127.
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Equation 11 and Equation 12 can be used to select appropriate values for R3 and R5.
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ VCOM(MAX) + DVCOM
(
R5 =
)
(11)
128 ´ D VCOM ´ R3
(127 ´ ISET ´ R3 ) - (128 ´ DVCOM )
(12)
Figure 5-12 shows the recommended connection for the case when two VCOM supplies VCOM1 and VCOM2
are to be generated.
AVDD
R3
IDAC
POS1
POS1
VCOM
DAC
+
OUT1
VCOM1
NEG1
–
ISET
SMODE
&
VIN < VUVLO
VREF
VFB1
R4
+
POS2
–
+
NEG2
–
OUT2
VCOM2
R5
RSET
RSET
VFB2
Figure 5-12. Dual Programmable VCOM Supplies
In Figure 5-12, the voltage VCOM2 generated by the second op-amp is slightly lower than VCOM1. If two
identical VCOM supplies are required, these can be generated by setting R4=0.
Equation 13 through Equation 15 can be used to calculate the correct values for R3 through R5 for the
case when two (slightly different) VCOM voltages are required:
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ VCOM1(MA X) + DVCOM
(13)
(
æ VCOM2(MAX)
R4 = ç
ç
è VCOM1(MAX)
)
ö æ
ö
128 ´ DVCOM ´ R3
÷´ ç
÷ ç (127 ´ ISET ´ R3 ) - (128 ´ DVCOM ) ÷÷
ø
ø è
(14)
æ VCOM1(MAX) - VCOM2(MAX) ö æ
ö
128 ´ DVCOM ´ R3
÷ ´ç
R5 = ç
÷
ç
÷ ç
÷
VCOM1(MAX)
è
ø è (127 ´ ISET ´ R3 ) - (128 ´ DVCOM ) ø
(15)
A Microsoft Excel® spreadsheet is available free of charge that calculates the values of R3, R4 and R5 –
contact your local sales representative for a copy.
5.9.1
Operational Amplifier Performance
Like most op amps, the VCOM op amps are not designed to drive purely capacitive loads, so it is not
recommended to connect a capacitor directly to their outputs in an attempt to increase performance;
however, the amplifiers are capable of delivering high peak currents that make such capacitors
unnecessary.
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High-speed op amps such as those in the TPS65642 require care when using them. The most common
problem is when parasitic capacitance at the inverting input creates a pole with the feedback resistor,
reducing amplifier stability. Two things can be done to minimize the likelihood of this happening. Both of
these work by shifting the pole (which can never be completely eliminated) to a frequency outside the op
amp's bandwidth, where it has no effect.
• Reduce the value of the feedback resistor. In applications where no feedback from the panel is used,
the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be
used, a small capacitor (10pF–100pF) across the feedback resistor will minimize ringing.
• Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB
traces between the feedback resistor and the inverting input, and by removing ground planes and other
copper areas above and below this PCB trace.
5.9.2
Power-Up (Programmable VCOM)
The programmable VCOM is enabled when AVDD> ≈ 3 V.
5.9.3
Power-Down (Programmable VCOM)
The programmable VCOM supports two kinds of power-down behavior, and the SMODE bit in the CONFIG
register determines which one is active (see Figure 5-41 and Figure 5-42).
If SMODE = 0, the active discharge transistor Q1 is permanently disabled; during power-down, VCOM
tracks AVDD until it is too low to support operation. If SMODE = 1, Q1 turns on when VIN
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