TPS65642A
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SLVSC21 – OCTOBER 2013
LCD Bias With Integrated Gamma Reference for Notebook PCs, Tablet PCs and Monitors
Check for Samples: TPS65642A
1 Introduction
1.1
Features
123
• 2.6 V to 6 V Input Voltage Range
• Synchronous Boost Converter (AVDD)
• Non-Synchronous Boost Converter With
Temperature Compensation (VGH)
• Synchronous Buck Converter (VCORE)
• Synchronous Buck Converter (VIO1)
• Low Dropout Linear Regulator (VIO2)
• Programmable VCOM Calibrator With Two
Integrated Buffer Amplifiers
• Gate Voltage Shaping
1.2
•
•
•
• Panel Discharge Signal (XAO)
• System Reset Signal (RST)
• 14-Channel, 10-Bit Programmable Gamma
Voltage Correction
• On-Chip EEPROM with Write Protect
• I2C™ Interface
• Thermal Shutdown
• Supports GIP and Non-GIP Displays
• 56-Ball, 3,16-mm × 3,45-mm 0,4-mm Pitch
DSBGA
Applications
Notebook PCs
Tablet PCs
Monitors
1.3
Description
The TPS65642A device is a compact LCD bias solution primarily intended for use in notebook and tablet
PCs. The device comprises two boost converters to supply the source driver and gate driver, or level
shifter, of the LCD panel; two buck converters and a low-dropout (LDO) linear regulator to supply the
system logic voltages; a programmable VCOM generator with two high-speed amplifiers; 14-channel
gamma-voltage correction; and a gate-voltage shaping function.
VIN
VIO1
AVDD
Boost Converter 1
AVDD
Buck Converter 1
VCORE
Buck Converter 2
VIO1
LDO Regulator
VIO2
Boost Converter 2
VGH
RST
Reset Generator
VGH
2
IC
XAO
Gate Voltage Shaping
VGHM
Programmable
Gamma Voltages
14
Programmable
VCOM + Buffers
2
VGAM
VCOM
2
I C Interface
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excel is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS65642A
SLVSC21 – OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Electrical Specifications
ABSOLUTE MAXIMUM RATINGS (1)
2.1
over operating free-air temperature range (unless otherwise noted)
Pin
voltage
MIN
MAX
UNIT
VIN, SW2, VCORE, SW3, VIO1, VIO2 RSET, COMP, SCL, SDA,
EN, FLK, WP, TCOMP, XAO, RST
–0.3
7
V
AVDD, SW1, OUT1, OUT2, OUTA-OUTN
–0.3
12
V
SW4
–0.3
36 (2)
V
POS1, NEG1, POS2, NEG2
–0.3
12 (3)
V
2
V
–0.3
40 (5)
V
Human Body Model
2000
V
Machine Model
200
V
Charged Device Model
700
V
|POS1-NEG1|
(4)
, |POS2-NEG2|
(4)
VGH, VGHM, RE
ESD
Rating
TA
Ambient temperature
–40
85
°C
TJ
Junction temperature
–40
150
°C
TSTG
Storage temperature
–65
150
°C
300
°C
Lead temperature (soldering, 10 seconds)
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VGH supplies up to 40 V can be generated, but require an external cascode transistor or charge pump.
For supply voltages less than 12 V, the absolute maximum input voltage is equal to the supply voltage.
Differential input voltage.
The combination of low temperatures and high VGH voltages can cause increased leakage current through the RE pin. In GIP
applications that do not use the gate-voltage shaping function it is recommended to leave the RE pin open to minimize this effect.
THERMAL INFORMATION (1)
2.2
TPS65642A
THERMAL METRIC
YFF
UNIT
56 PINS
θJA
Junction-to-ambient thermal resistance
45
θJCtop
Junction-to-case (top) thermal resistance
0.2
θJB
Junction-to-board thermal resistance
6.4
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
6.1
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2.3
RECOMMENDED OPERATING CONDITIONS
MIN
VIN
Input voltage range
2.6
TYP
MAX
UNIT
6
V
BOOST CONVERTER 1
AVDD
Boost converter 1 output voltage range
10.1
V
IAVDD
Boost converter 1 output current when 6 V ≥ VIN ≥ 4 V
700 (1)
mA
Boost converter 1 output current when 3.63 V ≥ VIN ≥ 2.64 V
400 (1)
mA
(1)
2
7
This figure includes the current that must be supplied to the input of boost converter 2.
Electrical Specifications
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RECOMMENDED OPERATING CONDITIONS (continued)
MIN
TYP
MAX
UNIT
L
Boost converter 1 inductor range
2.2
4.7
10
µH
COUT
Boost converter 1 output capacitance
10
µF
BOOST CONVERTER 2
AVDD
Input voltage range
7
8.4
16
24
10.1 (2)
V
VGH
Output voltage range
IGH
Output current
L
Inductor
10
15
COUT
Output capacitance
1
4.7
µF
RNTC
Thermistor resistance at 25°C
10
kΩ
15
40
(3)
40
V
mA
µH
BUCK CONVERTER 1 (VCORE)
VCORE
Output voltage
ICORE
Output current
L
Inductor
COUT
Output capacitance
1
1.1
1
2.2
4.7
10
1.3
V
600
mA
4.7
µH
22
µF
BUCK CONVERTER 2 (VIO1)
VIO1
Output voltage
IIO1
Output current
L
Inductor
COUT
Output capacitance
1.7
2.5
V
200 (4)
mA
1
2.2
4.7
µH
4.7
10
22
µF
1.8
V
200
mA
10
µF
LDO Regulator (VIO2)
VIO2
Output voltage
IIO
Output current
COUT
Output capacitance
1.7
4.7
PROGRAMMABLE VCOM
ISET
Programmable VCOM set current
50
µA
PROGRAMMABLE GAMMA CORRECTION
IGAM
Output current per channel
CGAM
Output capacitance
(2)
(3)
(4)
–100
100
µA
50
pF
VGH− AVDD must be greater than 9 V.
Output voltages greater than 36 V require an external cascode transistor.
This figure includes the current supplied to the input of the linear regulator.
2.4
ELECTRICAL CHARACTERISTICS
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V (1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Converters not switching
1.9
3
mA
Pin G5.
0.1
1
Pin B7. No load on gamma reference outputs
4.3
6
Pin F4. No load on op-amp outputs
4.0
7.5
No load on VGHM
0.1
1
POWER SUPPLY
Supply current into VIN pins
IIN
Supply current into AVDD pins
Supply current into VGH
mA
mA
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
VIN rising
2.3
2.42
2.5
VIN falling
2.1
2.19
2.4
Hysteresis
(1)
V
0.23
When VIO1 = 1.7 V or 1.8 V, the LDO regulator is disabled. When VIO1 = 2.5 V, the LDO regulator is enabled.
Electrical Specifications
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ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN = 2.64 V
1
1.8
VIN = 3.3 V
1.1
1.8
VIN = 6 V
1.7
1.8
UNIT
CONTROL PINS (EN, FLK, WP)
VIH
VIL
EN high-level input voltage threshold
EN low-level input voltage threshold
EN rising
EN falling
VIN = 2.64 V
0.7
VIN = 3.3 V
0.7
1
VIN = 6 V
0.7
1.6
V
0.9
V
IIH
EN high-level input current
EN = 2.5 V
–100
100
nA
IIL
EN low-level input current
EN = 0 V
–100
100
nA
VIN = 2.64 V
VIH
FLK high-level input voltage threshold
FLK rising
VIN = 3.3 V
VIN = 6 V
VIL
FLK low-level input voltage threshold
FLK falling
0.9
1.8
1
1.8
1.4
1.8
VIN = 2.6 V
0.6
0.8
VIN = 3.3 V
0.6
0.9
VIN = 6 V
0.6
1.3
V
V
IIH
FLK high-level input current
FLK = 2.5 V
–100
100
nA
IIL
FLK-low-level input current
FLK = 0 V
–100
100
nA
VIH
VIL
RPULL-UP
WP high-level input voltage threshold
WP low-level input voltage threshold
WP rising
WP falling
VIN = 2.64 V
1
1.8
VIN = 3.3 V
1.1
1.8
VIN = 6 V
1.7
1.8
VIN = 2.64 V
0.7
VIN = 3.3 V
0.7
1
VIN = 6 V
0.7
1.6
30
52
WP internal pullup resistance
V
0.9
V
75
kΩ
BOOST CONVERTER 1 (AVDD)
AVDD
Output voltage range
Tolerance
7
10.1
–1%
1%
V
VUVP
Undervoltage protection threshold
AVDD falling
65
70
75
% of
AVDD
VSCP
Short-circuit threshold
AVDD falling
25
30
35
% of
AVDD
ILK
Switch leakage current
VSW = VIN = 3.3 V, EN = 0 V, TJ = –40°C to 85°C
10
µA
rDS(ON)
Switch ON resistance
ISW = 1 A
114
250
mΩ
ILIM
Switch current limit
rDS(ON)
Rectifier ON resistance
fSW
Switching frequency
rDS(ON)
Discharge ON resistance
2.5
ISW = 1 A
3
3.5
A
242
400
mΩ
FREQ = 0
750
FREQ = 1
1200
IAVDD = 10 mA
76
kHz
100
Ω
BUCK CONVERTER 1 (VCORE)
VCORE
Output voltage
1
Tolerance
1.1
–3%
1.3
3%
V
VUVP
Undervoltage protection threshold
VCORE falling
65
70
75
% of
VCORE
VSCP
Short-circuit threshold
VCORE falling
25
30
35
% of
VCORE
ILIMA
Switch current limit
ISW ramps from 0 A to 2 A
0.8
A
rDS(ON)
Switch ON resistance
tOFF
Off time
4
1
1.2
High-side, ISW = ILIM
183
310
Low-side, ISW = 1 A
95
150
VIN = 3.3 V
260
370
480
VIN = 5 V
380
560
750
Electrical Specifications
mΩ
ns
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ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
1.7
1.8
MAX
UNIT
BUCK CONVERTER 2 (VIO1)
Output voltage
VIO1
Tolerance
–3%
2.5
V
3%
VUVP
Undervoltage protection threshold
VIO1 falling
65
70
75
% of
VIO1
VSCP
Short-circuit threshold
VIO1 falling
25
30
35
% of
VIO1
ILIM
High-side switch current limit
High-side, ISW ramps from 0 A to 2 A
0.8
1
1.2
A
High-side switch ON resistance
ISW = ILIM
183
350
Low-side switch ON resistance
ISW = 1 A
255
400
rDS(ON)
tOFF
Off time
rDS(ON)
Discharge ON resistance
VIN = 3.3 V
170
250
330
VIN = 5 V
250
370
500
15
50
Measured with 10 mA
mΩ
ns
Ω
LINEAR REGULATOR (VIO2) (2)
Output voltage
VIO2
Tolerance
IIO2 = 1 mA
1.7
1.8
–3%
3%
V
VUVP
Undervoltage protection threshold
VIO2 falling
65
70
75
% of
VIO2
VSCP
Short circuit threshold
VIO2 falling
25
30
35
% of
VIO2
BOOST CONVERTER 2 (VGH)
Output voltage range
VGH
Tolerance
16
40 (3)
–3%
3%
V
VUVP
Undervoltage protection threshold
VGH falling
65
70
75
% of VGH
VSCP
Short-circuit threshold
VGH falling
25
30
35
% of VGH
ILK
Switch leakage current
VEN = 0 V; VSW4 = 36 V
10
µA
rDS(ON)
Switch ON resistance
ISW = 1 A
tON(MAX)
Maximum tON time
tOFF
tOFF time
ITCOMP
Thermistor reference current
ISET = 50 μA, VTCOMP = 1 V
85°C
0.41
1
Ω
1
1.67
2.5
µs
1.5
2.11
3
µs
48
25°C
54
50
µA
RESET (RST)
Reset pulse duration range
Tolerance
Measured from end of VCORE ramp to 50% of RST rising
edge with a 10k pullup resistor
VOL
Low output voltage
IRST = 1 mA (sinking)
IOH
High output current
VRST = 2.5 V
tRESET
2
16
–20%
30%
0.27
–1
ms
0.5
V
1
µA
PROGRAMMABLE GAMMA CORRECTION
VDROPH
High-side output voltage drop
VDROPL
Low-side output voltage drop
Code = 1023; load = 10 µA, sourcing
5.6
100
Code = 1023; load = 100 µA, sourcing
44.2
200
Code = 0; load = 10 µA, sinking
49.1
100
Code = 0; load = 100 µA, sinking
65.5
200
mV
mV
Offset
Code = 512
–25
25
mV
INL
Integral nonlinearity
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
–3.6
5.9
LSB
DNL
Differential nonlinearity
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
–1
1.5
LSB
PROGRAMMABLE VCOM CALIBRATOR
SETZSE
Set zero-scale error
–1
1
LSB
SETFSE
Set full-scale error
–7
7
LSB
VRSET
Voltage on RSET pin
DNL
Differential nonlinearity
(2)
(3)
IRSET = 50 µA
–2%
–1
1.25
2%
V
1.5
LSB
LDO is enabled, when VIO1 = 2.5 V.
Output voltages greater than 36 V require an external cascode transistor or charge pump circuit.
Electrical Specifications
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ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
TEST CONDITIONS
MIN
TYP
AVOL
Open loop gain
PARAMETER
VCM = AVDD / 2, VOUT1 = 2 V, VOUT2 = AVDD –2 V, RL = ∞
70
91
VIO
Input offset voltage
VCM = AVDD / 2, VOUT = AVDD / 2
IB
Input bias current
VCM = AVDD / 2, VOUT = AVDD / 2
VDROPH
High-side voltage drop
VPOS = AVDD / 2, VNEG = AVDD / 2 – 1 V,
IOUT = 10 mA sourcing
VDROPL
Low-side voltage drop
VPOS = AVDD / 2, VNEG = AVDD / 2 + 1 V,
IOUT = 10 mA sinking
UNIT
–15
15
mV
–150
150
nA
0.05
0.1
V
0.03
0.1
V
dB
VCM = AVDD / 2, VSIGNAL = 2 VPP, open-loop,
RL = ∞, CL = 1 µF
200
Low-side peak output current
CMRR
Common-mode rejection ratio
VCM1 = 2 V, VCM2 = AVDD –2 V, VOUT = AVDD / 2
40
78
dB
PSRR
Power supply rejection ratio
AVDD1 = 7 V, AVDD2 = 10.1 V, VCM = 3 V, VOUT = 3 V
40
110
dB
TA = –40°C
18
30
TA = 25°C to 85°C
25
38
IPK
SR
High-side peak output current
MAX
Slew rate
Open-loop,
VPOS = AVDD / 2 ±1 V
294
–349
–200
mA
V/μs
GATE VOLTAGE SHAPING
VGH to VGHM ON resistance
rDS(ON)
VGHM to RE ON resistance
tPLH
Propagation delay
tPHL
VGH = 24 V, IGHM = 10 mA, FLK = 2.5 V
12
25
VGHM = 24 V, IGHM = 10 mA, FLK = 0 V
12
25
VGHM = 6 V, IGHM = 10 mA, FLK = 0 V
12
25
VGHM rising, 2.5 V, 50% thresholds, COUT = 150 pF, RE =
0Ω
72
175
VGHM falling, 2.5 V, 50% thresholds, COUT = 150 pF, RE =
0Ω
81
200
0.23
0.5
V
1
µA
Ω
ns
PANEL RESET / LCD BIAS READY (XAO)
VOL
Low output voltage
IXAO = 1 mA (sinking)
IOH
High output current
VXAO = 2.5 V
XAO threshold voltage
VDET
Tolerance
Hysteresis
XAO falling
XAO rising
2.2
3.9
–2.5%
2.5%
3%
6.3%
V
11%
TIMING
tDLY1
tDLY6
Boost converter 1 delay range
Tolerance
Gate voltage shaping; LCD biasready delay range
Tolerance
tSS1
tSS2
tUVP
Soft-start ramp time
Tolerance
Soft-start ramp time
Tolerance
VCORE, VIO1, VIO2
AVDD, VGH
Undervoltage protection timeout
0
70
–20%
30%
0
35
–20%
30%
0.5
4
–20%
30%
4
7.5
–20%
30%
40
50
ms
ms
ms
ms
65
ms
0.75
V
2
I C INTERFACE
ADDR
Configuration parameters slave
address
74h
Programmable VCOM slave address
4Fh
VIL
Low level input voltage
Rising edge, standard and fast mode
VIH
High level input voltage
Rising edge, standard and fast modes
1.75
V
VHYS
Hysteresis
Applicable to fast mode only
125
mV
VOL
Low level output voltage
Sinking 3 mA
CI
Input capacitance
fSCL
Clock frequency
tLOW
Clock low period
6
500
mV
10
pF
Standard mode
100
Fast mode
400
Standard mode
4.7
Fast mode
1.3
Electrical Specifications
kHz
µs
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ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
tHIGH
Clock high period
tBUF
TEST CONDITIONS
Standard mode
MIN
Fast mode
0.6
Bus free time between a STOP and a
START condition
Standard mode
4.7
Fast mode
1.3
thd:STA
Hold time for a repeated START
condition
Standard mode
tsu:STA
Set-up time for a repeated START
condition
Standard mode
tsu:DAT
Data set-up time
thd:DAT
Data hold time
tRCL1
Rise time of SCL after a repeated
START condition and after an ACK
bit
tRCL
Fast mode
tFDA
Set-up time for STOP condition
CB
Capacitive load on SDA and SCL
4
µs
0.6
4
µs
250
Fast mode
100
Standard mode
0.05
3.45
Fast mode
0.05
0.9
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
1000
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
300
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
300
Fast mode
20 +
0.1CB
300
Fall time of SDA
tsu:STO
µs
Standard mode
Rise time of SDA
Standard mode
Fast mode
UNIT
µs
0.6
Fall time of SCL
tRDA
MAX
Fast mode
Rise time of SCL
tFCL
TYP
4
ns
µs
ns
ns
ns
ns
ns
4
µs
0.6
Standard mode
400
Fast mode
400
pF
EEPROM
NWRITE
Number of write cycles
tWRITE
Write time
Data retention
1000
100
Storage temperature = 150°C
100
ms
1000 hrs
THERMAL SHUTDOWN
TSD (4)
(4)
Thermal shutdown threshold
120
150
180
°C
Once triggered, thermal shutdown will remain in the shutdown state until the device is powered down.
Terminal Description
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3 Terminal Description
3.1
Pin Assignment
NEG2
OUT2
AVDD
SW1
GND
GND
SW4
SW4
OUT1
AVDD
SW1
GND
EN
GND
GND
EN
NEG1
OUTD
AVDD
OUTH
WP
VGH
COMP
VGH
F2
OUTC
OUTG
OUTN
OUTK
SCL
VGHM
VGHM
SCL
OUTB
POS1
OUTF
OUTM
OUTJ
SDA
RE
RE
RSET
OUTA
OUTI
OUTE
OUTL
GND
FLK
FLK
GND
VIO1
VIN
XAO
RST
TCOMP
VCORE
VIO2
SW3
GND
VIN
SW2
GND
GND
VIN
SW2
XAO
SW3
A3
C7
AVDD
B6
B7
GND
VIO2
A6
A7
BOTTOM VIEW
TOP VIEW
3.2
RSET
VIO1
A5
D7
C6
B5
GND
A4
POS1
OUTA
RST
E7
D6
C5
B4
POS2
OUTB
OUTE
F7
E6
D5
C4
B3
VIN
A2
A1
OUTI
NEG1
OUTC
OUTF
G7
F6
E5
D4
C3
B2
B1
GND
OUTL
TCOMP
VCORE
OUTJ
G6
OUTD
OUTG
H7
GND
OUT1
F5
E4
D3
C2
C1
AVDD
OUTM
H6
G5
OUTH
OUTK
E3
D2
AVDD
F4
NEG2
OUT2
H5
G4
AVDD
OUTN
SDA
D1
SW1
F3
E2
E1
AVDD
H4
G3
WP
COMP
F1
POS2
GND
G2
G1
SW1
H3
H2
H1
GND
GND
GND
Pin Assignment
Table 3-1. PIN DESCRIPTIONS
PIN
8
I/O
DESCRIPTION
NAME
NO.
GND
A1
P
Ground
SW2
A2
O
Buck converter 1 (VCORE) switch pin
VIN
A3
P
Supply voltage
SW3
A4
O
Buck converter 2 (VIO1) switch pin
GND
A5
P
Ground
GND
A7
P
Ground
VIO2
A6
O
Linear regulator (VIO2) output and output sense
VCORE
B1
I
Buck converter 1 (VCORE) output sense
TCOMP
B2
I
Boost converter 2 (VGH) thermistor network connection
VIN
B3
P
Supply voltage
XAO
B4
O
Panel discharge
RST
B5
O
System reset
VIO1
B6
I
Buck converter 2 (VIO1) output sense. (Internally connected as supply voltage for LDO
regulator.)
AVDD
B7
I
Boost converter 1 (AVDD) output sense. (Internally connected as supply voltage for
programmable gamma correction.)
FLK
C1
I
Gate voltage shaping flicker clock
GND
C2
P
Ground
OUTL
C3
O
Gamma correction
Terminal Description
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Table 3-1. PIN DESCRIPTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
OUTI
C4
O
Gamma correction
OUTE
C5
O
Gamma correction
OUTA
C6
O
Gamma correction
RSET
C7
O
Reference current-setting resistor connection
RE
D1
O
Gate voltage shaping discharge resistor connection
SDA
D2
I/O
I2C serial data
OUTM
D3
O
Gamma correction
OUTJ
D4
O
Gamma correction
OUTF
D5
O
Gamma correction
OUTB
D6
O
Gamma correction
POS1
D7
I
VCOM 1 non-inverting input
VGHM
E1
O
Gate voltage shaping output
SCL
E2
I/O
I2C serial clock
OUTN
E3
O
Gamma correction
OUTK
E4
O
Gamma correction
OUTG
E5
O
Gamma correction
OUTC
E6
O
Gamma correction
POS2
E7
I
VCOM2 non-inverting input.
VGH
F1
I
Boost converter 2 (VGH) output sense. (Internally connected as supply voltage for the gate
voltage shaping.)
COMP
F2
O
Boost converter 1 (AVDD) compensation network connection
WP
F3
I
EEPROM write protect
AVDD
F4
I
VCOM1 and VCOM2 supply voltage
OUTH
F5
O
Gamma correction
OUTD
F6
O
Gamma correction
NEG1
F7
I
VCOM1 inverting input
GND
G1
P
Ground.
EN
G2
I
Boost converter 1 (AVDD) enable
GND
G3
P
Ground.
SW1
G4
O
Boost converter 1 (AVDD) switch pin
AVDD
G5
O
Boost converter 1 (AVDD) rectifier output
OUT1
G6
O
VCOM1 output
GND
G7
P
Ground.
SW4
H1
O
Boost converter 2 (VGH) switch pin
GND
H2
P
Ground
GND
H3
P
Ground
SW1
H4
O
Boost converter 1 (AVDD) switch pin
AVDD
H5
O
Boost converter 1 (AVDD) rectifier output
OUT2
H6
O
VCOM2 output
NEG2
H7
I
VCOM2 inverting input
Terminal Description
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4 Typical Characteristics
4.1
Table of Graphs
FUNCTIONAL BLOCK
PARAMETER
Boost Converter 1 (AVDD) Efficiency
VIN = 2.6 V to 6 V, AVDD = 8.4 V, IAVDD = 100 mA
Load Regulation
VIN = 3.3 V, 5 V, AVDD = 8.4 V, IAVDD = 1 mA to 500 mA
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V
Output Voltage Ripple
Switching Waveforms
Switching Frequency
Buck Converter 1 (VCORE) Efficiency
Figure 4-1
VIN = 5 V
Figure 4-2
Figure 4-3
AVDD = 8.4 V, IAVDD = 20 mA – 200 mA
AVDD = 8.4 V, RL = 82 Ω
Figure 4-4
RL = 82 Ω
Figure 4-5
RL = 33 Ω
Figure 4-6
VIN = 3.3 V
Figure 4-7
VIN = 5 V
Figure 4-8
VIN = 3.3 V
Figure 4-9
VIN = 5 V
Figure 4-10
RL = 820 Ω
Figure 4-11
RL = 82 Ω
Figure 4-12
VIN = 2.6 V to 6 V, AVDD = 7 V, 8.4 V, 10.1 V
RL = 82 Ω
Figure 4-13
VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500 mA
VIN = 3.4 V
Figure 4-14
VIN = 5 V
Figure 4-15
VIN = 3.3 V, AVDD = 8.4 V
VIN = 2.6 V to 6 V, VCORE = 1.1 V, ICORE = 300 mA
Figure 4-16
Load Regulation
VIN = 3.4 V, 5 V, VCORE= 1.1 V, ICORE = 1 mA to 500 mA
Figure 4-17
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VCORE= 1.1 V, Load = 3.9 Ω
Figure 4-18
Load Transient Response
VCORE = 1.1 V, ICORE = 50 mA - 200 mA
VIN = 3.3 V
Figure 4-19
VIN = 5 V
Figure 4-20
VIN = 3.3 V
Figure 4-21
VIN = 5 V
Figure 4-22
RL = 120 Ω
Figure 4-23
RL = 3.9 Ω
Figure 4-24
Switching Waveforms
VCORE = 1.1 V, RL = 3.9 Ω
VIN = 3.3 V, VCORE = 1.1 V
Switching Frequency
VIN = 2.6 V to 6 V, VCORE = 1.1 V
RL = 12 Ω
Figure 4-25
Efficiency
VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
VIN = 3.3 V
Figure 4-26
VIN = 5 V
Figure 4-27
Line Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
Figure 4-28
Load Regulation
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 500 mA
Figure 4-29
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 1.7 V, RL = 27 Ω
Load Transient Response
VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
Output Voltage Ripple
Switching Waveforms
10
VIN = 3.3 V
Line Regulation
Output Voltage Ripple
LDO Regulator (VIO2)
FIGURE
Line Regulation
Load Transient Response
Buck Converter 2 (VIO1)
TEST CONDITIONS
AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V, IAVDD = 1 mA to 500 mA
VIO1 = 1.7 V, RL = 27 Ω
VIN = 3.3 V, VIO1 = 1.7 V
Figure 4-30
VIN = 3.3 V
Figure 4-31
VIN = 5 V
Figure 4-32
VIN = 3.3 V
Figure 4-33
VIN = 5 V
Figure 4-34
RL = 270 Ω
Figure 4-35
RL = 27 Ω
Figure 4-35
RL = 27 Ω
Figure 4-35
Switching Frequency
VIN = 2.6 V to 6 V, VIO1 = 1.7 V
Load Regulation
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
Figure 4-38
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
Figure 4-39
Load Transient Response
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA - 100 mA
Figure 4-40
Output Voltage Ripple
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
Figure 4-41
Typical Characteristics
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FUNCTIONAL BLOCK
Boost Converter 2 (VGH)
SLVSC21 – OCTOBER 2013
PARAMETER
Figure 4-42
Line Regulation
VIN = 3.7 V, AVDD = 7 V to 10.1 V, VGH = 24 V, IGH = 10 mA
Figure 4-43
Load Regulation
VIN = 3.7 V, AVDD = 8.4 V, VGH = 24 V, IGH = 1 mA to 50 mA
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V (RL = 82
Ω), VGH = 24 V
RL = 4.8 kΩ
Figure 4-45
RL = 1.2 kΩ
Figure 4-46
VIN = 3.3V V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V
IGH = 5 mA - 10 mA
Figure 4-47
IGH = 10 mA - 30 mA
Figure 4-48
RL = 4.8 kΩ
Figure 4-49
RL = 1.2 kΩ
Figure 4-50
RL = 4.8 kΩ
Figure 4-51
RL = 1.2 kΩ
Figure 4-52
Output Voltage Ripple
Switching Waveforms
Power-Down Behavior
FIGURE
VIN = 3.7 V, AVDD = 8.4 V, VGH = 16 V, 24 V, 31 V
Load Transient Response
Power-Up Behavior
TEST CONDITIONS
Efficiency
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V
VIN = 3.3 V, AVDD = 8.4 V(RL = 82 Ω), VGH = 24 V
Figure 4-44
Switching Frequency
VIN = 3.3 V, AVDD = 7 V, 8.4 V, 10.1 V, VGH = 16 V to 31 V
VIN, VIO1, VIO2, VCORE
VIN = 3.3 V, tSS1 = 0.5 ms, VIO1 = 2.5 V, VIO2 = 1.8 V, VCORE =
1.1 V
RL = 3.9 Ω
Figure 4-53
Figure 4-54
EN, AVDD, VGH
VIN = 3.3 V, tSS2 = 4 ms, AVDD = 8.1 V (RL = 33 Ω), VGH = 24
V (RL = 1.2 kΩ)
tDLY1 = 0 ms
Figure 4-55
tDLY1 = 10 ms
Figure 4-56
XAO, AVDD, VGH, VGHM
VIN = 3.3 V, AVDD = 8.1 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ), GIP = 0
tDLY6 = 0 ms
Figure 4-57
tDLY6 = 10 ms
Figure 4-58
XAO, AVDD, VGH, VGHM
VIN = 3.3 V, AVDD = 8.1 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ), GIP = 1
tDLY6 = 0 ms
Figure 4-49
tDLY6 = 10 ms
Figure 4-60
AVDD, VGH, VCOM, VGAMA
VIN = 3.3 V, AVDD = 8.1 V, VGH = 24 V, VCOM = 4.05 V, VGAMA = 4.05 V
Figure 4-61
RST, VIO1, VIO2, VCORE
VDET = 2.5 V
RMODE = 0
Figure 4-62
RMODE = 1
Figure 4-63
VIN, XAO, AVDD, VGHM
GIP = 0
AVDD, VGH, VCOM, VGAMA
Figure 4-64
SMODE = 0
Figure 4-65
SMODE = 1
Figure 4-66
Gate Voltage Shaping
FLK, VGHM
VIN = 3.3 V, RE = 1 kΩ, CL = 10 nF, AVDD = 8.4 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ)
Figure 4-67
Op-Amp
Large-Signal Response
AVDD = 8.4 V, VPOS = 3.8 V ±0.5 V
Figure 4-68
Small-Signal Bandwidth
AVDD = 8.4 V, VPOS = 4 V + 65 mVPP, AV = +1, RF = 0 Ω
Figure 4-69
Gain Bandwidth
AVDD = 8.4 V, VPOS = 4 V + 65 mVPP, AV = +1, RF = 0 Ω
Figure 4-70
Peak Output Current
VIN = 3.3 V, AVDD = 8.4 V, RL = 2 kΩ to AVDD / 2, CL = 1 μF
Figure 4-71
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V, VCOM = 4 V, RL = ∞
Figure 4-72
Output Voltage Ripple and
Noise
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VCOM = 4 V, RL = ∞
Figure 4-73
Dynamic Response
AVDD = 8.4 V, RL = 909 k, CL = 55 pF
Programmable Gamma
Line Transient Response
Output Voltage Ripple and
Noise
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V (RL = 82
Ω)
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω)
GAMA = 0x0ff to
0x2ff
Figure 4-74
GAMA = 0x2ff to
0x0ff
Figure 4-75
GAMA = 0x0ff
Figure 4-76
GAMA = 0x1ff
Figure 4-77
GAMA = 0x2ff
Figure 4-78
GAMA = 0x1ff
Figure 4-79
Typical Characteristics
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Boost Converter 1 — Efficiency
VIN = 5 V, AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V
100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
Boost Converter 1 — Efficiency
VIN = 3.3 V, AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V
60
50
40
30
50
40
30
20
L=Toko 1269AS-H-4R7M
0
0
50
100
150
200
250
300
350
400
450
Iout - Output Current - mA
AVDD = 7.0 V
20
AVDD = 7.0 V
AVDD = 8.4 V
AVDD = 9.4 V
AVDD = 10.1 V
10
AVDD = 8.4 V
10
AVDD = 9.4 V
L=Toko 1269AS-H-4R7M
AVDD = 10.1 V
0
500
0
50
100
150
200
250
300
350
400
450
500
Iout - Output Current - mA
G401
G402
Figure 4-1.
spacer
Figure 4-2.
spacer
Boost Converter 1 — Line Regulation
VIN = 2.6 V to 6 V, AVDD = 8.4 V, IAVDD = 100 mA
Boost Converter 1 — Load Regulation
VIN = 3.3 V, 5 V, AVDD = 8.4 V, IAVDD = 1 mA to 500 mA
8.55
8.55
8.50
8.50
AVDD - Output Voltage - V
AVDD - Output Voltage - V
60
8.45
8.40
8.35
8.30
8.45
8.40
8.35
8.30
VIN = 3.3 V
L=Toko 1269AS-H-4R7M
L=Toko 1269AS-H-2R2M
8.25
3.1
3.6
4.1
4.6
5.1
5.6
VIN - Input Voltage - V
12
VIN = 5.0 V
8.25
2.6
0
50
100
150
200
250
300
350
400
450
IAVDD - Output Current - mA
G403
Figure 4-3.
spacer
Figure 4-4.
spacer
Boost Converter 1 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL = 82 Ω
Boost Converter 1 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL= 33 Ω
Figure 4-5.
Figure 4-6.
Typical Characteristics
500
G404
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Boost Converter 1 — Load Transient Response
VIN = 3.3 V, AVDD = 8.4 V, IAVDD = 20 mA - 200 mA
Boost Converter 1 — Load Transient Response
VIN = 5 V, AVDD = 8.4 V, IAVDD = 20 mA - 200 mA
Figure 4-7.
spacer
Figure 4-8.
spacer
Boost Converter 1 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.4 V, RL = 82 Ω
Boost Converter 1 — Output Voltage Ripple
VIN = 5 V, AVDD = 8.4 V, RL = 82 Ω
Figure 4-9.
spacer
Figure 4-10.
spacer
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V, RL = 820 Ω
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V, RL = 82 Ω
Figure 4-11.
spacer
Figure 4-12.
spacer
Typical Characteristics
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VIN
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Buck Converter 1 — Efficiency
VIN = 3.4 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500
mA
Boost Converter 1 — Switching Frequency
= 2.6 V to 6 V, AVDD = 7 V, 8.4 V, 10.1 V, RL = 82 Ω
100
90
80
1,300
70
Efficiency - %
fSW - Switching Frequency - kHz
1,500
1,100
900
700
60
50
40
30
500
1269AS-H-2R2M
L=Toko 1269AS-H-4R7M
3.0
3.5
20
AVDD=8.4V
10
4.0
4.5
5.0
5.5
VCORE = 1.0 V
VCORE = 1.1 V
VCORE = 1.2 V
L=Toko 1269AS-H-2R2M
AVDD=10.1V
300
2.5
AVDD=7.0V
VCORE = 1.3 V
0
6.0
VIN - Input Voltage - V
0
50
100
150
200
250
300
350
400
450
ICORE - Output Current - mA
G413
G416
Figure 4-13.
spacer
Figure 4-14.
spacer
Buck Converter 1 — Efficiency
VIN = 5 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500 mA
Buck Converter 1 — Line Regulation
VIN = 2.6 V to 6 V, VCORE = 1.1 V, ICORE = 300 mA
1.15
90
1.14
80
1.13
VCORE - Output Voltage - V
100
Efficiency - %
70
60
50
40
30
VCORE = 1.0 V
20
500
1.12
1.11
1.10
1.09
1.08
1.07
VCORE = 1.1 V
10
1.06
VCORE = 1.2 V
L=Toko 1269AS-H-2R2M
0
0
50
100
150
L=Toko 1269AS-H-4R7M
VCORE = 1.3 V
200
250
300
350
400
450
ICORE - Output Current - mA
1.05
500
2.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN - Input Voltage - V
G417
Figure 4-15.
spacer
Figure 4-16.
spacer
Buck Converter 1 — Load Regulation
VIN = 3.4 V, 5 V, VCORE = 1.1 V, ICORE = 0 mA to 500 mA
Buck Converter 1 — Line Transient Response
VIN = 3 V to 4.8 V, VCORE = 1.1 V, RL = 3.9 Ω
G416
1.15
VCORE - Output Voltage - V
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
VIN = 3.4 V
1.06
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
1.05
0
50
100
150
200
250
300
350
ICORE - Output Current - mA
400
450
500
G419
Figure 4-17.
spacer
14
Figure 4-18.
Typical Characteristics
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Buck Converter 1 — Load Transient Response
VIN = 3.3 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
Buck Converter 1 — Load Transient Response
VIN = 5 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
Figure 4-19.
Figure 4-20.
spacer
Buck Converter 1 — Output Voltage Ripple
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
Buck Converter 1 — Output Voltage Ripple
VIN = 5 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-21.
spacer
Figure 4-22.
spacer
Buck Converter 1 — Switching Waveforms
VIN = 3.3 V, VCORE = 1.1 V, RL = 120 Ω
Buck Converter 1 — Switching Waveforms
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-23.
spacer
Figure 4-24.
Typical Characteristics
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Buck Converter 1 — Switching Frequency
VCORE = 1.1 V, RL = 12 Ω
Buck Converter 2 — Efficiency
VIN = 3.3 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
100
90
1,500
80
1,300
70
Efficiency - %
fSW - Switching Frequency - kHz
1,700
1,100
900
60
50
40
30
700
20
500
VIO1 = 1.7 V
10
VIO1 = 1.8 V
L=Toko 1269AS-H-2R2M
L=Toko 1269AS-H-2R2M
300
VIO1 = 2.5 V
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
6.0
VIN - Input Voltage - V
50
100
150
200
250
300
350
400
450
IIO1 - Output Current - mA
G425
G428
Figure 4-25.
Figure 4-26.
spacer
Buck Converter 2 — Efficiency
VIN = 5 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
Buck Converter 2 — Line Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
1.80
90
1.78
80
1.76
VIO1 - Output Voltage - V
100
Efficiency - %
70
60
50
40
30
20
L=Toko 1269AS-H-2R2M
0
50
100
150
250
300
350
400
450
1.68
1.66
1.60
500
IIO1 - Output Current - mA
1.70
L=Toko 1269AS-H-2R2M
VIO1 = 2.5 V
200
1.72
1.62
VIO1 = 1.8 V
0
1.74
1.64
VIO1 = 1.7 V
10
500
2.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN - Input Voltage - V
G429
Figure 4-27.
spacer
Figure 4-28.
spacer
Buck Converter 2 — Load Regulation
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 500 mA
Buck Converter 2 — Line Transient Response
VIN = 3 V to 4.8 V, VIO1 = 1.7 V, RL = 27 Ω
G428
1.80
VIO1 - Output Voltage - V
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
VIN = 3.4 V
1.62
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
1.60
0
50
100
150
200
250
300
350
IIO1 - Output Current - mA
400
450
500
G431
Figure 4-29.
spacer
16
Figure 4-30.
Typical Characteristics
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Buck Converter 2 — Load Transient Response
VIN = 3.3 V, VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
Buck Converter 2 — Load Transient Response
VIN = 5 V, VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
Figure 4-31.
Figure 4-32.
spacer
Buck Converter 2 — Output Voltage Ripple
VIN = 3.3 V, VIO1 = 1.7 V, RL = 27 Ω
Buck Converter 2 — Output Voltage Ripple
VIN = 5 V, VIO1 = 1.7 V, RL = 27 Ω
Figure 4-33.
spacer
Figure 4-34.
spacer
Buck Converter 2 — Switching Waveforms
VIN = 3.3 V, VIO1 = 1.7 V, RL = 270 Ω
Buck Converter 2 — Switching Waveforms
VIN = 3.3 V, VIO1 = 1.7 V, RL = 27 Ω
Figure 4-35.
spacer
Figure 4-36.
Typical Characteristics
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Buck Converter 2 — Switching Frequency
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, RL = 27 Ω
LDO Regulator — Load Regulation
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
1.85
2,000
1,800
VIO2 - Output Voltage - V
fSW - Switching Frequency - kHz
1,900
1,700
1,600
1,500
1,400
1,300
1,200
1.83
1.81
1.79
1.77
1,100
L=Toko 1269AS-H-2R2M
1,000
1.75
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
6.0
VIN - Input Voltage - V
10
20
30
40
50
60
70
80
90
100
IIO2 - Output Current - mA
G437
G438
Figure 4-37.
Figure 4-38.
spacer
LDO Regulator — Line Transient Response
VIN = 3 V to 4.8 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
LDO Regulator — Load Transient Response
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA - 100 mA
Figure 4-39.
Figure 4-40.
LDO Regulator — Output Voltage Ripple
VIN =3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
Boost Converter 2 — Efficiency
(AVDD losses are excluded)
VIN = 3.7 V, AVDD = 8.4 V, VGH = 16 V, 24 V, 31 V
100
90
80
Efficiency - %
70
60
50
40
30
20
VGH = 16 V
VGH = 24 V
10
L=Murata LQH3NPN150NG0
VGH = 31 V
0
0
10
20
30
IGH - Output Current - mA
Figure 4-41.
18
40
50
G444
Figure 4-42.
Typical Characteristics
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Boost Converter 2 — Load Regulation
VIN = 3.7 V, AVDD = 8.4 V, VGH = 24 V, IGH = 1 mA to 50 mA
24.20
24.20
24.15
24.15
VGH - Output Voltage - V
VGH - Output Voltage - V
Boost Converter 2 — Line Regulation
VIN = 3.7 V, AVDD = 7 V to 10.1 V, VGH = 24 V, IGH = 10 mA
24.10
24.05
24.00
23.95
23.90
23.85
24.10
24.05
24.00
23.95
23.90
23.85
L=Murata LQH3NPN150NG0
L=Murata LQH3NPN150NG0
23.80
23.80
7
7.5
8
8.5
9
AVDD - Input Voltage - V
9.5
10
0
5
10
15
20
25
30
35
40
45
IGH - Output Current - mA
G443
50
G446
Figure 4-43.
spacer
Figure 4-44.
spacer
Boost Converter 2 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k
Boost Converter 2 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-45.
spacer
Figure 4-46.
Boost Converter 2 — Load Transient Response
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, IGH = 5 mA - 10
mA
Boost Converter 2 — Load Transient Response
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, IGH = 10 mA - 30
mA
Figure 4-47.
Figure 4-48.
Typical Characteristics
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Boost Converter 2 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k
Boost Converter 2 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-49.
Figure 4-50.
Boost Converter 2 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k
Boost Converter 2 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-51.
Figure 4-52.
Boost Converter 2 — Switching Frequency
AVDD = 7 V, 8.4 V, 10.1 V, VGH = 16 V to 31 V, RL = 4.8 kΩ
Power-Up Sequencing
VIN, VIO1, VIO2, VCORE
fSW - Switching Frequency - kHz
550
500
450
400
350
AVDD=7.0V
300
AVDD=8.4V
L=Murata LQH3NPN150NG0
AVDD=10.1V
250
16
18
20
22
24
26
VGH - Output Voltage - V
28
30
G453
Figure 4-53.
20
Figure 4-54.
Typical Characteristics
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Power-Up Sequencing
EN, AVDD, VGH (tDLY1 = 0 ms)
Power-Up Sequencing
EN, AVDD, VGH (tDLY1 = 10 ms)
Figure 4-55.
Figure 4-56.
Power-Up Sequencing — GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-Up Sequencing — GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-57.
Figure 4-58.
Power-Up Sequencing — GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-Up Sequencing — GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-59.
Figure 4-60.
Typical Characteristics
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Power-Up Sequencing
AVDD, VGH, VCOM, VGAMA
Power-Down Sequencing — RMODE = 0
VDET = 2.5 V, RST, VIO1, VIO2, VCORE
Figure 4-61.
Figure 4-62.
Power-Down Sequencing – RMODE = 1
VDET = 2.5 V, RST, VIO1, VIO2, VCORE
Power-Down Sequencing — GIP = 0
VIN, XAO, AVDD, VGHM
Figure 4-63.
Figure 4-64.
Power-Down Sequencing — SMODE = 0
AVDD, VGH, VCOM, VGAMA
Power-Down Sequencing — SMODE = 1
AVDD, VGH, VCOM, VGAMA
Figure 4-65.
Figure 4-66.
Typical Characteristics
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Gate Voltage Shaping — FLK, VGHM
VIN = 3.3 V, AVDD = 8.4 V (RL = 33 Ω), VGH = 24 V (RL = 1.2 kΩ), RE
= 1 kΩ, CL = 10 nF
VCOM Buffer — Large Signal Response
AVDD = 8.4 V, RL = 82 Ω, VPOS = 3.8 V + 0.5 Vpp
Figure 4-67.
Figure 4-68.
VCOM Buffer — Small-Signal Bandwidth
AVDD = 8.4 V, VPOS = 4 V + 65 mVpp
VCOM Buffer — Gain-Bandwidth Product
AVDD = 8.4 V, VPOS = 4 V + 65 mVpp
Figure 4-69.
Figure 4-70.
VCOM Buffer — Peak Output Current
VIN = 3.3 V, AVDD = 8.4 V, RL = 2k to AVDD / 2, CL = 1 μF
VCOM Buffer — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL = 82 Ω, VCOM = 4 V, RL = ∞
Figure 4-71.
Figure 4-72.
Typical Characteristics
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VCOM Buffer — Output Voltage Ripple and Noise
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VCOM = 4 V, RL = ∞
Programmable GAMMA — Dynamic Response
GAMA = 0x0ff to 0x2ff, RL = 909 kΩ, CL = 55 pF
Figure 4-73.
Figure 4-74.
GAMMA Voltage — Dynamic Response
GAMA = 0x2ff to 0x0ff, RL= 909 kΩ, CL= 55 pF
Programmable GAMMA — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x0ff
Figure 4-75.
Figure 4-76.
Programmable GAMMA — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x1ff
Programmable GAMMA — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x2ff
Figure 4-77.
Figure 4-78.
Typical Characteristics
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Programmable GAMMA — Output Voltage Ripple and Noise
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x1ff
Figure 4-79.
Typical Characteristics
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5 Detailed Description
Figure 5-1 shows an internal block diagram of the TPS65642A device.
EN
Internal
VUVLO
+
–
VDET
XAO
Sequencing
RST
+
–
SW2
VIN
Buck 1
VCORE
SW3
Buck 2
VIO1
LDO
SW1
Boost 1
COMP
VIO2
AVDD
TCOMP
Temperature
Compensation
SW4
Boost 2
VGH
Gate Voltage
Shaping
FLK
VGHM
RE
OUTA
Programmable
Gamma
AVDD
OUTN
RSET
Programmable
VCOM
AVDD
POS1
+
NEG1
–
POS2
+
NEG2
–
OUT1
OUT2
SCL
2
SDA
IC
Interface
Internal
WP
Figure 5-1. Internal Block Diagram
26
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5.1
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BOOST CONVERTER 1 (AVDD)
Boost converter 1 is synchronous and uses a virtual current mode topology that:
• Achieves high efficiencies
• Allows the converter to work in continuous-conduction mode under all operating conditions, which
simplifies compensation
• Provides a better drive signal for the negative charge pump connected to the switch node (because the
converter always runs in continuous-conduction mode, even at low output currents)
• Provides true input-output isolation when the boost converter is disabled
VIN
AVDD
VIN
SW1
Q1B
AVDD
AVDD
FREQ
VREF
AVDD
PWM
Control
+
–
SMODE
&
Q1A
Q2
UVLO
GND
COMP
Figure 5-2. Boost Converter 1 Internal Block Diagram
5.1.1
Switching Frequency (Boost Converter 1)
The nominal switching frequency of boost converter 1 can be programmed to 750 kHz or 1200 kHz using
the FREQ bit in the MISC register. The factory default value is 1200 kHz.
5.1.2
Compensation (Boost Converter 1)
Boost converter 1 uses an external compensation network connected to the COMP pin to stabilize its
feedback loop. A simple series R-C network connected between the COMP pin and ground is sufficient to
achieve good performance, in effect, stable and with good transient response. Good starting values, which
will work for most applications, are 100 kΩ and 1 nF for 1200 MHz AVDD switching frequency and 56 kΩ
and 1.5 nF for 750 kHz AVDD switching frequency.
In some applications (for example, those using electrolytic output capacitors), it may be necessary to
include a second compensation capacitor between the COMP pin and ground. This has the effect of
adding an additional pole in the frequency response of the feedback loop, which cancels the zero
introduced by the ESR of the output capacitor.
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The COMP pin is directly connected to the input current comparator of the converter, which means that
any noise present on this pin can directly affect converter operation. In practical applications the most
likely source of noise is the switch pin on the converter, and for proper operation it is essential that the
stray capacitance between the SW1 and the COMP pins is minimized. This can be ensured using good
PCB layout practices, namely:
•
•
•
Locating the compensation components close to the COMP pin
Removing the GND plane from underneath the SW1 PCB tracks (to prevent this high dV/dt signal from
inducing currents locally in the GND plane)
Connecting the ground side of the compensation components to a noise-free GND location, in effect,
away from noisy power ground signals
NOTE
For the most robust operation TI recommends to ensure that the parasitic capacitance
between the SW1 and COMP is below 0.1 pF.
5.1.3
Power Up (Boost Converter 1)
Boost converter 1 starts tDLY1 milliseconds after EN or RST goes high, whichever occurs later. Delay time
tDLY1 can be programmed from 0 ms to 70 ms using the DLY1 register. Once asserted, the EN signal must
remain high to ensure normal device operation. Once disabled (EN = 0), boost converter 1 remains
disabled until the device is powered down (even if EN is re-asserted).
To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS2 milliseconds.
Start-up time tSS2 can be programmed from 4 ms to 7.5 ms using the SS2 register. Longer soft-start times
generate lower inrush currents.
The same ramp rate is also used for boost converter 2 – changing the SS2 register affects both boost
converters.
The soft-start function is not implemented if the output voltage of boost converter 1 is re-programmed
during operation. During normal operation (when AVDD remains constant) the non-implementation of softstart is not a problem, however, it may cause problems during production if AVDD is changed while the
converter is enabled. Problems can occur under such conditions because, without a soft-start, the
converter draws a high inrush current when the output voltage of the converter is changed. If the converter
is supplied from a high-impedance source, this inrush current can, under certain circumstances, pull VIN
below the UVLO threshold, disabling the IC and interrupting the writing of the configuration parameters.
Use one or more of the following recommendations to ensure trouble-free configuration during production:
• Program the configuration parameters before the IC is soldered to the PCB
• Supply the PCB with a voltage high enough to ensure that the voltage on the VIN pin remains above
the UVLO threshold when the value of AVDD is changed
• Ensure that the supply impedance is low enough to ensure that the voltage on the VIN pin remains
above the UVLO threshold when the value of AVDD is changed
• Disable boost converter 1 while the value of AVDD is changed
5.1.4
Power Down (Boost Converter 1)
Boost converter 1 is disabled when EN = 0 or VIN VUVLO (the same time buck converter 2 and LDO regulator
starts).
To minimize inrush current during start-up, buck converter 1 ramps VCORE from zero to the final value in
tSS1 milliseconds. Soft-start time tSS1 can be programmed from 0.5 ms to 4 ms using the SS1 register.
The same ramp rate is used for buck converter 2 and the linear regulator. Changing SS1 affects all three
regulators.
5.2.3
Power Down (Buck Converter 1)
Buck converter 1 is disabled when VIN< VUVLO. The output of buck converter 1 is not actively discharged.
5.3
BUCK CONVERTER 2 (VIO1)
Buck converter 2 is a low-power synchronous-buck converter that in typical applications generates the I/O
supply voltage for the timing controller and source drivers. Buck converter 2 is essentially the same as
buck converter 1: the output voltage VIO1 can be programmed by the user, but the output is actively
discharged during power-down.
VIN
VIN
VIO1
UVLO
Q2
Q1A
PWM
Control
VREF
SW3
VIO1
+
–
VIO1
Q1B
GND
Figure 5-4. Buck Converter 2 Internal Block Diagram
5.3.1
Output Voltage (Buck Converter 2)
The output voltage of buck converter 2 can be programmed to 1.7 V, 1.8 V, or 2.5 V using the VIO
register. The factory default setting is 1.7 V. When VIO1 = 1.7 V or 1.8 V, the LDO regulator is disabled.
5.3.2
Power-Up (Buck Converter 2)
Buck converter 2 starts as soon as VIN > VUVLO (the same time buck converter 1 and LDO regulator
starts), and implements the same voltage ramping as buck converter 1.
5.3.3
Power-Down (Buck Converter 2)
Buck converter 2 is disabled and actively discharges its output when VIN < VUVLO.
30
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5.4
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LDO REGULATOR (VIO2)
In applications in which the timing controller and source drivers use different I/O voltages, the low-dropout
(LDO) regulator can be used to generate the lower I/O supply voltage VIO2. The LDO regulator is supplied
from the VIO1 pin, which is the output of buck converter 2.
VIO1
VIO2
+
–
DAC
VIO2
Figure 5-5. Linear Regulator Block Diagram
5.4.1
Output Voltage (LDO Regulator)
When VIO1 = 2.5 V, the output voltage of the LDO regulator can be programmed to 1.7 V or 1.8 V using
the VIO register. When VIO1= 1.7 V or 1.8 V, the LDO regulator is disabled (factory default setting). Once
the device is powered up, the EN signal must remain high, to ensure reliable LDO programming.
5.4.2
Power-Up (LDO Regulator)
At power up, the LDO regulator starts as soon as VIN > VUVLO (the same time buck converter 1 and buck
converter 2 starts). The LDO regulator ramps the output linearly from zero to VIO2 in tSS1 milliseconds.
Soft-start time tSS1 can be programmed from 0.5 ms to 4 ms using the SS1 register.
The same ramp rate is used for both buck converters and the LDO regulator. Changing the SS1 register
affects all three regulators.
When the LDO is turned on or turned off during normal device operation (that is: programming VIO1 from
1.7 V to 2.5 V or vice versa), the ramp or discharge characteristic is defined by the load connected to the
LDO.
5.4.3
Power-Down (LDO Regulator)
The LDO regulator is supplied from the VIO1 pin, which is actively discharged during power-down. The
output of the LDO regulator therefore discharges through the body diode of transistor Q1 as long as VIO2
is high enough to forward bias the body diode. Thereafter, VIO2 continues to discharge through the load
connected to it.
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BOOST CONVERTER 2 (VGH)
Boost converter 2 is non-synchronous, and uses a constant off-time topology. The switching frequency of
the converter is not constant, but automatically adjusts for best performance according to VIN and VGH.
Boost converter 2 uses peak current control and is designed to operate permanently in discontinuousconduction mode (DCM), thereby allowing the internal compensation circuit to achieve stable operation
over a wide range of output voltages and currents, such as when temperature compensation is used.
Figure 5-6 shows a simplified block diagram of boost converter 2.
AVDD
VGH
AVDD
VGH
SW4
PWM
Control
Q1
–
27:1
+
Temperature
Compensation
VGHCOLD
VGHHOT
GND
TCOMP
RT1
RNTC
RT2
Figure 5-6. Boost Converter 2 Block Diagram
Boost converter 2 can be temperature compensated, allowing the output voltage to transition from a
higher voltage at low temperatures VGH(COLD) to a lower voltage at high temperatures VGH(HOT) (see
Figure 5-7 and Figure 5-8). The values of VGH(HOT) and VGH(COLD) are programmed using the VGHHOT and
VGHCOLD registers. The values of THOT and TCOLD are programmed by selecting the appropriate resistor
values for the thermistor network connected to the TCOMP pin.
VGH
VGH(COLD)
VGH(HOT)
TCOLD
THOT
Temperature
Figure 5-7. Boost Converter 2 Temperature Compensation Characteristic
32
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1.429V
TCOMP
RT1
+
DAC1
A1
Q1
−
ISET
0.893V
1.107V
RNTC
RT2
R1
R2
+
DAC2
A2
−
PWM
Controller
0.571V
VGH
R4
R3
R2 = 2∙R1
R4 = 27∙R3
Figure 5-8. Boost Converter 2 Temperature Compensation Block Diagram
With proper selection of the external components RT1, RT2 and RNTC, temperatures THOT and TCOLD can be
configured to suit the characteristics of each display. A Microsoft Excel® spreadsheet allowing easy
calculation of component values is available from Texas Instruments free of charge.
5.5.1
Power-Up (Boost Converter 2)
When AVDD is finished ramping up, boost converter 2 enables. To minimize inrush current during start-up,
boost converter 2 ramps VGH linearly to the programmed value in tSS2 seconds. Soft-start time tSS2 can be
programmed from 4 ms to 7.5 ms using the SS2 register. The same ramp rate is also used for boost
converter 1. Changing SS2 affects both boost converters.
5.5.2
Power-Down (Boost Converter 2)
Boost converter 2 is disabled when EN = 0 or VIN< VUVLO. The output of the converter is not actively
discharged when the converter is disabled. Once disabled (EN = 0), boost converter 2 remains disabled
until the device is powered down (even if EN is re-asserted).
5.5.3
Setting the Output Voltage (Boost Converter 2)
The output voltage of boost converter 2 at cold temperatures can be programmed from 25 V to 40 V (1)
using the VGHCOLD register. The output voltage of boost converter 2 at hot temperatures can be
programmed from 16 V to 31 V using the VGHHOT register.
In applications that do not require temperature compensation, the TCOMP pin must be tied to ground and
the VGHHOT register must set the voltage of VGH.
See Figure 5-8 and note that between VGHHOT and VGHCOLD, the output voltage of boost converter 2 is
given by Equation 1.
VGH = 28 ´ (VDAC2 + 3 ´ ( VTCOMP - VDAC2 ))
(1)
Equation 1 calculates the voltage required on the TCOMP pin at temperatures THOT and TCOLD.
V
VTCOMPHOT = GHHOT
28
2 ´ VGHHOT + VGHCOLD
VTCOMPCOLD =
84
(1)
(2)
(3)
Output voltages greater than 36 V require an external cascode transistor.
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Equation 4 calculates the appropriate value for RT2
2
R T2 =
- b ± b - 4ac
2a
where
•
V
- VTCOMPHOT
a = RNTCCOLD - RNTCHOT - TCOMPCOLD
ISET
•
æV
- VTCOMPHOT ö
b = (RNTCCOLD + RNTCHOT ) ´ ç TCOMPCOLD
÷
I
è
ø
SET
•
•
•
æV
- VTCOMPHOT ö
c = (R NTCCOLD ´ RNTCHOT ) ´ ç TCOMPCOLD
÷
ISET
è
ø
RNTCCOLD is the resistance of the thermistor at temperature TCOLD
RNTCHOT is the resistance of the thermistor at temperature THOT
Once the value of RT2 has been calculated, use Equation 5 to calculate the appropriate value of RT1.
æV
ö æR
´ RT2 ö
RRT1 = ´ ç TCOMPCOLD ÷ - ç NTCCOLD
÷
ISET
è
ø è R NTCCOLD + R T2 ø
5.5.4
(4)
(5)
Protection (AVDD, VCORE, VIO1, VIO2, VGH)
Each voltage regulator is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if a regulator output falls below 70% of the programmed voltage for longer than 50
ms, in which case the IC is disabled. To recover normal operation following an undervoltage condition, the
cause of the error condition must be removed and the supply voltage, VIN, must be cycled. A short-circuit
condition is detected if a regulator output falls below 30% of its programmed voltage, in which case the IC
is disabled immediately. To recover normal operation following a short-circuit condition, the cause of the
error must be removed and the supply voltage,VIN, must be cycled.
5.6
RESET GENERATOR
The RST pin generates an active-low reset signal for the timing controller. During power up, the reset
timer starts when VCORE has finished ramping. The reset pulse duration tRESET can be programmed from 2
ms to 16 ms using the RESET register. The RST signal is latched when it goes high and is not taken low
again until the device is powered down (even if VCORE temporarily falls out of regulation). The active
power-down threshold (VUVLO or VDET) can be selected using the RMODE bit in the CONFIG register.
The RST output is an open-drain type that requires an external pullup resistor. Pullup-resistor values in
the range 10 kΩ to 100 kΩ are recommended for most applications.
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GATE VOLTAGE SHAPING
The gate-voltage shaping function reduces image sticking in LCD panels by modulating the gate ON
voltage (VGH) of the LCD panel. Figure 5-9 shows a block diagram of the gate voltage shaping function
and Figure 5-10 shows the typical waveforms during operation.
VGH
VGH
Q1
FLK
VGHM
Control
Logic
FLK
VGHM
Q2
RE
RE
Figure 5-9. Gate-Voltage Shaping Block Diagram
VPG4
VIO2
FLK
Don’t Care
tDLY6
VGHM
VGH
Figure 5-10. Gate-Voltage Shaping Waveforms
Gate-voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2 is off, and VGHM is
equal to VGH. When FLK is low, Q1 is turned off, Q2 is turned on, and the LCD-panel load connected to
the VGHM pin discharges through the external resistor connected to the RE pin. This resistor is typically
connected to GND or AVDD.
During power-up Q2 is held permanently on and Q1 permanently off, regardless of the state of the FLK
signal, until tDLY6 milliseconds after boost converter 2 (VGH) has finished ramping. The value of tDLY6 can
be programmed from 0 ms to 35 ms using the DLY6 register.
During power-down Q1 is held permanently on and Q2 permanently off, regardless of the state of the FLK
signal.
Non-GIP or Non-ASG panels that do not use the gate-voltage shaping function must leave the RE pin
floating and connect the FLK pin to GND.
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PANEL RESET / LCD BIAS READY (XAO)
The TPS65642A device provides an output signal through the XAO pin that is used to reset a level-shifter
or gate-driver IC during power up and power down. The GIP bit in the CONFIG register defines whether
the XAO pin works in GIP mode or non-GIP mode.
The primary purpose of the XAO signal in non-GIP applications is to drive the outputs of the display-panel
gate-driver IC high during power down by generating an active-low signal. When the GIP = 0, the XAO pin
is pulled low whenever VIN < VDET. The VDET threshold voltage can be configured using the VDET register.
When the GIP = 1, the XAO output is used to delay the start of level-shifter activity during power up. The
delay time tDLY6 starts when VGH is done ramping up, and can be configured using the DLY6 register.
The XAO output is an open-drain type and requires an external pull up, typically in the range 10 kΩ to 100
kΩ.
5.9
PROGRAMMABLE VCOM CALIBRATOR
The programmable VCOM calibrator uses a digital-to-analog converter (DAC) to generate an offset current
IDAC for an external resistor divider connected to AVDD (see Figure 5-11 and Figure 5-12). Higher values of
the 7-bit digital word N written to the DAC generate higher IDAC sink currents, and therefore lower VCOM
voltages.
Figure 5-11 shows the recommended circuit for the most commonly used application, when the LCD panel
requires only one VCOM supply voltage. The second op-amp is shown wired as a unity-gain buffer with an
input tied to GND (the recommended configuration if a second op-amp is not used), however, using a
second op-amp for other purposes, such as generating a half-AVDD supply rail, is acceptable.
AVDD
R3
IDAC
POS1
POS1
VCOM
DAC
+
OUT1
VCOM1
NEG1
–
R5
ISET
SMODE
&
VIN < VUVLO
VREF
VFB1
+
POS2
–
+
NEG2
–
OUT2
VCOM2
RSET
RSET
Figure 5-11. Single-Programmable VCOM Supply
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The external resistor RSET generates a reference current ISET for the DAC. Since this reference current is
also used by the temperature compensation function of boost converter 2, care must be taken to ensure
that a suitable value is chosen. For most applications, a value of 24.9 kΩ is recommended, which
generates a reference current given by Equation 6.
V
ISET = REF
RSET
ISET =
1.25 V
24.9 kW
= 50.2 m A
(6)
The output current IDAC sunk by the DAC is given by Equation 7.
(N + 1)´ ISET
IDAC =
128
where
•
N is the 7-bit word written to the DAC, and ranges from 0 to 127
(7)
Equation 8 and Equation 9 can calculate appropriate values for R3 and R5.
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ VCOM(MAX) + DVCOM
(
R5 =
)
(8)
128 ´ D VCOM ´ R3
(127 ´ ISET ´ R3 ) - (128 ´ DVCOM )
(9)
Figure 5-12 shows the recommended connection for the case when two VCOM supplies VCOM1 and VCOM2
are to be generated.
AVDD
R3
IDAC
POS1
POS1
VCOM
DAC
+
OUT1
VCOM1
NEG1
–
ISET
SMODE
VIN < VUVLO
VREF
&
VFB1
R4
+
POS2
–
+
NEG2
–
OUT2
VCOM2
R5
RSET
RSET
VFB2
Figure 5-12. Dual-Programmable VCOM Supplies
In Figure 5-12, the voltage VCOM2 generated by the second op-amp is slightly lower than VCOM1. If two
identical VCOM supplies are required, these can be generated by setting R4 = 0.
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Equation 10 through Equation 12 calculate the correct values for R3 through R5 for the case when two
(slightly different) VCOM voltages are required.
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ VCOM1(MA X) + DVCOM
(10)
(
æ
R4 = ç
ç
è
)
ö
VCOM2(MAX) ö æ
128 ´ DVCOM ´ R3
÷´ ç
÷
VCOM1(MAX) ÷ø çè (127 ´ ISET ´ R3 ) - (128 ´ DVCOM ) ÷ø
(11)
æ VCOM1(MAX) - VCOM2(MAX) ö æ
ö
128 ´ DVCOM ´ R3
÷ ´ç
R5 = ç
÷÷
ç
÷
ç
VCOM1(MAX)
è
ø è (127 ´ ISET ´ R3 ) - (128 ´ DVCOM ) ø
(12)
A Microsoft Excel spreadsheet is available free of charge that calculates the values of R3, R4 and R5 —
contact a local TI sales representative for a copy.
5.9.1
Operational Amplifier Performance
Like most operation amplifiers (op amps), the VCOM op amps are not designed to drive purely capacitive
loads, so TI does not recommend to connect a capacitor directly to the outputs of the op amps in an
attempt to increase performance; however, the amplifiers are capable of delivering high peak currents that
make such capacitors unnecessary.
High-speed op amps such as those in the TPS65642A device require care when using them. The most
common problem is when parasitic capacitance at the inverting input creates a pole with the feedback
resistor, reducing amplifier stability. Two things can minimize the likelihood of this happening which work
by shifting the pole (which can never be completely eliminated) to a frequency outside the bandwidth of
the op amp, where it has no effect.
1. Reduce the value of the feedback resistor. In applications where no feedback from the panel is used,
the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be
used, a small capacitor (10 pF – 100 pF) across the feedback resistor will minimize ringing.
2. Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB
traces between the feedback resistor and the inverting input, and by removing ground planes and other
copper areas above and below this PCB trace.
5.9.2
Power Up (Programmable VCOM)
The programmable VCOM is enabled when AVDD > ≈ 3 V.
5.9.3
Power Down (Programmable VCOM)
The programmable VCOM supports two kinds of power-down behavior, and the SMODE bit in the CONFIG
register determines which behavior is active (see Figure 5-41 and Figure 5-42).
If SMODE = 0, the active discharge transistor Q1 is permanently disabled; during power-down, VCOM
tracks AVDD until VCOM is too low to support operation. If SMODE = 1, Q1 turns on when VIN < VUVLO,
actively pulling VCOM low.
5.10 PROGRAMMABLE GAMMA-VOLTAGE GENERATOR
The gamma-voltage correction supplies 14 reference voltages that can be used by the system source
driver IC to match the LCD-panel luminance characteristics more closely to the response of the human
eye.
The gamma-correction voltages can be programmed individually using the I2C interface. During power up,
the default gamma voltage for each channel is loaded from EEPROM into the corresponding DAC.
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During operation, the output voltages of the DAC can be changed by programming new values via the I2C
interface. Values programmed to the DACs but not transferred to EEPROM are lost when power is
removed from the device. The next time the device is powered up, the DACs are programmed with
whatever values are stored in the EEPROM. The current DAC settings can be transferred to EEPROM
(thereby becoming the new default values used during power-up) at any time by sending the appropriate
command to the Control Register through the I2C interface.
AVDD
AVDD
OUTA
GAMA
DAC
GAMN
DAC
OUTN
Figure 5-13. Gamma Correction Block Diagram
The output stages of the gamma correction block are capable of extending close to the supply rails (AVDD
and ground); however, they can only achieve this rail-to-rail performance with the specified accuracy if the
outputs are lightly loaded. The gamma reference outputs are only intended to drive high impedance loads
such as those presented by a gamma buffer or a high impedance source driver input.
The output voltage VGAM of each channel is given by:
VGAM =
where
•
N
× AVDD
1024
N is the 10-bit digital word programmed to the gamma register and ranges from 0 to 1023
(13)
Any non-used output can be left open and, to save power, must be programmed to the maximum voltage
(approximately 180-µA saving per output).
5.11 CONFIGURATION
The TPS65642A device divides the configuration parameters into two categories:
1. VCOM
2. all other configuration parameters
In typical applications, all configuration parameters except VCOM are programmed by the subcontractor
during PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.
5.11.1 RAM, EEPROM, and Write Protect
Configuration parameters are changed by writing the desired values to the appropriate RAM register(s).
The RAM registers are volatile and their contents are lost when power is removed from the device. By
writing to the Control Register, storing the active configuration in non-volatile EEPROM is possible; during
power up, the contents of the EEPROM are copied into the RAM registers and used to configure the
device.
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An active-high Write Protect (WP) pin prevents the configuration parameters from being changed by
accident. This pin is internally pulled high and must be actively pulled low to access to the EEPROM or
RAM registers. Note that the WP pin disables all I2C traffic to and from the TPS65642A device, and must
also be pulled low during read operations. This is to ensure that noise present on the I2C lines does not
erroneously overwrite the active configuration stored in RAM (which would not be protected by a simple
EEPROM write-protect scheme).
5.11.2 Configuration Parameters (Excluding VCOM)
Table 5-1 shows the memory map of the configuration parameters.
Table 5-1. Configuration Memory Map
REGISTER
ADDRESS
REGISTER NAME
FACTORY
DEFAULT
00h
CONFIG
00h
Sets miscellaneous configuration bits
01h
AVDD
0Eh
Sets the output voltage of boost converter 1
02h
VGHHOT
00h
Sets the output voltage of boost converter 2 at high temperatures
03h
VGHCOLD
00h
Sets the output voltage of boost converter 2 at low temperatures
04h
VIO
00h
Sets the output voltage of buck converter 2 and the LDO regulator
05h
MISC
05h
Sets the output voltage of buck converter 1 (VCORE) and the switching
frequency of boost converter 1 (AVDD)
06h
SS1
03h
Sets the soft-start time for buck converters 1 and 2 and the linear
regulator
07h
SS2
00h
Sets the soft-start time for boost converters 1 and 2
08h
RESET
01h
Sets the reset pulse duration
09h
DLY1
02h
Sets the boost converter 1 start-up delay
0Ah
DLY6
04h
Sets the gate voltage shaping and LCD ready start-up delay
0Bh
VDET
00h
Sets the threshold of the /RST and /XAO signals
02h
Contains the 2 MSBs of the 10-bit gamma voltage A
00h
Contains the 8 LSBs of the 10-bit gamma voltage A
02h
Contains the 2 MSBs of the 10-bit gamma voltage B
00h
Contains the 8 LSBs of the 10-bit gamma voltage B
02h
Contains the 2 MSBs of the 10-bit gamma voltage C
00h
Contains the 8 LSBs of the 10-bit gamma voltage C
02h
Contains the 2 MSBs of the 10-bit gamma voltage D
00h
Contains the 8 LSBs of the 10-bit gamma voltage D
02h
Contains the 2 MSBs of the 10-bit gamma voltage E
00h
Contains the 8 LSBs of the 10-bit gamma voltage E
02h
Contains the 2 MSBs of the 10-bit gamma voltage F
00h
Contains the 8 LSBs of the 10-bit gamma voltage F
02h
Contains the 2 MSBs of the 10-bit gamma voltage G
00h
Contains the 8 LSBs of the 10-bit gamma voltage G
02h
Contains the 2 MSBs of the 10-bit gamma voltage H
00h
Contains the 8 LSBs of the 10-bit gamma voltage H
02h
Contains the 2 MSBs of the 10-bit gamma voltage I
00h
Contains the 8 LSBs of the 10-bit gamma voltage I
02h
Contains the 2 MSBs of the 10-bit gamma voltage J
00h
Contains the 8 LSBs of the 10-bit gamma voltage J
02h
Contains the 2 MSBs of the 10-bit gamma voltage K
00h
Contains the 8 LSBs of the 10-bit gamma voltage K
02h
Contains the 2 MSBs of the 10-bit gamma voltage L
00h
Contains the 8 LSBs of the 10-bit gamma voltage L
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
40
DESCRIPTION
GAMMA-A
GAMMA-B
GAMMA-C
GAMMA-D
GAMMA-E
GAMMA-F
GAMMA-G
GAMMA-H
GAMMA-I
GAMMA-J
GAMMA-K
GAMMA-L
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Table 5-1. Configuration Memory Map (continued)
REGISTER
ADDRESS
REGISTER NAME
24h
FACTORY
DEFAULT
GAMMA-M
25h
26h
GAMMA-N
27h
FFh
Control
DESCRIPTION
02h
Contains the 2 MSBs of the 10-bit gamma voltage M
00h
Contains the 8 LSBs of the 10-bit gamma voltage M
02h
Contains the 2 MSBs of the 10-bit gamma voltage N
00h
Contains the 8 LSBs of the 10-bit gamma voltage N
00h
Controls whether read and write operations access RAM or EEPROM
registers
5.11.3 CONFIG (00h)
Figure 5-14. CONFIG Register Bit Allocation
7
6
5
4
3
Not Implemented
2
1
0
RMODE
SMODE
GIP
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-2. CONFIG Register Field Descriptions
Bit
Field
Value
7–3
Not implemented.
N/A
2
RMODE
1
0
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
Configures the RST power-down threshold voltage.
0
VUVLO threshold used.
1
VDET Threshold used.
SMODE
Configures the power-down behavior of AVDD and VCOM.
0
AVDD is actively discharged (but not VCOM).
1
VCOM is actively discharged (but not AVDD).
GIP
This bit configures the device for use with either GIP or non-GIP LCD panels.
0
The device operates in non-GIP mode, and XAO functions as a panel reset during powerdown.
1
The device operates in GIP mode, and the XAO functions as an enable for the panel level shifter
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5.11.4 AVDD (01h)
Figure 5-15. AVDD Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
R/W-1
R/W-0
AVDD
R/W-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-3. AVDD Register Field Descriptions
42
Bit
Field
Value
7–4
Not Implemented
N/A
4–0
AVDD
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure boost converter 1's output voltage (AVDD).
00h
7.0 V
01h
7.1 V
02h
7.2 V
03h
7.3 V
04h
7.4 V
05h
7.5 V
06h
7.6 V
07h
7.7 V
08h
7.8 V
09h
7.9 V
0Ah
8.0 V
0Bh
8.1 V
0Ch
8.2 V
0Dh
8.3 V
0Eh
8.4 V
0Fh
8.5 V
10h
8.6 V
11h
8.7 V
12h
8.8 V
13h
8.9 V
14h
9.0 V
15h
9.1 V
16h
9.2 V
17h
9.3 V
18h
9.4 V
19h
9.5 V
1Ah
9.6 V
1Bh
9.7 V
1Ch
9.8 V
1Dh
9.9 V
1Eh
10.0 V
1Fh
10.1 V
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5.11.5 VGHHOT (02h)
Figure 5-16. VGHHOT Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
R/W-0
R/W-0
VGHHOT
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-4. VGHHOT Register Field Descriptions
Bit
Field
Value
7–4
Not Implemented
N/A
3–0
VGHHOT
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure boost converter 2's output voltage (VGH) of at high temperatures.
0h
16 V
1h
17 V
2h
18 V
3h
19 V
4h
20 V
5h
21 V
6h
22 V
7h
23 V
8h
24 V
9h
25 V
Ah
26 V
Bh
27 V
Ch
28 V
Dh
29 V
Eh
30 V
Fh
31 V
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5.11.6 VGHCOLD (03h)
Figure 5-17. VGHCOLD Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
R/W-0
R/W-0
VGHCOLD
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-5. VGHCOLD Register Field Descriptions
44
Bit
Field
Value
7–4
Not Implemented
N/A
3–0
VGHCOLD
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure boost converter 2's output voltage (VGH) at low temperatures.
0h
25 V
1h
26 V
2h
27 V
3h
28 V
4h
29 V
5h
30 V
6h
31 V
7h
32 V
8h
33 V
9h
34 V
Ah
35 V
Bh
36 V
Ch
37 V
Dh
38 V
Eh
39 V
Fh
40 V
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5.11.7 VIO (04h)
Figure 5-18. VIO Register Bit Allocation
7
6
5
4
3
2
1
Not Implemented
0
VIO
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-6. VIO Register Field Descriptions
Bit
Field
Value
7–2
Not Implemented
N/A
1–0
VIO
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the output voltage of buck converter 2 (VIO1) and the LDO regulator (VIO2).
Once the device is powered up, the EN signal must remain high, to ensure reliable LDO
programming.
0h
VIO1 = 1.7 V, LDO regulator disabled.
1h
VIO1 = 1.8 V, LDO regulator disabled.
2h
VIO1 = 2.5 V, VIO2 = 1.7 V.
3h
VIO1 = 2.5 V, VIO2 = 1.8 V.
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5.11.8 MISC (05h)
Figure 5-19. MISC Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
FREQ
R/W-1
0
VCORE
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-7. MISC Register Field Descriptions
Bit
Field
Value
7–3
Not Implemented
N/A
2
FREQ
1–0
46
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
This bit configures boost converter 1's (AVDD) switching frequency.
0h
750 kHz
1h
1200 kHz
VCORE
These bits configure buck converter 1's (VCORE) output voltage.
0h
1V
1h
1.1 V
2h
1.2 V
3h
1.3 V
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5.11.9 SS1 (06h)
Figure 5-20. SS1 Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
SS1
R/W-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-8. SS1 Register Field Descriptions
Bit
Field
Value
7–3
Not Implemented
N/A
2–0
SS1
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the soft-start time for buck converter 1 (VCORE), buck converter 2 (VIO1) and
the LDO linear regulator (VIO2).
0h
0.5 ms
1h
1 ms
2h
1.5 ms
3h
2 ms
4h
2.5 ms
5h
3 ms
6h
3.5 ms
7h
4 ms
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5.11.10 SS2 (07h)
Figure 5-21. SS2 Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
SS2
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-9. SS2 Register Field Descriptions
48
Bit
Field
7–3
Not Implemented
2–0
SS2
Value
Description
N/A 0 1 These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the soft-start time for boost converter 1 (AVDD) and boost converter 2 (VGH).
0h
4 ms
1h
4.5 ms
2h
5 ms
3h
5.5 ms
4h
6 ms
5h
6.5 ms
6h
7 ms
7h
7.5 ms
Detailed Description
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5.11.11 RESET (08h)
Figure 5-22. RESET Register Bit Allocation
7
6
5
4
3
2
1
Not Implemented
0
RESET
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-10. RESET Register Field Descriptions
Bit
Field
Value
7–2
Not Implemented
N/A
1–0
RESET
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the duration of the reset pulse during start-up.
0h
2 ms
1h
4 ms
2h
8 ms
3h
16 ms
Detailed Description
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5.11.12 DLY1 (09h)
Figure 5-23. DLY1 Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
DLY1
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-11. DLY1 Register Field Descriptions
50
Bit
Field
Value
7–3
Not Implemented
N/A
2–0
DLY1
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the start-up delay for boost converter 1 (AVDD).
0h
0 ms
1h
10 ms
2h
20 ms
3h
30 ms
4h
40 ms
5h
50 ms
6h
60 ms
7h
70 ms
Detailed Description
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5.11.13 DLY6 (0Ah)
Figure 5-24. DLY6 Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
DLY6
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-12. DLY6 Register Field Descriptions
Bit
Field
Value
7–3
Not Implemented
N/A
2–0
DLY6
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the delay between VGH reaching its final value and gate voltage shaping or
XAO being enabled.
0h
0 ms
1h
5 ms
2h
10 ms
3h
15 ms
4h
20 ms
5h
25 ms
6h
30 ms
7h
35 ms
Detailed Description
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5.11.14 VDET (0Bh)
Figure 5-25. VDET Register Bit Allocation
7
6
5
4
3
2
Not Implemented
1
0
VDET
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-13. VDET Register Field Descriptions
52
Bit
Field
Value
7–3
Not Implemented
N/A
2–0
VDET
Description
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
These bits configure the threshold for XAO and RST (if RMODE is "1" in the CONFIG register).
0h
2.2 V
1h
2.3 V
2h
2.4 V
3h
2.5 V
4h
3.6 V
5h
3.7 V
6h
3.8 V
7h
3.9 V
Detailed Description
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5.11.15 GAMxHI (0Ch, 0Eh…26h)
Figure 5-26. GAMxHI Register Bit Allocation
7
6
5
4
3
2
1
Not Implemented
0
GAMxHI
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-14. GAMxHI Register Field Descriptions
Bit
Field
Value
7–2
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
Description
1–0
GAMxHI
0h–3h
These bits form the two most significant bits of the 10-bit GAMx value used to program the gamma
correction voltage for channel x.
Detailed Description
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5.11.16 GAMxLO (0Dh, 0Fh…27h)
Figure 5-27. GAMxLO Register Bit Allocation
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
R/W-0
GAMxLO
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-15. GAMxLO Register Field Descriptions
54
Bit
Field
7–0
GAMxLO
Value
Description
00h–FF These bits form the least significant eight bits of the 10-bit value used to program the gamma
h
correction voltage for channel x.
Detailed Description
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5.11.17 Control (FFh)
Figure 5-28. CONTROL Register Bit Allocation
7
6
5
WED
4
3
2
Not Implemented
1
0
RED
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-16. CONTROL Register Field Descriptions
Bit
Field
7
WED
6–1
Not Implemented
0
RED
Value
Description
Setting this bit forces the contents of all DAC registers to be copied to the EEPROM, thereby
making them the default values during power-up.
0
Not used. This bit is automatically reset to 0 when the contents of the DAC registers have
been copied to EEPROM.
1
The contents of all DAC registers are copied to the EEPROM, making them the new default values
following power-up.
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
This bit configures the data returned by read operations.
0
Read operations return the contents of the DAC registers.
1
Read operations return the content of the EEPROM registers.
Detailed Description
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5.11.18 Example – Writing to a Single RAM Register
1.
2.
3.
4.
5.
6.
7.
8.
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65642A acknowledges
Bus master sends address of RAM register (00h)
TPS65642A acknowledges
Bus master sends data to be written
TPS65642A acknowledges
Bus master sends STOP condition
74h
S
7-Bit Slave Address
00h
0
A
RAM Register Address
DATA
A
RAM Register Data
A
P
Figure 5-29. Writing to a Single RAM Register
56
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5.11.19 Example – Writing to Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65642A acknowledges
4. Bus master sends address of first RAM register to be written to (00h)
5. TPS65642A acknowledges
6. Bus master sends data to be written to first RAM register
7. TPS65642A acknowledges
8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
9. TPS65642A acknowledges
10. Steps (8) and (9) repeated until data for final RAM register has been sent
11. TPS65642A acknowledges
12. Bus master sends STOP condition
74h
S
7-Bit Slave Address
00h
0
A
RAM Register Address (n)
DATA
A
DATA
RAM Register Data (n)
A
RAM Register Data (n+1)
A
DATA
RAM Register Data (Last)
A
P
Figure 5-30. Writing to Multiple RAM Registers
Detailed Description
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5.11.20 Example – Saving Contents of all RAM Registers to EEPROM
1.
2.
3.
4.
5.
6.
7.
8.
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65642A acknowledges
Bus master sends address of Control Register (FFh)
TPS65642A acknowledges
Bus master sends data to be written to the Control Register (80h)
TPS65642A acknowledges
Bus master sends STOP condition
74h
S
7-Bit Slave Address
FFh
0
A
Control Register Address
80h
A
Control Register Data
A
P
Figure 5-31. Saving Contents of all RAM Registers to E2PROM
58
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5.11.21 Example – Reading from a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of RAM register (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends RAM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
S
74h
FFh
00h
7-Bit Slave Address
A
Control Register Address
Control Register Data
A
RAM Register Address
0
A
A
P
1
A
R/W
S
7-Bit Slave Address
74h
00h
74h
0
A
Sr
7-Bit Slave Address
DATA
RAM Register Data
A
P
Figure 5-32. Reading from a Single RAM Register
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5.11.22 Example – Reading from a Single EEPROM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of EEPROM register (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends EEPROM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
74h
S
7-Bit Slave Address
S
7-Bit Slave Address
FFh
01h
Control Register Data
0
A
Control Register Address
0
A
EEPROM Register Address
74h
A
A
P
1
A
74h
00h
A
Sr
7-Bit Slave Address
DATA
EEPROM Register Data
A
P
Figure 5-33. Reading from a Single EEPROM Register
60
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5.11.23 Example – Reading from Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of first register to be read (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends contents of first RAM register to be read
18. Bus master acknowledges
19. TPS65642A sends contents of second RAM register to be read
20. Bus master acknowledges
21. TPS65642A sends contents of third (last) RAM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
74h
S
7-Bit Slave Address
00h
FFh
0
A
Control Register Address
A
RAM Register Address (n)
Control Register Data
A
A
P
1
A
R/W
74h
S
7-Bit Slave Address
00h
0
DATA
74h
A
Sr
7-Bit Slave Address
DATA
RAM Register Data (n+1)
RAM Register Data (n)
A
DATA
A
RAM Register Data (Last)
A
P
Figure 5-34. Reading from Multiple RAM Registers
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5.11.24 Example – Reading from Multiple EEPROM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of first EEPROM register to be read (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends contents of first EEPROM register to be read
18. Bus master acknowledges
19. TPS65642A sends contents of second EEPROM register to be read
20. Bus master acknowledges
21. TPS65642A sends contents of third (last) EEPROM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
74h
S
7-Bit Slave Address
0
FFh
01h
A
Control Register Address
Control Register Data
A
EEPROM Register Addr (n)
A
A
P
1
A
R/W
74h
S
7-Bit Slave Address
74h
00h
0
A
Sr
7-Bit Slave Address
DATA
DATA
EEPROM Register Data (n+1)
EEPROM Register Data (n)
A
DATA
A
EEPROM Register Data (Last)
A
P
Figure 5-35. Reading from Multiple EEPROM Registers
62
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5.11.25 Configuration Parameter VCOM
Figure 5-36. VCOM Register Bit Allocation
7
6
5
4
3
2
1
VCOM
R/W-0
R/W-0
R/W-0
R/W-0
0
P
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-17. VCOM Register Field Descriptions
Bit
Field
7–1
VCOM
Value
00h–7F
h
0
Description
During write operations these bits contain the data to be written. During read operations these bits
contain the contents of the EEPROM register.
P
V
VCOM + 1
IOUT = REF ´
R SET
128
During write operations this bit configures the destination for data.
0
Data is written to the DAC register and EEPROM.
1
Data is written to the DAC register only.
During read operations this bit indicates whether the contains of the RAM register and EEPROM
are the same or not.
0
DAC register and EEPROM contents are the same.
1
DAC register and EEPROM contents are different.
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5.11.26 Example – Writing a VCOM Value of 77h to RAM Register Only
1.
2.
3.
4.
5.
6.
Bus master sends a START condition.
Bus master sends 9E hexadecimal (7-bit slave address plus low R/W bit).
TPS65642A slave acknowledges.
Bus master sends EF hexadecimal (data to be written plus LSB = 1).
TPS65642A slave acknowledges.
Bus master sends a STOP condition.
4Fh
S
77h
7-Bit Slave Address
0
A
Data to be Written
1
A
P
Figure 5-37. Writing a VCOM Value of 77h to RAM Only
5.11.27 Example – Writing a VCOM Value of 77h to EEPROM and RAM
1.
2.
3.
4.
5.
6.
Bus master sends a START condition.
Bus master sends 9E hexadecimal (7-bit slave address plus low R/W bit).
TPS65642A slave acknowledges.
Bus master sends EE hexadecimal (data to be written plus LSB = 0).
TPS65642A slave acknowledges.
Bus master sends a STOP condition.
4Fh
S
77h
7-Bit Slave Address
0
A
Data to be Written
0
A
P
Figure 5-38. Writing a VCOM Value of 77h to EEPROM and RAM
64
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5.11.28 Example — Reading a VCOM Value of 77h from EEPROM When RAM Contents are
Identical
1.
2.
3.
4.
5.
6.
Bus master sends a START condition.
Bus master sends 9F hexadecimal (7-bit slave address plus high R/W bit).
TPS65642A slave acknowledges.
TPS65642A sends EE hexadecimal from EEPROM (data to be read plus LSB = '0').
Bus master does not acknowledge.
Bus master sends a STOP condition.
4Fh
S
77h
7-Bit Slave Address
1
A
Data to be Read
0
A
P
Figure 5-39. Reading 77h from EEPROM when RAM Contents are Identical
5.11.29 Example —Reading a VCOM Value of 77h from EEPROM When RAM Contents are
Different
1.
2.
3.
4.
5.
6.
Bus master sends a START condition.
Bus master sends 9F hexadecimal (7-bit slave address plus high R/W bit).
TPS65642A slave acknowledges.
TPS65642A sends EF hexadecimal from RAM (data to be read plus LSB = '0').
Bus master does not acknowledge.
Bus master sends a STOP condition.
4Fh
S
77h
7-Bit Slave Address
1
A
Data to be Read
1
A
P
Figure 5-40. Reading 77h from EEPROM when RAM Contents are Different
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5.11.30 I2C Interface
Configuration parameters and the VCOM voltage setting are programmed through an industry standard I2C
serial interface. The TPS65642A device always works as a slave device and supports standard (100 kbps)
and fast (400 kbps) modes of operation. During write operations, all further attempts to access the slave
addresses are ignored until the current write operation is complete.
NOTE
The I2C interface contains a known bug. If a new start condition appears on the bus
before transfer of the slave address byte from a previously initiated read/write
operation is complete, the I2C interface may hang. Normal operation is recovered after
cycling VIN.
5.12 POWER SEQUENCING
1. Buck converter 1 (VCORE), Buck converter 2 (VIO1), and the linear regulator (VIO2) start as soon as VIN >
VUVLO.
2. The reset generator holds RST low until tRESET seconds after VCORE has reached power good status.
3. Boost converter 1 starts tDLY1 milliseconds after EN goes high (or RST has gone high, whichever
occurs later). Once asserted, the EN signal must remain high to ensure normal device operation. Once
disabled (EN = 0), boost converter 1 remains disabled until the device is powered down (even if EN is
re-asserted).
4. Boost converter 2 starts as soon as AVDD has reached power-good status.
5. In non-GIP mode, VGHM is held at high impedance until tDLY6 milliseconds after VGH reaches powergood status; XAO goes high when VIN > VDET and low when VIN < VDET.
6. In GIP mode, XAO is held low until tDLY6 milliseconds after VGH reaches power-good status.
Figure 5-41 and Figure 5-42 show the typical power-up or down characteristics of the TPS65642A device
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EN
VIN < VDET
VIN > VDET
VIN
VIN > VUVLO
VIN < VUVLO
tSS1
Actively
discharged
VIO1
Actively discharged
through backgate diode
VIO2
enabled
Discharged
through load
VCORE
RST
RMODE=0
RST
RMODE=1
AVDD
SMODE=0
tRESET
Pulled low
tRESET
Pulled low
tDLY1
Actively
discharged
tSS2
AVDD
SMODE=1
Discharged
through load
tSS2
VGH
Discharged
through load
VGL
Discharged
through load
VGHM
Held high as long
as possible
(tracks VGH)
XAO
GIP=1
Held high as long
as possible
XAO
GIP=0
Pulled low
tDLY6
VCOM
SMODE=0
Remains active
(tracks AVDD)
VCOM
SMODE=1
POS pin
pulled low
VGAM
AVDD=3V
Pulled low
Figure 5-41. Power-Up or Power-Down Sequencing With EN Connected to VIN
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EN
VIN
VIN > VDET
VIN > VUVLO
VIN < VDET
VIN < VUVLO
tSS1
Actively
discharged
VIO1
Actively discharged
through backgate diode
VIO2
enabled
Discharged
through load
VCORE
RST
RMODE=0
RST
RMODE=1
AVDD
SMODE=0
tRESET
Pulled low
tRESET
Pulled low
tDLY1
Actively
discharged
tSS2
AVDD
SMODE=1
Discharged
through load
tSS2
VGH
Discharged
through load
VGL
Discharged
through load
VGHM
Held high as long
as possible
(tracks VGH)
XAO
GIP=1
Held high as long
as possible
XAO
GIP=0
Pulled low
tDLY6
VCOM
SMODE=0
Remains active
(tracks AVDD)
VCOM
SMODE=1
POS pin
pulled low
VGAM
AVDD=3V
Pulled low
Figure 5-42. Power-Up or Power-Down Sequencing With EN Connected to T-CON Ready
68
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5.13 UNDERVOLTAGE LOCKOUT
An undervoltage lockout function disables the TPS65642A device when the supply voltage is too low for
proper operation.
6 Application Information
6.1
External Component Selection
Care must be applied to the choice of external components because these components greatly affect
overall performance. The TPS65642A device was developed with the two goals of high performance and
small or low-profile solution size. Because these two goals are often in direct opposition to one another
(for example, larger inductors tend to achieve higher efficiencies), some trade-off is always necessary.
Inductors must have adequate current capability so that the inductors do not saturate under worst-case
conditions. For high efficiency, inductors must also have low DC resistance (DCR).
Capacitors must have adequate effective capacitance under the applicable DC bias conditions they
experience in the application. MLCC capacitors typically exhibit only a fraction of the nominal capacitance
under real-world conditions and this must be taken into consideration when selecting capacitors. This
problem is especially acute in low profile capacitors, in which the dielectric field strength is higher than in
taller components. In general, the capacitance values shown in the circuit diagrams in this data sheet refer
to the effective capacitance after DC bias effects have been taken into consideration. Reputable capacitor
manufacturers provide capacitance-versus-DC-bias curves that greatly simplify component selection.
Table 6-1, Table 6-2,Table 6-3, Table 6-4, and Table 6-5 list some components suitable for use with the
TPS65642A device. The list is not exhaustive — other components may exist that are equally suitable (or
better), however, these components have been proven to work well and were used extensively during the
development of the TPS65642A device.
Table 6-1. Boost Converter 1 External Components
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
L
Chip Inductor, 4.7 μH, ±20%
1269AS-H-4R7N
Toko
< 1 mm
CIN
Ceramic Capacitor, X5R, 10 µF, 16 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
COUT
Table 6-2. Buck Converter 1 External Component Recommendations
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
L
Chip Inductor
1269AS-H-2R2N
Toko
< 1 mm
COUT
Ceramic Capacitor, X5R, 10 = µF, 6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
Table 6-3. Buck Converter 2 External Component Recommendations
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
L
Chip Inductor
1269AS-H-2R2
Toko
THICKNESS
< 1 mm
COUT
Ceramic Capacitor, X5R, 10 µF, 6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
Table 6-4. LDO Regulator External Component Recommendations
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
COUT
Ceramic Capacitor, X5R, 10 µF,6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
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Table 6-5. Boost Converter 2 External Components
6.2
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
L
Wirewound Inductor, 15 μH, ±20%
1156AS-150M
Toko
< 1 mm
L
Wirewound Inductor, 15 μH, ±20%
LQH3NPN150NG0
Murata
< 1 mm
COUT
Ceramic Capacitor, X5R, 4.7 µF, 50 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
D
Switching Diode, 150 mA, 75 V, 350
mW
BAS16W
Infineon
< 1 mm
Typical Application Circuit
Figure 6-1 and Figure 6-2 show the recommended application circuits for non-GIP and GIP displays
respectively. Minor changes may be required to optimize the circuit for a specific application, however, the
basic circuit is unlikely to change significantly.
70
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Product Folder Links: TPS65642A
TPS65642A
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SLVSC21 – OCTOBER 2013
470nF BAV99
VGL
2.2µF
4.7R
4.7µH
VIN
AVDD
20µF
10µF
SW1 AVDD
VIN
AVDD
1.5nF
56k
10µF
VIO1
BOOST
CONVERTER 1
COMP
EN
From T-CON
10k
To T-CON
CONTROL
XAO
To Level Shifter
LDO REGULATOR
VIO2
VIO2
RST
10µF
AVDD
TCOMP
15µH
BOOST
CONVERTER 2
VGH
SW4
BAS16W
2.2µF
2.2µH
VCORE
SW2
VCORE
20µF
BUCK
CONVERTER 1
2.2µH
VIO1
SW3
VIO1
10µF
From T-CON
BUCK
CONVERTER 2
GATE
VOLTAGE
SHAPING
FLK
AVDD
RE
VGH
VGHM
VGHM
VGAMH
1k
VGAMA
OUTA
OUTH
VGAMB
OUTB
OUTI
VGAMI
VGAMC
OUTC
OUTJ
VGAMJ
VGAMD
OUTD
OUTK
VGAMK
VGAME
OUTE
OUTL
VGAML
VGAMF
OUTF
OUTM
VGAMM
VGAMG
OUTG
OUTN
VGAMN
AVDD
AVDD
GAMMA
REF
1µF
AVDD
To/From
T-CON
SCL
2
I C INTERFACE
WP
From T-CON
SDA
12.7k
1k
POS1
NEG1
7.5k
191R
POS2
PROGRAMMABLE
VCOM
VCOM1
OUT1
1k
11.8k
100nF
VCOM1 Feedback
24.9k
NEG2
100nF
VCOM2 Feedback
RSET
7.5k
OUT2
PGND
VCOM2
AGND
Figure 6-1. Typical Application Circuit for Non-GIP Displays
Application Information
Copyright © 2013, Texas Instruments Incorporated
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470nF BAV99
VGL
2.2µF
4.7R
4.7µH
VIN
AVDD
20µF
10µF
SW1 AVDD
VIN
AVDD
1.5nF
56k
10µF
VIO1
BOOST
CONVERTER 1
COMP
EN
From T-CON
10k
To T-CON
CONTROL
XAO
LDO REGULATOR
VIO2
RST
To Level Shifter
VIO2
10µF
AVDD
10k@25°C
10.4k
TCOMP
15µH
BOOST
CONVERTER 2
VGH
SW4
10.2k
BAS16W
2.2µF
2.2µH
VCORE
SW2
VCORE
20µF
BUCK
CONVERTER 1
2.2µH
VIO1
SW3
VIO1
10µF
BUCK
CONVERTER 2
GATE
VOLTAGE
SHAPING
FLK
RE
VGH
VGH
VGHM
VGAMA
OUTA
OUTH
VGAMH
VGAMB
OUTB
OUTI
VGAMI
OUTJ
VGAMJ
OUTK
VGAMK
VGAMC
OUTC
VGAMD
OUTD
VGAME
OUTE
OUTL
VGAML
VGAMF
OUTF
OUTM
VGAMM
VGAMG
OUTG
OUTN
VGAMN
AVDD
AVDD
GAMMA
REF
1µF
AVDD
To/From
T-CON
SCL
2
I C INTERFACE
WP
From T-CON
SDA
12.7k
1k
POS1
NEG1
7.5k
191R
POS2
PROGRAMMABLE
VCOM
VCOM1
OUT1
1k
11.8k
100nF
VCOM1 Feedback
24.9k
NEG2
100nF
VCOM2 Feedback
RSET
7.5k
OUT2
PGND
VCOM2
AGND
Figure 6-2. Typical Application Circuit for GIP Displays
72
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Product Folder Links: TPS65642A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65642AYFFR
ACTIVE
DSBGA
YFF
56
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65642A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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