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TPS65708
SLVSAE1B – OCTOBER 2010 – REVISED SEPTEMBER 2015
TPS65708 PMU for Embedded Camera Module
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
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•
Two 400-mA Step-Down Converters
Up to 95% Efficiency
VIN Range for DC-DC Converters From
3.6 V to 6 V
2.25-MHz Fixed-Frequency Operation
Power Save Mode at Light Load Current
Output Voltage Accuracy in PWM mode ±1.5%
100% Duty Cycle for Lowest Dropout
180° Out-of-Phase Operation
2 General Purpose 200-mA LDOs
LDOs Optionally Powered From Step-Down
Converters
7.5-mA PWM Dimmable Current Sink
Available in a 16-Ball DSBGA (WCSP) With
0.5-mm Pitch
Device Options:
– VDCDC1 = 3.3 V
– VDCDC2 = 1.8 V
– VLDO1 = 2.8 V
– VLDO2 = 1.2 V
– ISINK(PWM=1) = 7.5 mA
– SEQUENCING : DCDC1, LDO1, DCDC2,
LDO2
Monitors
Laptops
Handheld Equipment
3 Description
The TPS65708 device is a power management unit
targeted for embedded camera modules or other
portable low-power consumer end equipment. The
device contains two high-efficiency step-down
converters, two low-dropout linear regulators, and a
7.5-mA current sink for driving a LED. The 2.25-MHz
step-down converter enters a low-power mode at light
load for maximum efficiency across the widest
possible range of load currents. For low-noise
applications, the devices can be forced into fixedfrequency PWM mode using the MODE pin. The
device allows the use of small inductors and
capacitors to achieve a small solution size. The
TPS65708 device provides an output current of up to
400 mA on both DC-DC converters and up to 200 mA
on each of the LDOs. The enable signal to the DCDC converters and LDOs is generated internally by
the undervoltage lockout circuit.
The TPS65708 comes in a small 16-pin wafer chipscale package (WCSP) with 0.5-mm ball pitch.
Device Information(1)
PART NUMBER
TPS65708
PACKAGE
DSBGA (16)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
VCC
TPS65708
L1 1.5 mH
VIN1
DCDC1
400 mA
Vout1
10 mF
FB1
PGND1
MODE
L2 1.5 mH
VIN2
DCDC2
400 mA
Vout2
10 mF
FB2
PGND2
VLDO1
VINLDO1
LDO1
200 mA
2.2 mF
VLDO2
VINLDO2
LDO2
200 mA
Vout3
Vout4
2.2 mF
V(USB)
PWM
ISINK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65708
SLVSAE1B – OCTOBER 2010 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 11
7.1 Setup....................................................................... 10
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Applications ................................................ 15
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2011) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Original (October, 2010) to Revision A
•
2
Page
Page
Corrected pin location identification for VCC, VIN1, and VIN2 pins....................................................................................... 3
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5 Pin Configuration and Functions
YZH Package
16-Pin DSBGA
Bottom View
VIN2
C4
PGND2
D4
VLDO2
A4
Vcc
B4
A4
FB2
C3
L2
D3
VINLDO2
A3
MODE
B3
A3
FB1
C2
L1
D2
PWM
B2
VINLDO1
A2
A2
VIN1
C1
PGND1
D1
VLDO1
A1
ISINK
B1
A1
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
A1
VLDO1
O
Output voltage from LDO1
A2
VINLDO1
I
Input voltage pin for LDO1
A3
VINLDO2
I
Input voltage pin for LDO2
A4
VLDO2
O
Output voltage from LDO2
B1
ISINK
O
Open-drain current sink; connect to the cathode of a LED
B2
PWM
I
Input for LED PWM dimming
B3
MODE
I
Set low to enable Power Save Mode. Pulling this PIN to high forces the device to operate in PWM mode
over the whole load range.
B4
VCC
I
Supply Input for internal reference, has to be connected to VIN1 and VIN2
C1
VIN1
I
Input voltage pin for buck converter (1)
C2
FB1
I
Feedback input from buck converter (1)
C3
FB2
I
Feedback input from buck converter (2)
C4
VIN2
I
Input voltage pin for buck converter (2)
D1
PGND1
—
Power ground
D2
L1
O
Switch output from buck converter (1)
D3
L2
O
Switch output from buck converter (2)
D4
PGND2
—
Power ground
(1)
(2)
VCC must be the highest input voltage for the device to operate correctly.
VIN1/VIN2 must be connected to VCC.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
Voltage
Current
MIN
MAX
UNIT
All pins except A/PGND pins with respect to
AGND
–0.3
7
V
Pin VLDO1 and VLDO2 with respect to AGND
–0.3
3.6
V
L1, L2, VLDO1, VLDO2, PGND
700
mA
AGND, ISINK
50
mA
All other pins
3
mA
85
°C
125
°C
150
°C
Operating free-air temperature, TA
–40
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VIN1/2
Input voltage for step-down converter DCDC1and DCDC2
3.6
6
VOUTDCDC1/2
Output voltage for DCDC1 and DCDC2 step-down converter
0.8
3.3
V
IOUTDCDC1
DC output current at L1 or L2
400
mA
L
Inductor at L1 or L2 (1)
2.2
µH
VINLDO1
Input voltage for LDO1
1.7
6
V
VLDO
Output voltage for LDO1 and LDO2
0.8
3.3
V
VINLDO2
Input voltage for LDO2
1.7
ILDO
Output current at LDO1 or LDO2
CINDCDC1/2
Input capacitor at VIN1 and VIN2
4.7
COUTDCDC1/2
Output capacitor at VOUT1, VOUT2
4.7
COUTLDO1/2
Output capacitor at VLDO1, VLDO2
2.2
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
4
1
1.5
6
200
V
V
mA
µF
10
22
µF
µF
To support a typical inductor value of 1.5 µH, the minimum inductance can go as low as 1 µH. It is not recommended to use a 1-µH
labeled inductor as the inductance will drop significantly below 1 µH in operation due to initial tolerances and saturation.
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6.4 Thermal Information
TPS65708
THERMAL METRIC (1)
YZH (DSBGA)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
75
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22
°C/W
RθJB
Junction-to-board thermal resistance
26
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
24
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted: VIN1 = VIN2 = VCC = 5 V, L = 1.5 µH, COUTDCDCx = 10 µF, COUTLDOx = 2.2 µF, TA = –40°C to 85°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DCDC1, DCDC2, LDO1 and LDO2 enabled,
IOUT = 0 mA, MODE = 0; (PFM mode)
ISINK in standby for PWM = 0
140
200
μA
DCDC1, DCDC2, LDO1 and LDO2 enabled,
IOUT = 0 mA, MODE = 1 ; (PWM mode)
ISINK in standby if PWM = 0;
Not including inductor losses
4
mA
DCDC1, DCDC2, LDO1 and LDO2 enabled,
IOUT = 0 mA, MODE = 0; (PFM mode) ;
ISINK in standby PWM = 0;
During power-up sequencing
170
μA
SUPPLY CURRENT
IQ
ISD
Operating quiescent current DCDCx and
LDOx
Shutdown Current
DCDCx, LDOx and ISINK disabled;
VCC < 1.8 V
6
15
μA
VCC
V
DIGITAL PINS ( MODE)
VIH
High-Level Input Voltage for MODE
VIL
Low-Level Input Voltage for MODE
Ilkg
Input Leakage Current
1.2
0
MODE tied to GND or VIN1 / VIN2
0.4
V
0.01
0.1
μA
3.6
3.7
V
UNDERVOLTAGE LOCKOUT (UVLO), SENSED AT PIN VCC
UVLO
Internal undervoltage lockout threshold
VCC, VIN1, VIN2 rising
Internal undervoltage lockout threshold
hysteresis
VCC, VIN1, VIN2 falling
3.5
130
mV
STEP-DOWN CONVERTERS
VIN1
Input voltage for DCDC1
3.5
6
V
VIN2
Input voltage for DCDC2
3.5
6
V
POWER SWITCH
High-side MOSFET ON-resistance
VIN1 / VIN2 = 3.6 V
250
400
mΩ
Low-side MOSFET ON-resistance
VIN1 / VIN2 = 3.6 V
150
300
mΩ
ILIMF
Forward current limit
3.6 V ≤ VIN1 / VIN2 ≤ 6 V
820
1050
mA
IO
DC output current
VIN1 / VIN2 > 3.5 V , L = 1.5 µH
400
mA
RDS(on)
650
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Electrical Characteristics (continued)
Unless otherwise noted: VIN1 = VIN2 = VCC = 5 V, L = 1.5 µH, COUTDCDCx = 10 µF, COUTLDOx = 2.2 µF, TA = –40°C to 85°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.03
2.25
2.48
MHz
OSCILLATOR
fSW
Oscillator frequency
OUTPUT
VOUT1
DCDC1 default output voltage
VIN1 ≥ 3.6 V
3.3
V
VOUT2
DCDC2 default output voltage
VIN2 ≥ 3.6 V
1.8
V
IFB
FB pin input current
DC-DC converter input voltage below
undervoltage lockout threshold
RFB
FB pin input resistance due to internal
voltage divider
DC-DC converter input voltage above
undervoltage lockout threshold; VOUT = 3.3 V
990
kΩ
RFB
FB pin input resistance due to internal
voltage divider
DC-DC converter input voltage above
undervoltage lockout threshold; VOUT = 1.8 V
585
kΩ
DC output voltage accuracy (1)
VIN1 and VIN2 = 3.6 V to 6 V, +1% voltage
positioning active; PFM operation,
0 mA < IOUT < IOUTmax
DC output voltage accuracy
VIN1 / VIN2 = 3.3V to 6V, PWM operation,
0 mA < IOUT < IOUTmax
DC output voltage load regulation
PWM operation
0.5
%/A
tStart
Start-up time
Time from UVLO is exceeded (Vin > 3.6 V) to
Start switching
200
µs
tRamp
VOUT ramp time
Time to ramp from 5% to 95% of VOUT
RDIS
Internal discharge resistor at L1 and L2
DCDCx disabled; 1 V < VIN1/2 < 3.6 V
VOUT
0.1
1.25%
–1.5%
3%
1.5%
250
300
µA
400
µs
550
Ω
THERMAL PROTECTION SEPARATELY FOR DCDC1, DCDC2 and LDO1
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
30
°C
VLDO1, VLDO2 LOW DROPOUT REGULATOR
VINLDO
Input voltage range for LDO1 and LDO2
VLDO1
LDO1 Default Output Voltage (1)
1.7
2.8
6
V
V
VLDO2
LDO2 Default Output Voltage
1.2
V
IO
Output current for LDO1 and LDO2
ISC
LDO1 and LDO2 short circuit current limit
VLDOx = GND
Dropout voltage at LDOx
200
mA
550
mA
IO = 200 mA; VINLDOx = 3.3 V
200
mV
Dropout voltage at LDOx
IO = 200 mA; VINLDOx = 1.8 V
300
mV
Output voltage accuracy for LDO1 and
LDO2
IO = 200 mA
–2%
2%
Line regulation for LDO1 and LDO2
VINLDO = VLDO + 0.5 V (min 1.7 V) to 6 V,
IO = 50 mA
–1%
1%
Load regulation for LDO1 and LDO2
IO = mA to 200 mA
–1.5%
1%
PSRR
Power Supply Rejection Ratio
f = 10 kHz, COUT ≥ 2.2 μF VINLDOx = 5 V,
VOUT = 2.8 V, IOUT = 100 mA
Vn
Output noise voltage
tRamp
RDIS
(1)
6
260
360
50
dB
VOUT = 2.8 V, BW = 10 Hz to 100 kHz
160
µV
RMS
VOUT ramp time
Internal soft start when LDO is enabled;
Time to ramp from 5% to 95% of VOUT
250
µs
Internal discharge resistor at VLDO1 and
VLDO2
VIN < UVLO
200
400
550
Ω
VINLDO > 2.8 V
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Electrical Characteristics (continued)
Unless otherwise noted: VIN1 = VIN2 = VCC = 5 V, L = 1.5 µH, COUTDCDCx = 10 µF, COUTLDOx = 2.2 µF, TA = –40°C to 85°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LED CURRENT SINK
ILED
Isink Current (LED current for 100% duty
cycle)
Set internally by EEPROM to 7.5 mA; available
current range from 7.5 mA to 30 mA; contact
factory about default settings other than 7.5 mA
Minimum voltage drop from ISINK to
AGND needed for proper regulation
at 7.5 mA ≤ ISINK ≤ 20 mA
0.4
V
Minimum voltage drop from ISINK to
AGND needed for proper regulation
at 20 mA < ISINK ≤ 30 mA
0.55
V
ISINK accuracy
ISINK ≥ 10 mA
ISINK accuracy
7.5 mA ≤ ISINK < 10 mA
PWM duty cycle
7.5
mA
–5%
5%
–10%
10%
5%
100%
1.2
VCC
V
0
0.4
V
0.1
μA
PWM frequency
50
VIH
High-Level Input Voltage for PWM pin
ISINK is enabled
VIL
Low-Level Input Voltage for PWM pin
ISINK is high resistive
Ilkg
Input Leakage Current on PWM pin
0.01
kHz
ISINK rise / fall time
V(ISINK) ≥ 0.4 V for 7.5 mA ≤ ISINK ≤ 20 mA; or
V(ISINK) > 0.6 V for 20 mA < ISINK ≤ 30 mA
500
ns
ISINK rise / fall time
V(ISINK) ≤ 0.6 V; 20 mA < ISINK ≤ 30 mA
700
ns
6.6 Typical Characteristics
Table 1. Table Of Graphs
FIGURE
η
Efficiency DCDC (VO = 3.3 V)
vs Load current / PFM mode
Figure 1
η
Efficiency DCDC (VO = 3.3 V)
vs Load current / PWM mode
Figure 2
η
Efficiency DCDC (VO = 1.2 V)
vs Load current / PFM mode
Figure 3
η
Efficiency DCDC (VO = 1.2 V)
vs Load current / PWM mode
Figure 4
Line transient response DCDC (PWM)
Scope plot for a 3.6 V to 5 V to 3.6 V input voltage
change
Figure 5
Line transient response DCDC (PFM)
Scope plot for a 3.6 V to 5 V to 3.6 V input voltage
change
Figure 6
Line transient response LDO
Scope plot for a 3.6 V to 5 V to 3.6 V input voltage
change
Figure 7
Load transient response DCDC (PFM)
Scope plot for a 10% to 90% load step (40 mA to 360
mA)
Figure 8
Load transient response DCDC (PWM)
Scope plot for a 10% to 90% load step (40 mA to 360
mA)
Figure 9
Load transient response LDO
Scope plot for a 10% to 90% load step (20 mA to 180
mA)
Figure 10
Startup timing DCDC1, DCDC2, LDO1 and LDO2
Scope plot of startup; R1 = supply voltage is applied
Figure 14
LDO POWER SUPPLY REJECTION RATIO (PSRR)
Scope plot
Figure 11
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100
100
3.6 V
90
90
80
80
4.2 V
70
70
3.6 V
Efficiency - %
Efficiency - %
5V
60
50
40
60
4.2 V
50
40
5V
30
30
20
20
10
10
0
0.1
1
10
IO - Output Current - mA
100
0
0.1
1k
Figure 1. Efficiency DCDC (VO = 3.3 V) vs Load Current /
PFM Mode; for VIN = 3.6 V to 5 V
1
10
IO - Output Current - mA
100
1k
Figure 2. Efficiency DCDC (VO = 3.3 V) vs Load Current /
PWM Mode; for VIN = 3.6 V to 5 V
100
100
90
3.6 V
4.2 V
90
3V
80
80
4.2 V
60
50
40
50
30
20
10
10
10
IO - Output Current - mA
100
1k
3V
5V
40
20
1
3.6 V
60
30
0
0.1
8
70
5V
Efficiency - %
Efficiency - %
70
0
0.1
1
10
IO - Output Current - mA
100
1k
Figure 3. Efficiency DCDC (VO = 1.2 V) vs Load Current /
PFM Mode; for VIN = 3 V to 5 V
Figure 4. Efficiency DCDC (VO = 1.2 V) vs Load Current /
PWM Mode; for VIN = 3 V to 5 V
Figure 5. Line Transient Response DCDC (PWM)
Figure 6. Line Transient Response DCDC (PFM)
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Figure 7. Line Transient Response LDO
Figure 8. Load Transient Response DCDC (PFM)
Figure 9. Load Transient Response DCDC (PWM)
Figure 10. Load Transient Response LDO
Figure 11. LDO Power Supply Rejection Ratio (PSRR)
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7 Parameter Measurement Information
7.1 Setup
The graphs in Typical Characteristics were taken using the TPS65708EVM with the passive components as
listed:
• L(Vout1) = L(Vout2) = BRC1608T1R5M (1.5 μH)
• C(Vout1) = C(Vout2) = GRM188R60J106 (10 μF / 6.3 V)
• C(LDO1) = C(LDO2) = GRM185R60J225 (2.2 μF / 6.3 V)
• C(VIN1) = C(VIN2) = GRM188R60J106 (10 μF / 6.3 V)
• C(VINLDO1) = C(VINLDO2) = GRM185R60J225 (2.2 μF / 6.3 V)
• VCC = VIN1= VIN2 = VINLDO1 = VINLDO2 unless otherwise noted
10
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8 Detailed Description
8.1 Overview
The TPS65708 device integrates two fixed-output voltage, highly efficient step-down converters, two fixed-output
voltage LDOs, and a 7.5-mA current sink with PWM dimming for driving and LED.
8.2 Functional Block Diagram
VCC
5V
TPS65708
L1
VIN1
10 mF
DCDC1
400 mA
1.5 mH
Vout1 = 3.3 V
10 mF
FB1
PGND1
MODE
L2
VIN2
10 mF
DCDC2
400 mA
1.5 mH
Vout2 = 1.8 V
10 mF
FB2
PGND2
VINLDO1
2.2 mF
VLDO1
LDO1
200 mA
VINLDO2
2.2 mF
Vout3 = 2.8 V
2.2 mF
VLDO2
LDO2
200 mA
Vout4 = 1.2 V
2.2 mF
5 V or 3.3 V
depending on LED
dimming signal
from uP
PWM
Current
Sink
7.5 mA
ISINK
8.3 Feature Description
8.3.1 DC-DC Converters
The TPS65708 step-down converters operate with typically 2.25-MHz fixed-frequency pulse width modulation
(PWM) at moderate to heavy load currents. With MODE pin set to low, at light load currents the converter can
automatically enter Power Save Mode and operates then in PFM mode.
During PWM operation, the converter uses a unique fast response voltage mode control scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is
turned on. The current flows now from the input capacitor through the high-side MOSFET switch through the
inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips
and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the
current limit of the high-side MOSFET switch is exceeded. After an off time preventing shoot through current, the
low-side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the
inductor to the output capacitor and to the load, and returns back to the inductor through the low-side MOSFET
rectifier.
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Feature Description (continued)
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
on the high-side MOSFET switch. A 180° phase shift between DCDC1 and DCDC2 decreases the input RMS
current and synchronizes the operation of the two DC-DC converters. The FB pin must directly be connected to
the output voltage of the DC-DC converter and no external resistor network must be connected. As the Feedback
input serves as the power input to the LOD, the external connection should be as short and as thick as possible
to keep the voltage drop as small as possible.
8.3.2 Power Save Mode
The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converter will enter
Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates
with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The
converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode
occurs once the inductor current in the low-side MOSFET switch becomes zero, which indicates discontinuous
conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the
output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current
pulse. The high-side MOSFET switch will turn on, and the inductor current ramps up. After the On-time expires,
the switch is turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with typical 25-µA current consumption.
If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage
ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify
the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage
ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value.
Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency
decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode
is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be
disabled by setting Mode pin to high. The converter will then operate in fixed-frequency PWM mode.
8.3.3 Dynamic Voltage Positioning
This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and heavy to
light. The feature is active in Power Save Mode and regulates the output voltage 1% higher than the nominal
value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load
throw-off.
Figure 12. Dynamic Voltage Positioning
12
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Feature Description (continued)
8.3.4 Soft Start
The step-down converter in TPS65708 has an internal soft-start circuit that controls the ramp up of the output
voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250 µs. This limits the
inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high
impedance power source is used.
EN
95%
5%
VOUT
t Start
t RAMP
Figure 13. Soft Start
8.3.5 100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output
voltage. In order to maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more
cycles. With further decreasing VIN the high-side MOSFET switch is turned on completely. In this case, the
converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications
to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:
VINmin = VOmax + IOmax (RDS(on)max + RL)
where
•
•
•
•
IOmax = maximum output current plus inductor ripple current
RDS(on)max = maximum high-side switch RDS(on)
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
(1)
8.3.6 180° Out-of-Phase Operation
In PWM Mode, the converters operate with a 180° turn-on phase shift of the PMOS (high-side) transistors. This
prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths
the input current. This feature reduces the surge current drawn from the supply.
8.3.7 Undervoltage Lockout and Enable for DCDC1, DCDC2, LDO1, and LDO2
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. The circuit disables the DC-DC converters and LDOs at too low input
voltages.
As TPS65708 does not have enable pins for the DC-DC converters and LDOs, the internal undervoltage lockout
not only serves as a protection circuit but also as an enable circuitry. The supply voltage to TPS65708 is
internally sensed at pin VCC. When the voltage at VCC exceeds 3.6 V, the internal enable signals to the DC-DC
converter and LDOs are set HIGH to start-up the outputs in the pre-defined sequence. When the supply voltage
drops below 3.6 V, the DC-DC converters and LDOs are disabled again and the discharge circuitry is enabled to
make sure the voltage at the output capacitor ramps down quickly. Disabling the DC-DC converter or LDO,
forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In
this mode, the power FETs are turned off and the entire internal control circuitry is switched off.
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Feature Description (continued)
8.3.8 Output Voltage Discharge
The DC-DC converters and LDOs contain an output capacitor discharge feature which makes sure that the
capacitor is discharged when the supply voltage drops below the undervoltage lockout threshold. The discharge
has a built in delay function, so the output discharge is active for a couple of 100 ms after the VCC voltage
dropped below its undervoltage lockout threshold. This will make sure that the capacitor is discharged even the
supply voltage dropped below 2.1 V. The discharge function is also enabled when voltage is applied at VCC
starting at about 2.1 V until the voltage exceeded the undervoltage lockout threshold that enables the power-up
sequencing.
8.3.9 Power-Up Sequencing
Three different power-up sequencing options are available. The options are factory set and can not be changed
by the user. Contact TI if an option different from the default is needed.
• DCDC1, DCDC2, LDO1, and LDO2 are turning on at the same time.
• DCDC1 first, when power good, LDO1 is enabled, when power good, DCDC2 is enabled when power good,
LDO2 is enabled
• DCDC2 first, when power good, LDO2 is enabled, when power good, DCDC1 is enabled when power good,
LDO1 is enabled
The TPS65708 is set to option 2 such that DCDC1 starts first followed by LDO1, DCDC2, and LDO2.
8.3.10 Short-Circuit Protection
All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.
8.3.11 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds typically 150°C for the DC-DC converters or LDOs, the device
goes into thermal shutdown. In this case, the low-side and high-side MOSFETs for the DC-DC converters as well
as the LDOs are turned off. The device continues its operation and powers up the DC-DC converters and LDOs
with the pre-defined sequencing when the junction temperature falls below the thermal shutdown hysteresis
again. During thermal shutdown also the LED driver is disabled.
8.3.12 LDOs
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.7 V. Both LDOs offer a maximum dropout voltage of 300
mV at rated output current. The LDOs support a current limit feature.
8.3.13 LED Driver
The TPS65708 contains a LED driver for a current of up to 30 mA. ISINK is an open drain current sink that
regulates a current in an LED. The anode of the LED needs to be tied to a positive supply voltage; for example,
VCC or the output voltage of one of the DC-DC converters in TPS65708, depending on the forward voltage of the
LED. The cathode of the LED is connected to ISINK which sets a constant current to GND. ISINK is regulated
internally based on the default current set internally. In addition, the LED current can be PWM dimmed by a
signal applied to pin PWM. If pin PWM is pulled LOW, the LED driver is disabled and its output ISINK is high
resistive. If PWM is HIGH, the current sink regulates to the current defined by EEPROM (TI factory set in two
ranges. 7.5 mA to 15 mA with 0.5-mA resolution and 15 mA to 30 mA in 1-mA resolution). The maximum PWM
frequency is 50 kHz with a duty cycle range of 5% to 100%. The TPS65708 is set to 7.5 mA as a default.
Contact TI about different default settings.
8.4 Device Functional Modes
The TPS65708 requires a power supply greater than UVLO threshold (3.6 V typical) at VCC pin. Otherwise, the
device will remain off with shutdown current defined in Electrical Characteristics. When a power supply rises
above the UVLO threshold DCDC1, DCDC2, LDO1, and LDO2 will turn on automatically in predefined order.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65708 device is designed for use as a power supply for embedded camera module or other portable
low-power equipment.
9.2 Typical Applications
9.2.1 Powering All Rails from the Input Supply of 5 V
VCC
5V
TPS65708
L1
VIN1
10 mF
DCDC1
400 mA
1.5 mH
Vout1 = 3.3 V
10 mF
FB1
PGND1
MODE
L2
VIN2
10 mF
DCDC2
400 mA
1.5 mH
Vout2 = 1.8 V
10 mF
FB2
PGND2
VINLDO1
2.2 mF
VLDO1
LDO1
200 mA
VINLDO2
2.2 mF
Vout3 = 2.8 V
2.2 mF
VLDO2
LDO2
200 mA
Vout4 = 1.2 V
2.2 mF
5 V or 3.3 V
depending on LED
dimming signal
from uP
PWM
Current
Sink
7.5 mA
ISINK
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Typical Applications (continued)
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
VALUE
Input Supply Voltage
3.6 V to 6 V
Switching Frequency
2.25 MHz
Output Filter Corner Frequency
40 kHz
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
9.2.1.2.1.1 Inductor Selection
The converter operates typically with a 1.5-µH or 2.2-µH output inductor. The selected inductor has to be rated
for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the
efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest
efficiency.
Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 2. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
Vout
1 ΔIL
Vin
ΔIL = Vout ´
ILmax = Ioutmax +
L ´ f
2
where
•
•
•
•
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
(2)
The highest inductor current will occur at maximum Vin.
Open-core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. It must be considered, that the core material from inductor to inductor differs and will
have an impact on the efficiency especially at high switching frequencies.
The step-down converter has internal loop compensation. The internal loop compensation is designed to work
with an output filter corner frequency calculated as follows:
1
fc =
with L = 1.5 mH, Cout = 10 mF
2π L ´ Cout
(3)
This leads to the fact the selection of external L-C filter has to be coped with the above equation. As a general
rule the product of L × COUT should be constant while selecting smaller inductor or increasing output capacitor
value.
Refer to Table 3 and the typical applications for possible inductors.
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Table 3. Tested Inductors
INDUCTOR TYPE
INDUCTOR VALUE
SUPPLIER
BRC1608
1.5 µH
Taiyo Yuden
MLP2012
2.2 µH
TDK
MIPSA2520
2.2 µH
FDK
GLCR1608T1R5M-HC
1.5 µH
TDK
LQM21P
2.2 µH
Murata
9.2.1.2.1.2 Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small
ceramic capacitors with a typical value of 10 µF, without having large output voltage under and overshoots during
heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are
therefore recommended. For an inductor value of 1.5 µH or 2.2 µH, an output capacitor with 10 µF can be used.
See the recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. Just for completeness the RMS ripple current is calculated as:
Vout
1 1
Vin ´
IRMSCout = Vout ´
L×f
2 ´ 3
(4)
At nominal load currents, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
Vout
1 1
ö
Vin ´ æ
ΔVout = Vout ´
+ ESR ÷
ç
L× f
8
´
Cout
´
f
è
ø
(5)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
9.2.1.2.1.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased
without any limit for better input voltage filtering.
Table 4. Tested Capacitors
TYPE
VALUE
VOLTAGE RATING
SIZE
SUPPLIER
MATERIAL
GRM155R60G475ME47D
4.7 µF
4V
0402
Murata
Ceramic X5R
GRM155R60J225ME15D
2.2 µF
6.3 V
0402
Murata
Ceramic X5R
GRM185R60J225
2.2 µF
6.3 V
0603
Murata
Ceramic X5R
GRM188R60J475K
4.7 µF
6.3 V
0603
Murata
Ceramic X5R
GRM188R60J106ME47D
10 µF
6.3 V
0603
Murata
Ceramic X5R
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9.2.1.3 Application Curve
Figure 14. Start-Up Sequencing
9.2.2 Powering the LDOs From the Output of the DC-DC Converters to Improve Efficiency
See Design Requirements, Detailed Design Procedure, and Application Curve.
5V
VCC
TPS65708
L1
VIN1
DCDC1
400 mA
10 mF
1.5 mH
Vout1 = 3.3 V
10 mF
FB1
PGND1
MODE
L2
VIN2
DCDC2
400 mA
10 mF
1.5 mH
Vout2 = 1.8 V
10 mF
FB2
PGND2
VINLDO1
VLDO1
LDO1
200 mA
2.2 mF
VINLDO2
VLDO2
LDO2
200 mA
2.2 mF
dimming signal
from uP
PWM
Vout3 = 2.8 V
2.2 mF
Current
Sink
7.5 mA
Vout4 = 1.2 V
2.2 mF
5 V or 3.3 V
depending on LED
ISINK
10 Power Supply Recommendations
The device is optimized to be powered from single-cell Lithium battery. The input supply at VCC pin is required to
stay above UVLO threshold without shutting down DC-DC converters. Power input pins of each regulator should
be properly bypassed through ceramic capacitors that work best when placed close to the input pins as close as
possible.
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11 Layout
11.1 Layout Guidelines
•
•
•
All input capacitors should be soldered as close as possible to the device.
All inductors should be placed as close as possible to switching pins through thick trace.
All feedback traces should be routed differentially and away from noisy traces such as switching signals.
11.2 Layout Example
VINLDO1
VINLDO2
VLDO1
Run feedback traces
differentially
GND
GND
VIN
VLDO2
L1
L2
GND
Run feedback traces
differentially
GND
Place inductors
close to Lx pins
VDCDC1
VDCDC2
GND
Figure 15. Layout Recommendation
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65708YZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65708
TPS65708YZHT
ACTIVE
DSBGA
YZH
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65708
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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