Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
TPS6572x Power Management IC (PMIC) With Battery Charger, One Step-Down Converter
and One LDO
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Battery Charger With Power Path Management
28-V Rated Power Path With:
– 100-mA Input Current Limit
– 500-mA Input Current Limit
300-mA Charge Current
200-mA Step-Down Converter for TPS65720
400-mA Step-Down Converter for TPS65721,
TPS657201, TPS657202
Up to 92% Efficiency
VIN Range for DCDC Converter From 2.3 V to
5.6 V
2.25-MHz Fixed Frequency Operation
Power Save Mode at Light Load Current
Output Voltage Accuracy in PWM Mode ±2%
100% Duty Cycle for Lowest Dropout
1 General Purpose 200-mA LDO
VIN Range for LDO From 1.8 V to 5.6 V
I2C Compatible Interface
4GPIOs
Available in a 25-Ball DSBGA With 0.4-mm Pitch
and in 4-mm × 4-mm 32-Pin WQFN Package
The device allows the use of small inductors and
capacitors to achieve a small solution size. The
TPS65720 provides an output current of up to
200 mA on the DC-DC converter while TPS657201,
TPS657202, and TPS65721 provide up to 400 mA.
The TPS6572x also integrates one 200-mA LDO. The
LDO operates with an input voltage range from 1.8 V
to 5.6 V, thus allowing it to be supplied from the
output of the step-down converter or directly from the
system voltage.
The TPS65720, TPS657201, and TPS657202 come
in a small 25-ball 2-mm × 2-mm wafer chip scale
package (DSBGA) with 0.4-mm ball pitch or a
4-mm × 4-mm WQFN package with a 0.4-mm pitch
(TPS65721).
Device Information
PART NUMBER
DSBGA (25)
2.11 mm × 2.11 mm
TPS65721
WQFN (32)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
TPS65720
BAT
BAT
AC
2 Applications
Bluetooth Headsets
Handheld Equipment
Wearables, Smart Watches
Portable Accessories
ISET
Charger and
Power Path
10kΩ
TS
The TPS6572x device is a small power management
unit targeted for Bluetooth headsets or other portable
low-power consumer-end equipments. The device
contains an USB friendly Lithium-Ion battery charger,
a highly efficient step-down converter, a low-dropout
linear regulator, and additional supporting functions.
The device is controlled by an I2C interface. Several
settings can be customized by the use of nonvolatile
memory which is factory programmed.
The 2.25-MHz step-down converter enters a lowpower mode at light load for maximum efficiency
across the widest possible range of load currents. For
low-noise applications the devices can be forced into
fixed-frequency PWM mode using the I2C-compatible
interface.
LiIon
NTC
SYS
SYS
R5
L1
DCDC1
200 mA
SYS
4.7 µF / 6.3 V
2.2 µH
ON
or
OFF
4.7 µF
22pF
R2
150 kΩ
VINLDO1
PB_IN
VDCDC1 = 2.05 V
R1
360 kΩ
FB_DCDC1
R6
3 Description
BODY SIZE (NOM)
TPS65720x
1 µF
•
•
•
•
PACKAGE
(1)
Bluetooth
Chip
2.2 µF
LDO1
200 mA
VLDO1 = 1.85 V
VLDO1
2 × 100 kΩ
AGND
GPIO0
GPIO1
GPIO2
GPIO3
Indication
LEDs
Reset Generator
and Startup Logic
GPIO or
5-mA
Current
Sink
2
IC
Interface
Vin
4.7 µF / 4 V
PGND
RESET
INT
2×
3.3 kΩ
Reset
INT
HOLD_LDO1
HOLD_DCDC1
GPIO
SCLK
SDAT
SCLK
SDAT
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Dissipation Ratings ................................................. 14
Timing Requirements .............................................. 14
Switching Characteristics ........................................ 15
Typical Characteristics ............................................ 16
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagrams ..................................... 18
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 30
8.5 Programming........................................................... 31
8.6 Register Maps ......................................................... 33
9
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application ................................................. 47
10 Power Supply Recommendations ..................... 56
11 Layout................................................................... 56
11.1 Layout Guidelines ................................................. 56
11.2 Layout Example .................................................... 56
12 Device and Documentation Support ................. 57
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
57
57
57
57
57
57
58
58
13 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2016) to Revision C
Page
•
Changed the title of the data sheet ........................................................................................................................................ 1
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 57
Changes from Revision A (September 2015) to Revision B
Page
•
Changed Timer Fault, To: Charger Fault, and Bit = 1 To: Bit = 1 .................................. 24
•
IRMASK0 Register Address: 0Dh (read/write) , Changed B4 From: M_TIMER_FAULT To: Reserved .............................. 44
•
IR0 Register Address: 10h (read only) , Changed B4 From: TIMER_FAULT To: Reserved ............................................... 45
•
IR0 Register Address: 10h (read only) , Changed B4 From: Rising edge of TIMER_FAULT To: Reserved....................... 45
Changes from Original (October 2009) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added the TPS657202 and the TPS65721 devices to the data sheet................................................................................... 1
2
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
5 Device Options
PART NUMBER (1)
(1)
SIZE FOR DSBGA PACKAGE
OPTION
TPS65720
D = 2105 μm ±25 μm
E = 2105 μm ±25 μm
DCDC1 externally adjustable
LDO1 default 1.85 V
AC input current limit = 500 mA
TPS657201
D = 2105 μm ±25 μm
E = 2105 μm ±25 μm
DCDC1 default 1.85 V
LDO1 default 1.85 V
analog multiplexer (TS_OUT)
AC input current limit = 500 mA
TPS657202
D = 2105 μm ±25 μm
E = 2105 μm ±25 μm
DCDC1 default 1.90 V
LDO1 default 2.85 V
analog multiplexer (TS_OUT)
AC input current limit = 100 mA
TPS65721
—
DCDC1 externally adjustable
LDO1 externally adjustable
AC input current limit = 500 mA
The RSN and YFF package is available in tape and reel. Add R suffix (TPS65720YFFR; TPS65721RSNR) to order quantities of 3000
parts per reel. Add T suffix (TPS65720YFFT; TPS65721RSNT) to order quantities of 250 parts per reel.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
3
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
6 Pin Configuration and Functions
YFF Package
25-Pin DSBGA
Bottom View
AC
ISET
RESET
SDAT
SCLK
A5
SYS
SYS
PB_IN
GPIO0
GPIO1
A4
BAT
BAT
GPIO2
INT
GPIO3
A3
HOLD_
DCDC1
L1
TS
HOLD_
LDO1
GND
A2
FB_
DCDC1
PGND
E1
AGND
D1
VINLDO1
C1
VLDO1
B1
A1
Pin Functions—DSBGA (TPS65720)
PIN
I/O
NO.
DESCRIPTION
NAME
A1
VLDO1
O
Output voltage of LDO1
A2
HOLD_LDO1
I
Power-on input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released HIGH.
A3
GPIO3
I/O
General purpose I/O or 5-mA current sink
A4
GPIO1
I/O
General purpose I/O
A5
SCLK
I
Clock input for the I2C interface
B1
VINLDO1
I
Input voltage for LDO1
B2
GND
—
Connect to AGND and PGND
B3
GPIO2
I/O
General purpose I/O or 5-mA current sink
B4
GPIO0
I/O
General purpose I/O
B5
SDAT
I/O
Data line for the I2C interface
C1
AGND
—
Analog ground
C2
TS
I
Connect a thermistor from this pin to GND for battery temperature
C3
INT
O
Open-drain interrupt output
C4
PB_IN
I
Push button input; Turns on DCDC1 and LDO1 if pulled to GND.
C5
RESET
O
Open-drain output of the reset generator; This output goes active LOW when the output voltage of LDO1 falls 8% below its target
voltage.
D1
FB_DCDC1
I
Feedback input of step-down converter
D2
HOLD_DCDC1
I
Power-On input for DCDC1 converter. When pulled HIGH, the DC-DC converter is kept enabled after PB_IN was released HIGH.
D3
BAT
I/O
Connect to battery + terminal
D4
SYS
O
System voltage; output of the power path manager. Power input for step-down converter DCDC1
D5
ISET
I
Connect a resistor from this pin to GND to set fast charge current
E1
PGND
—
Power ground
E2
L1
O
Switch output of step-down converter
E3
BAT
I/O
Connect to battery + terminal
E4
SYS
O
System voltage; output of the power path manager. Power input for step-down converter DCDC1
E5
AC
I
Input power for power manager, connect to external DC supply.
4
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
YFF Package
25-Pin DSBGA
Bottom View
AC
ISET
RESET
SDAT
SCLK
A5
SYS
SYS
PB_IN
GPIO0
GPIO1
A4
BAT
BAT
GPIO2
INT
GPIO3
A3
HOLD_
DCDC1
L1
TS
HOLD_
LDO1
TS_OUT
A2
FB_
DCDC1
PGND
E1
AGND
D1
VINLDO1
C1
VLDO1
B1
A1
Pin Functions—DSBGA (TPS657201, TPS657202)
PIN
I/O
NO.
DESCRIPTION
NAME
A1
VLDO1
O
Output voltage of LDO1
A2
HOLD_LDO1
I
Power-on input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released HIGH.
A3
GPIO3
I/O
General purpose I/O or 5-mA current sink
A4
GPIO1
I/O
General purpose I/O
A5
SCLK
I
Clock input for the I2C interface
B1
VINLDO1
I
Input voltage for LDO1
B2
VBAT/TS_OUT
O
Output of battery temperature and battery voltage monitor
B3
GPIO2
I/O
General purpose I/O or 5-mA current sink
B4
GPIO0
I/O
General purpose I/O
B5
SDAT
I/O
Data line for the I2C interface
C1
AGND
—
Analog ground
C2
TS
I
Connect a thermistor from this pin to GND for battery temperature
C3
INT
O
Open-drain interrupt output
C4
PB_IN
I
Push button input; Turns on DCDC1 and LDO1 if pulled to GND.
C5
RESET
O
Open-drain output of the reset generator; This output goes active LOW when the output voltage of LDO1 falls 8% below its target
voltage.
D1
FB_DCDC1
I
Feedback input of step-down converter
D2
HOLD_DCDC1
I
Power-on input for DCDC1 converter. When pulled HIGH, the DC-DC converter is kept enabled after PB_IN was released HIGH.
D3
BAT
I/O
Connect to battery + terminal
D4
SYS
O
System voltage; output of the power path manager. Power input for step-down converter DCDC1
D5
ISET
I
Connect a resistor from this pin to GND to set fast charge current
E1
PGND
—
Power ground
E2
L1
O
Switch output of step-down converter
E3
BAT
I/O
Connect to battery + terminal
E4
SYS
O
System voltage; output of the power path manager. Power input for step-down converter DCDC1
E5
AC
I
Input power for power manager, connect to external DC supply.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
5
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
AC
AC
SYS
SY S
BAT
BAT
L1
P GN D
RSN Package
32-Pin WQFN With Thermal Pad
Top View
24 23 22 21 20 19 18 17
HOLD_DCDC1
FB_DCDC1
TS
AGND
GND
VINLDO1
VLDO1
NC
25
26
27
28
29
30
31
32
TPS65721
16
15
14
13
12
11
10
9
ISET
PB_IN
RESET
INT
SDAT
MODE
NC
NC
FB_LDO1
HOLD_LDO1
THRESHOLD
GPIO3
GPIO2
GPIO1
GPIO0
SCLK
1 2 3 4 5 6 7 8
Pin Functions—WQFN (TPS65721)
PIN
NAME
NO.
AC
17, 18
AGND
BAT
FB_DCDC1
I/O
I
DESCRIPTION
Input power for power manager, connect to external DC supply.
28
—
Analog ground
21, 22
I/O
Connect to battery + terminal
26
I
Feedback input of step-down converter
Feedback input for LDO1
FB_LDO1
1
I
GND
29
—
Connect to AGND and PGND
GPIO0
7
I/O
General purpose I/O
GPIO1
6
I/O
General purpose I/O
GPIO2
5
I/O
General purpose I/O or 5-mA current source
GPIO3
4
I/O
General purpose I/O or 5-mA current source
HOLD_DCDC1
25
I
Power-on input for DCDC1 converter. When pulled HIGH, the DC-DC converter is kept enabled
after PB_IN was released HIGH.
HOLD_LDO1
2
I
Power-on input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released
HIGH.
INT
13
O
Open-drain interrupt output
ISET
16
I
Connect a resistor from this pin to GND to set fast charge current
L1
23
O
Switch output of step-down converter
MODE
11
I
Pull HIGH to force the DCDC1 converter to PWM mode.
PB_IN
15
I
Push button input; Turns on DCDC1 and LDO1 if pulled to GND.
PGND
24
—
Power ground
RESET
14
O
Open-drain output of the reset generator; This output goes active LOW when the input voltage at
pin THRESHOLD falls below the threshold voltage.
SCLK
8
I
Clock input for the I2C interface
SDAT
12
I/O
Data line for the I2C interface
19, 20
O
System voltage; output of the power path manager. Power input for step-down converter DCDC1
THRESHOLD
3
I
Input voltage to the reset comparator. When the input voltage falls below the threshold, the RESET
output is actively pulled LOW.
TS
27
I
Connect a thermistor from this pin to GND for battery temperature
VINLDO1
30
I
Input voltage for LDO1
VLDO1
31
O
Output voltage from LDO1
ThermalPad
—
—
Connect to GND
SYS
6
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
All pins except A/PGND, AC, GPIOx pins with respect to AGND
–0.3
7
V
GPIOx pins with respect to AGND
–0.3
VSYS
V
AC pin with respect to AGND
–0.3
28
V
–0.3
3.6
V
AC, BAT, SYS, L1, VLDO1, VINLDO1, PGND
600
mA
GPIOx, AGND
20
mA
All other pins
3
mA
Voltage range on pin VLDO1, FB_LDO1, TS_OUT, TS with respect to AGND
Current
Continuous total power dissipation
See Dissipation Ratings
Operating free-air temperature, TA
–40
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
85
°C
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
UNIT
±2000
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VAC
Input voltage at AC pin
VSYS
Voltage at SYS pin
IINUSB
NOM
MAX
UNIT
4.35
28
2.2
5.6
V
Input current at AC
500
mA
IOUTSYS
Output current at SYS
400
mA
IBAT
Average current into and out of BAT pin
300
mA
VINDCDC1
Input voltage for step-down converter DCDC1
2.3
5.6
V
VDCDC1
Output voltage for DCDC1 step-down converter; externally adjustable
0.6
VINDCDC1
IOUTDCDC1
Output current at L
L
Inductor at L (1)
2.2
VINLDO1
Input voltage for LDO1
1.8
VLDO1
Output voltage for LDO1
0.8
ILDO1
Output current at LDO1
CINAC
Input capacitor at AC (1)
3.3
V
V
400
mA
4.7
μH
VSYS
V
3.3
V
200
mA
0.1
1
μF
CBAT
Capacitor at BAT
(1)
0.1
4.7
μF
CSYS
Capacitor at SYS (1)
4.7
10
μF
CINDCDC1
Input capacitor at VINDCDC1 (1); if connected to SYS, only one 4.7-μF capacitor
required for SYS and CINDCDC1
4.7
COUTDCDC1
Output capacitor at VDCDC1 (1)
4.7
CINLDO1
Input capacitor at VINLDO1 (1)
2.2
μF
COUTLDO1
Output capacitor at LDO1 (1)
2.2
μF
(1)
μF
10
22
μF
See Application and Implementation for more details.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
7
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
RISET
Minimum RISET value for proper operation; lower values may trigger the short circuit
protection on ISET
700
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
Ω
7.4 Thermal Information
THERMAL METRIC
(1)
TPS65720
TPS65721
YFF (DSBGA)
RSN (WQFN)
25 PINS
32 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
60.9
37.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
28.2
°C/W
RθJB
Junction-to-board thermal resistance
11.3
8.6
°C/W
ψJT
Junction-to-top characterization parameter
1.4
0.3
°C/W
ψJB
Junction-to-board characterization parameter
11.3
8.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DCDC1 enabled, IOUT = 0 mA. PFM mode enabled; device not
switching
36
45
DCDC1 enabled, IOUT = 0 mA. PWM mode
2.8
Current into BAT pin (PFM mode)
33
50
μA
Current into VINLDO1
13
18
μA
SUPPLY CURRENT
IQ
Operating quiescent current when
only DCDC1 converter is enabled
IQ
Operating quiescent current when
LDO1 and DCDC1 are enabled
ISD
μA
mA
Shutdown current after voltage was
applied to BAT but device never
enabled before (shipping mode)
For VINLDO1 = 0 V (LDO1 supplied by DCDC1); powered by
VBAT = 3.6 V
4
13
μA
Shutdown current after first powerup
For VINLDO1 = 0 V (LDO1 supplied by DCDC1); powered by
VBAT = 3.6 V
12
17
μA
Shutdown current after first powerup
For VINLDO1 ≠ 0 V (LDO1 supplied by SYS); powered by VBAT
= 3.6 V
12
18
μA
SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD
VIH
High-level input voltage for SCLK,
SDAT, GPIOx, HOLD_DCDC1,
HOLD_LDO1, PB_IN
GPIOs configured as input
1.2
VSYS
V
VIL
Low-level input voltage for SCLK,
SDAT, GPIOx, HOLD_DCDC1,
HOLD_LDO1, PB_IN
GPIOs configured as input
0
0.4
V
VOL
Low-level output voltage for SDAT,
GPIOx, INT, RESET
GPIOs configured as output; Io = 1 mA; no internal pull-up
0
0.4
V
Sink current for GPIO2, GPIO3
GPIO2, GPIO3 configured as current sink; VOL = 0.4 V ;
for TJ = 0°C to 85°C
Sink current for GPIOx
GPIOx configured as open-drain output ; output = LOW
Minimum voltage for proper current
regulation from GPIO2 or GPIO3 to
GND if programmed as a current
sink
IO = 5 mA; current sink turned on
IOL
VOL
VRESET-falling
LDO1 out of regulation reset
voltage
VRESET-rising
–20%
Falling edge; RESET is asserted LOW for TPS65720,
TPS657201, TPS657202
mA
3
mA
V
VLDO1, nom13%
Rising edge; RESET is released HIGH for TPS65720,
TPS657201, TPS657202 after TRESET
VLDO1,
nom-7%
VLDO1,
nom-4%
Threshold voltage for reset input
Falling voltage; WQFN package only
VTHRESHOLD_hys
Hysteresis on THRESHOLD
Rising voltage; WQFN package only
ILKG
Input leakage current
PB_IN, SDAT, SCLK, GPIOx configured as output, INT, RESET,
output high impedance
Submit Documentation Feedback
20%
0.4
VTHRESHOLD_down
8
5
–3%
570
V
V
3%
30
mV
mV
0.2
μA
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Electrical Characteristics (continued)
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.2
2.25
UNIT
STEP-DOWN CONVERTER
VSYS
Input voltage for DCDC1
UVLO
Internal undervoltage lockout
threshold hysteresis
2.3
VSYS falling
2.15
5.6
V
V
VSYS rising
120
mV
VSYS = VINDCDC1 = 3.6 V, YFF package
350
600
VSYS = VINDCDC1 = 3.6 V, RSN package
400
650
1
μA
VINDCDC1/2 = 3.6 V, YFF package
300
500
mΩ
VINDCDC1/2 = 3.6 V, RSN package
350
550
mΩ
POWER SWITCH
RDS(ON)
High-side MOSFET ON-resistance
ILK_HS
High-side MOSFET leakage current
mΩ
VDS = 5.6 V
RDS(ON)
Low-side MOSFET ON-resistance
ILK_LS
Low-side MOSFET leakage current
VDS = 5.6 V
Forward current limit high-side and
low-side MOSFET
2.3 V ≤ VIN ≤ 5.6 V, TPS65720
425
2.3 V ≤ VIN ≤ 5.6 V, TPS65721, TPS657201, TPS657202
625
ILIMF
IO
DC output current
1
μA
600
775
mA
850
1150
mA
VSYS > 2.7 V; TPS65720
200
VSYS > 2.7 V; TPS65721, TPS657201, TPS657202
400
mA
OUTPUT
VOUT
Output voltage range
VFB
Feedback voltage
0.6
Vin
V
0.6
V
VOUT
Default output voltage for
TPS657201
1.85
V
VOUT
Default output voltage for
TPS657202
1.90
V
IFB
FB pin input current for externally
adjustable version
External resistor-divider
IFB
FB pin input current for TPS657201,
TPS657202
Internal resistor-divider
DC output voltage accuracy
for TPS65720, TPS65721
(1)
VOUT
VIN = 2.3 V to 5.6 V; PFM operation, 0 mA < IOUT < IOUTMAX
DC output voltage load regulation
PWM operation
VPGOOD-falling
PGOOD threshold at falling output
voltage
is set to 1
VPGOOD-rising
PGOOD threshold at rising output
voltage
is set to 0
Internal discharge resistor at L
DCDC1 disabled; the discharge function can be disabled as an
EEPROM option
RDIS
1%
VIN = 2.3 V to 5.6 V, PWM operation, 0 mA < IOUT < IOUTMAX
–2%
0.1
μA
5
μA
3%
2%
0.5
VDCDC1,
nom-14%
300
%/A
VDCDC1,
nom-7%
V
VDCDC1,
nom-5%
V
400
Ω
THERMAL PROTECTION FOR DCDC1 AND LDO1
TSD
(1)
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
30
°C
Output voltage specification does not include tolerance of external voltage programming resistors.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
9
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Electrical Characteristics (continued)
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 LOW DROPOUT REGULATOR
VINLDO
Input voltage range for LDO1
1.8
5.6
V
VLDO1
LDO1 output voltage range
0.8
3.3
V
VLDO1
LDO1 output voltage
Default output voltage for TPS65720, TPS657201
1.85
V
VLDO1
LDO1 output voltage
Default output voltage for TPS657202
2.85
V
VFB_LDO1
Feedback voltage
Externally adjustable version only: TPS65721
IFB_LDO1
FB pin input current
IO
Output current for LDO1
ISC
LDO1 short circuit current limit
VLDO1 = GND; VINLDO1 = 2.05 V
Dropout voltage at LDO1, YFF
package
IO = 200 mA, VINLDO = 2.05 V
Dropout voltage at LDO1, RSN
package
IO = 200 mA, VINLDO = 2.05 V
Output voltage accuracy for LDO1
IO = 200 mA
–1.5%
2.5%
Line regulation for LDO1
VINLDO1 = VLDO1 + 0.5 V (min. 1.8 V) to 5.6 V (VSYS),
IO = 50 mA
–1%
1%
Load regulation for LDO1
IO = 0 mA to 200 mA for LDO1
–1%
2%
Internal discharge resistor at
VLDO1
LDO disabled, discharge function per default disabled in register
RDIS
0.8
350
V
0.1
μA
200
mA
500
mA
180
mV
120
250
mV
Ω
400
BATTERY VOLTAGE AND BATTERY TEMPERATURE MONITOR WITH MULTIPLEXER; INTERNAL BATTERY VOLTAGE COMPARATOR
VTS
Input voltage range on TS pin for
full scale output on pin TS_OUT
(0 V to 1.4 V)
VBAT
Input voltage range on BAT pin for
full scale output on pin TS_OUT
(0 V to 1.4 V)
VTS_OUT
Output voltage range on pin
TS_OUT
ITS_OUT = 0 mA
Equals –20°C to 60°C on a 10k NTC
Offset error on pin TS_OUT
In temperature-sense mode; VO with Vbat = 2.2 V
Slew rate
VTS_OUT; 0 V to 1.4 V
ITS_OUT_SC
Short circuit current
1.4
V
2.2
4.5
V
0
1.4
0.06
1.4
V
0 < ITS_OUT < 0.05 mA
SR
0
±7.5
1
mV
V/ms
0.1
mA
Load capacitance
Maximum capacitance at TS_OUT
Battery voltage comparator
threshold voltage
Depending on Bits , ; falling voltage
Battery voltage comparator
threshold voltage hysteresis
Rising voltage
Offset
TJ = 10°C to 35°; for V(TS) ≥ 0.2 V
–22
22
mV
Gain error
TJ = 10°C to 35°; for V(TS) ≥ 0.2 V
–11
11
mV
Offset
TJ = –40°C to 85°C; for V(TS) ≥ 0.2 V
–30
30
mV
Gain error
TJ = –40°C to 85°C; for V(TS) ≥ 0.2 V
–14
14
mV
Internal TS resistor (for 10k NTC,
B=3380)
TJ = 25°C
–1.5%
29.23
1.5%
kΩ
Internal TS resistor (for 100k NTC)
TJ = 25°C
–1.5%
292.3
1.5%
kΩ
Internal TS resistor temperature
drift
TJ = –40°C to 85°C
Internal V2V0 reference voltage
TJ = –40°C to 85°C
1.2%
V
–3%
100
pF
3%
V
200
mV
ACCURACY
VBAT MODE
TS MODE
10
Submit Documentation Feedback
–4.5%
–1.2%
2
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Electrical Characteristics (continued)
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3
3.45
V
300
mV
140
mV
POWER PATH
VUVLO
Undervoltage lockout
VAC: 0 V → 4 V
3.2
VHYS-UVLO
Hysteresis on UVLO
VAC: 4 V → 0 V
200
VIN-DT
Input power detection threshold
(Input power detected if VIN > VBAT + VIN-DT) VBAT = 3.6 V,
VIN: 3.5 V → 4 V
40
VHYS-INDT
Hysteresis on VIN-DT
VBAT = 3.6 V, VIN: 4 V → 3.5 V
20
VOVP
Input overvoltage protection
threshold
VAC: 5 V → 7 V
6.4
VHYS-OVP
Hysteresis on OVP
VAC: 11 V → 5 V
105
ISYS = 0.3 A, VAC = 4.35 V, VBAT = 4.2 V; YFF package
170
285
mV
VDO(AC-SYS)
AC pin to SYS pin dropout voltage
VAC – VSYS
ISYS = 0.3 A, VAC = 4.35 V, VBAT = 4.2 V; RSN package
210
325
mV
Battery to SYS pin dropout voltage
VBAT – VSYS
ISYS = 0.2 A, VAC = 0 V, VBAT > 3 V; YFF package
80
mV
ISYS = 0.2 A, VAC = 0 V, VBAT > 3 V; RSN package
120
mV
VDO(BAT-SYS)
VSYS(REG)
SYS pin voltage regulation
selectable register
Bits ;
80
mV
6.6
6.8
V
mV
00: VAC > VSYS + VDO(AC-SYS), VBAT < 3.3V
–5%
3.4
5%
00: VAC > VSYS + VDO(AC-SYS), VBAT ≥ 3.3 V
–5%
VBAT +
200 mV
5%
01: VAC > VSYS + VDO(AC-SYS)
–5%
4.4
5%
10: VAC > VSYS + VDO(AC-SYS)
–5%
5.0
5%
11: VAC > VSYS + VDO(AC-SYS)
–5%
5.5
5%
90
95
100
Bit = 00
IAC-MAX
Maximum Input Current Register
Bit < AC input current1, AC input current0> = 01 or 10
450
475
500
VAC-LOW
Input voltage threshold when input
current is reduced
Input current is reduced if voltage at AC falls below VAC-LOW to
keep the AC voltage above 4.5 V
4.35
4.5
4.65
Output voltage threshold when
charging current is reduced
Bit = 1
VDPM
VO(REG) –
100 mV
Register
Bit = 0
4.3
V
mA
V
V
VBSUP1
Enter battery supplement mode
VOUT ≤
VBAT –
40 mV
V
VBSUP2
Exit battery supplement mode
VOUT ≥
VBAT –
20 mV
V
VO(SC1)
Output short-circuit detection
threshold, power-on
0.8
0.9
1
VO(SC2)
Output short-circuit detection
threshold, supplement mode
VBAT – VOUT > VO(SC2) indicates
short-circuit
200
250
300
mV
80
μA
V
BATTERY CHARGER
QUIESCENT CURRENT
IIACSTDBY)
Standby current into AC pin
ICC
Active supply current, AC pin
IBAT(SC)
Source current for BAT pin shortcircuit detection
VBAT(SC)
BAT pin short-circuit detection
threshold
Vo(BATREG)
VLOWV
VIN = 5 V; ACinputcurrent[1,0] = 11
60
VIN = 28 V; ACinputcurrent[1,0] = 11
Battery charger voltage
VIN = 5 V, no load on DCDC1, LDO1, SYS pin, VSYS[1,0] = 11;
ACinputcurrent[1,0] = 10; CH_EN = 0
Depending on setting in CHGCONFIG3 And internal EEPROM
Default = 4.2 V
Precharge to fast-charge transition
threshold
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
530
μA
2
mA
4
7.5
11
mA
1.6
1.8
2.0
V
–1%
4.15
1%
–1%
4.175
1%
–1%
4.20
1%
–1%
4.225
1%
–1%
4.25
1%
–1%
4.275
1%
–1%
4.30
1%
–1%
4.325
1%
2.9
3.0
3.1
V
Submit Documentation Feedback
V
11
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Electrical Characteristics (continued)
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENT (continued)
Maximum battery fast charge
current
ICHG
IPRECHG
ITERM
10
VBAT > VLOWV, VIN = 5 V, IIN-MAX > ICHG, No load on SYS pin,
thermal loop not active, DPPM loop not active
KISET / RISET
mA
A
at 300 mA for ICH_SCL[1,0] = 11 (charge current scaling is
100% of ISET value)
–15%
450
15%
at 40 mA for ICH_SCL[1,0] = 11 (charge current scaling is 100%
of ISET value)
–20%
450
20%
at 225 mA range for ICH_SCL[1,0] = 10 (charge current scaling
is 75% of ISET value)
–15%
338
15%
at 30 mA for ICH_SCL[1,0] = 10 (charge current scaling is 75%
of ISET value)
–20%
338
20%
at 150 mA for ICH_SCL[1,0] = 01 (charge current scaling is 50%
of ISET value)
–10%
225
10%
at 20 mA for ICH_SCL[1,0] = 01 (charge current scaling is 50%
of ISET value)
–15%
225
15%
at 75 mA for ICH_SCL[1,0] = 00 (charge current scaling is 25%
of ISET value)
–10%
112
10%
at 10 mA for ICH_SCL[1,0] = 00 (charge current scaling is 25%
of ISET value)
Fast charge current factor
AΩ
–20%
112
20%
for I_PRE[1,0] = 11 (pre-charge current scaling is 20% of charge
current)
0.15 × ICHG
0.2 × ICHG
0.25 × ICHG
for I_PRE[1,0] = 10 (pre-charge current scaling is 15% of charge
current)
0.11 × ICHG
0.15 × ICHG
0.19 × ICHG
for I_PRE[1,0] = 01 (pre-charge current scaling is 10% of charge
current)
0.07 × ICHG
0.1 × ICHG
0.13 × ICHG
for I_PRE[1,0] = 00 (pre-charge current scaling is 5% of charge
current)
0.03 × ICHG
0.05 × ICHG
0.08 × ICHG
for I_TERM[1,0] = 11 (termination current is 20% of charge
current)
0.15 × ICHG
0.2 × ICHG
0.27 × ICHG
for I_TERM[1,0] = 10 (termination current is 15% of charge
current)
0.11 × ICHG
0.15 × ICHG
0.21 × ICHG
for I_TERM[1,0] = 01 (termination current is 10% of charge
current)
0.07 × ICHG
0.1 × ICHG
0.15 × ICHG
for I_TERM[1,0] = 00 (termination current is 5% of charge
current)
0.03 × ICHG
0.05 × ICHG
0.08 × ICHG
165
100
60
mV
5
7.5
10
mA
–35%
5
35%
h
–35%
30
35%
min
Precharge current
Charge current value for termination
detection threshold (internally set)
VRCH
Recharge detection threshold
IBAT(DET)
Sink current for battery detection
Voltage below nominal charger voltage
TCHG
Charge safety timer
Safety timer range selectable by I2C; default setting without
DPPM or thermal loop active
TPRECHG
Pre-charge timer
Pre-charge timer range; default setting
12
mA
Minimum battery fast charge current
Battery fast charge current set
factor
KISET
300
VBAT(REG) > VBAT > VLOWV, VIN = VAC or VUSB = 5 V
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Electrical Characteristics (continued)
VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to
85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thermistor high temperature
detection resistance (equals 45°C
for 10-kΩ NTC; B = 3380)
4.3
5
5.7
kΩ
Thermistor high temperature
detection resistance (equals 50°C
for 10-kΩ NTC; B = 3380)
3.5
4.1
4.8
kΩ
Thermistor high temperature
detection resistance (equals 55°C
for 10-kΩ NTC; B = 3380 )
2.9
3.5
4.2
kΩ
2.4
3
3.5
kΩ
43
50
57
kΩ
Thermistor high temperature
detection resistance (equals 50°C
for 100-kΩ NTC)
35
41
48
kΩ
Thermistor high temperature
detection resistance (equals 55°C
for 100-kΩ NTC)
29
35
42
kΩ
Thermistor high temperature
detection resistance (equals 60°C
for 100-kΩ NTC)
24
30
35
kΩ
Thermistor low temperature
detection resistance (equals 0°C for
10-kΩ NTC; B = 3380)
25
27
30
kΩ
Thermistor low temperature
detection resistance (equals 5°C for
10-kΩ NTC; B = 3380)
20
22
24
kΩ
Thermistor low temperature
detection resistance (equals 10°C
for 10-kΩ NTC; B = 3380 )
16
18
20
kΩ
13
15
16
kΩ
250
270
300
kΩ
Thermistor low temperature
detection resistance (equals 5°C for
100-kΩ NTC)
200
220
240
kΩ
Thermistor low temperature
detection resistance (equals 10°C
for 100-kΩ NTC)
160
180
200
kΩ
Thermistor low temperature
detection resistance (equals 15°C
for 100-kΩ NTC)
130
150
160
kΩ
BATTERY-PACK NTC MONITOR
Thermistor high temperature
detection resistance (equals 60°C
for 10-kΩ NTC; B = 3380)
RNTCHOT
Thermistor high temperature
detection resistance (equals 45°C
for 100-kΩ NTC)
Thermistor low temperature
detection resistance (equals 15°C
for 10-kΩ NTC; B = 3380)
RNTCCOLD
VHYS(COLD)
Thermistor low temperature
detection resistance (equals 0°C for
100-kΩ NTC)
Low temperature trip point
hysteresis
Thermistor not detected for 10k
NTC
RNOSENSOR
Thermistor not detected for 100k
NTC
Hot temperature detected and charging suspended when the
resistance of the battery-NTC is lower than RNTCHOT
Cold temperature detected and charging suspended when the
resistance of the battery-NTC is higher than RNTCCOLD
For 10-kΩ NTC; B = 3380
Hot temperature detected and charging suspended when the
resistance of the battery-NTC is higher than RNOSENSOR
5
°C
260
340
620
kΩ
2500
3400
6200
kΩ
THERMAL REGULATION
TJ(REG)
Lower Temperature regulation limit
115
°C
TJ(REG)
Upper Temperature regulation limit
135
°C
TJ(OFF)
Thermal shutdown temperature
155
°C
TJ(OFF-HYS)
Thermal shutdown hysteresis
20
°C
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
13
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
7.6 Dissipation Ratings
See
(1)
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
YFF
55 K/W
1.8 W
RSN
38 K/W
2.6 W
(1)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
18 mW/K
1W
0.7 W
26 mW/K
1.4 W
1W
The thermal resistance was measured on a high K board.
7.7 Timing Requirements
MIN
NOM
MAX UNIT
Low to high transition of RESET pin, Bit
RESET_DELAY = 0
9
11
13
Low to high transition of RESET pin, Bit
RESET_DELAY = 1
70
90
110
RESET and PB_IN
TRESET
Reset delay time on pin RESET
ms
HIGH to LOW transition of RESET pin RESET
will go low by HOLD pin going LOW AND HOLD
Bit set to 0 OR voltage at Vreset falling below the
threshold
Tdebounce
Debounce time at PB_IN
Rising and falling voltage
10
39
50
μs
60
ms
POWER OUTPUTS, DCDC1 and LDO1
tStart
DCDC1 Start-up time
Time from active EN to Start switching
170
μs
tRamp
DCDC1 VOUT ramp time
Time to ramp from 5% to 95% of VOUT
250
μs
LDO1 PGOOD debounce time
Internal PGOOD comparator at VOUTLDO1 is
debounced by
80
μs
LDO1 VOUT Ramp time
Internal soft-start when LDO is enabled;
Time to ramp from 5% to 95% of VOUT
250
μs
2
ms
50
μs
2
ms
250
μs
tRamp
POWER PATH
tDGL(PGOOD)
Deglitch time, input power
detected status
tBLK(OVP)
Input overvoltage blanking time
Time measured from VIN: 0 V → 5 V 1 μs
rise time to PGOOD = LO
Time measured from VAC: 11 V → 5 V 1 μs
fall time to = 0
tREC(OVP)
Input overvoltage recovery time
tDGL(SC2)
Output short-circuit detection
deglitch time, supplement mode
short circuit
VBAT – VOUT > VO(SC2) indicates
short-circuit
tREC(SC2)
Recovery time, supplement mode
short circuit
60
ms
tDGL1(LOWV)
Deglitch time on pre-charge to
fast-charge transition
25
ms
tDGL2(LOWV)
Deglitch time on fast-charge to
pre-charge transition
25
ms
tDGL(TERM)
Deglitch time, termination detected
25
ms
tDGL(RCH)
Deglitch time, recharge threshold
detected
62.5
ms
tDGL(NO-IN)
Delay time, input power loss to
charger turn-off
20
ms
tDET
Battery detection timer
250
ms
50
ms
CHARGER
VBAT = 3.6 V. Time measured from VIN: 5 V →
3.3 V 1 μs fall time
BATTERY PACK MONITOR
tDGL(TS)
Deglitch time, pack temperature
fault detection
tSW(VBAT-TS)
MUX switching time
14
Submit Documentation Feedback
Bit toggles
1
ms
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Timing Requirements (continued)
MIN
NOM
MAX UNIT
I2C COMMUNICATION
fMAX
Clock frequency
400
kHz
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
300
ns
tF
DATA and CLK fall time
300
ns
th(STA)
Hold time (repeated) START
condition (after this period the first
clock pulse is generated)
600
ns
th(DATA)
Setup time for repeated START
condition
600
ns
th(DATA)
Data input hold time
tsu(DATA)
Data input setup time
tsu(STO)
STOP condition setup time
t(BUF)
Bus free time
ns
ns
0
ns
100
ns
600
ns
1300
ns
7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fSW
TEST CONDITIONS
DCDC1 Switching frequency
MIN
TYP
MAX
UNIT
2.03
2.25
2.48
MHz
DATA
t(BUF)
th(STA)
t(LOW)
tr
tf
CLK
th(STA)
t(HIGH)
th(DATA)
STO
STA
tsu(STA)
tsu(DATA)
tsu(STO)
STA
STO
Figure 1. Serial I/f Timing Diagram
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
15
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
7.9 Typical Characteristics
The graphs have been generated on the TPS65720YFF EVM with the inductors as mentioned in the graphs. See the
TPS65720EVM User's Guide (SLVU324) for details on the layout.
Table 1. Table Of Graphs
FIGURE
Scope plot using TPS65720 (battery
powered) for
PB_IN; Vo_DCDC1; Vo_LDO1
Startup DCDC1 and LDO1
Figure 2
Figure 3, Figure 4,
Figure 5, Figure 6
KISET vs RISET
150
VILDO = VODCDC,
IODCDC = 200 mA
VIbat = 3.6 V
145
TA = 25°C
1 V/div
140
KISET - AW
135
VODCDC = 2.05 V
1 V/div
TA = -40°C
TA = 85°C
130
125
120
VOLDO = 1.85 V
115
1 V/div
110
Time - 200 ms/div
0
4000
8000
12000
RISET - W
16000
20000
24000
Figure 3. KISET vs RISET; ICH_SCL[1,0] = 00
Figure 2. Start-Up DCDC1 and LDO1
395
260
TA = 25°C
390
255
TA = -40°C
385
380
TA = 25°C
TA = -40°C
KISET - AW
KISET - AW
250
245
TA = 85°C
375
TA = 85°C
370
365
240
360
355
235
350
230
345
0
4000
8000
12000
RISET - W
16000
20000
Figure 4. KISET vs RISET; ICH_SCL[1,0] = 01
16
Submit Documentation Feedback
24000
0
4000
8000
12000
RISET - W
16000
20000
24000
Figure 5. KISET vs RISET; ICH_SCL[1,0] = 10
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
505
500
TA = -40°C
495
TA = 25°C
KISET - AW
490
485
TA = 85°C
480
475
470
465
460
0
4000
8000
12000
RISET - W
16000
20000
24000
Figure 6. KISET vs RISET; ICH_SCL[1,0] = 11
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
17
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8 Detailed Description
8.1 Overview
The TPS6572x device has a battery charger, DC-DC, and LDO that compliment most small low-power products
such as wearables, accessories, and MCU systems. In addition to the power delivery the device has I2C
communication, push button, RESET control, and GPIOs/LED drivers for a complete power system. The DC-DC
and LDO turn on automatically with push-button or valid AC input. The system holds them on by use of the
HOLD_DCDC1 and HOLD_LDO1 pins.
8.2 Functional Block Diagrams
TPS65720
BAT
AC
BAT
1uF
charger / power path
NTC
SYS
ISET
set
charge
current
LiIon
TS
SYS
4.7uF
R5
L1
HOLD_DCDC1
DCDC1
200mA
2.2uH
22pF
Vout 1
R1
4.7uF
FB_DCDC1
R2
VINLDO1
2.2uF
HOLD_LDO1
VLDO1
LDO 1
200mA
Vout 2
2.2uF
SYS
R6
PB_IN
ON /
OFF
reset
generator /
startup logic
RESET
INT
SCLK
PGND
I2C interface
SDAT
GPIO0
AGND
GPIO or
5mA current
sink
GPIO1
GPIO2
GPIO3
Copyright © 2016, Texas Instruments Incorporated
Figure 7. Functional Block Diagram for TPS65720
18
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Functional Block Diagrams (continued)
TPS657201
BAT
AC
BAT
1uF
charger / power path
NTC
SYS
ISET
set
charge
current
SYS
4.7uF
R5
L1
DCDC1
400mA
HOLD_DCDC1
VINLDO1
2.2uF
LiIon
TS
2.2uH
Vout 1
4.7uF
FB_DCDC1
VLDO1
LDO 1
200mA
HOLD_LDO1
Vout 2
2.2uF
SYS
TS_OUT
R6
reset
generator /
startup logic
PB_IN
ON /
OFF
RESET
INT
SCLK
I2C interface
PGND
SDAT
GPIO0
GPIO or
5mA current
sink
AGND
GPIO1
GPIO2
GPIO3
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Functional Block Diagram for TPS657201, TPS657202
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
19
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Functional Block Diagrams (continued)
TPS65721
AC
BAT
AC
BAT
1uF
charger / power path
NTC
SYS
ISET
set
charge
current
LiIon
TS
SYS
4.7uF
R5
L1
MODE
DCDC 1
200mA
HOLD_DCDC1
2.2uH
4.7uF
Vout1
R1
22pF
FB_DCDC1
R2
VINLDO1
VLDO1
LDO1
200 mA
HOLD_LDO1
Vout2
2.2uF
R3
FB_LDO1
R4
SYS
R6
THRESHOLD
PB_IN
reset
generator /
startup logic
ON /
OFF
RESET
INT
SCLK
I2C interface
PGND
SDAT
GPIO0
GPIO or
5mA current
sink
AGND
GPIO1
GPIO2
GPIO3
Copyright © 2016, Texas Instruments Incorporated
Figure 9. Functional Block Diagram for WQFN Version
8.3 Feature Description
8.3.1 Battery Charger and Power Path
The TPS6572x integrates a Li-Ion linear charger and system power-path management targeted at space-limited
portable applications. The TPS6572x powers the system while simultaneously and independently charging the
battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge
termination and enables the system to run with a defective or absent battery pack. It also allows instant system
turnon even with a totally discharged battery. The input power source for charging the battery and running the
system can be an AC adapter or an USB port. The power-path management feature automatically reduces the
charging current if the system load increases. The power-path architecture also permits the battery to
supplement the system current requirements when the adapter cannot deliver the peak system currents.
20
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Feature Description (continued)
8.3.2 Power-Path Management
The current at the input pin AC of the power path manager is shared between charging the battery and powering
the system load on the SYS pin. Priority is given to the system load. The input current is monitored continuously.
If the sum of the charging and system load currents exceeds the preset maximum input current (programmed
internally by I2C), the charging current is reduced automatically. The default value for the current limit is 500 mA
for the AC pin.
250mV
V BAT
OUT -SC1
V O(SC1
)
Q1
AC
< I_PR_CH0>
< I_PR_CH1>
V REF
ISET
V IPRECHG
V ICHG
< I_CH_SCL0 > T J
< I_CH_SCL1 >
T J(REG )
V IN -LOW
USB 100
USB 500
USB- susp
-
ILIM
Short Detect
V DPPM
V O(REG)
Q2
VSYS
V
BAT(REG
)
V OUT
I BIAS
IBAT(SC
40mV
-
ITERM
Supplement
V LOWV
V REF- ITERM
T3L: ITERM
~3V
)
BAT
V RCH
V BAT(SC)
ITERM floating
tD G L(RC H)
)
)
t D G L2 (L O W V
t D G L1 (L O W V
I BAT (DET)
tDG L (T E R M )
V AC
V BAT + V
OUT-SC2
SYS
EN2
Short Detect
t DGL(SC2)
BAT -SC
AC -DT
t DGL(NO
INTC
V HOT
-
IN )
t DGL(PGOOD
V UVLO
Charge Control
V COL
)
V OVP
D
t BLK(OVP
)
V DIS(TS)
T3L: /CE
Halt
timers
Reset
timers
V IPRECHG
V ICHG
V ISET
Dynamical
ly
Controlled
Oscillator
Fast - Charge
Timer
Pre -Charge
Timer
~100mV
TS
t DGL(T S )
Timers
disabled
T3L : TD
T3L: /GHG
T3L: /PGOOD
Timer
fault
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Charger Block Diagram
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
21
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Feature Description (continued)
8.3.3 Battery Charging
When = 1, battery charging begins. First, the device checks for a short circuit on the BAT pin by
sourcing IBAT(SC) to the battery and monitoring the voltage. When the BAT voltage exceeds VBAT(SC), the battery
charging continues. The battery is charged in three phases: conditioning pre-charge, constant-current fast charge
(current regulation) and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control
loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is
exceeded.
Figure 11 shows what happens in each of the three phases:
PRECHARGE
CC FAST CHARGE
CV TAPER
DONE
VBAT(REG)
IO(CHG)
Battery Current
Battery
Voltage
VLOWV
TERM CURRENT = 1
I(PRECHG)
I(TERM)
Figure 11. Battery Charge
In the pre-charge phase, the battery is charged with the pre-charge current (IPRECHG). Once the battery voltage
crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage
reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off
as the battery approaches full charge. Note that termination detection is disabled whenever the charge rate is
reduced from the set point because of the actions of the thermal loop, the DPM loop, or the VIN(LOW) loop. The
value of the fast-charge current is set by the resistor connected from the ISET pin to GND, and is given by
Equation 1:
ICHG = KISET / Riset
(1)
The charge current limit is adjustable up to 300 mA. The valid resistor range is 1500 Ω to 11.25 kΩ. Note that if
ICHG is programmed as greater than the input current limit, the battery does not charge at the rate of ICHG, but
at the slower rate of IACmax (minus the load current on the OUT pin, if any). In this case, the charger timers are
proportionately slowed down.
8.3.3.1 I-PRECHARGE
The value for the pre-charge current is defined with Bits based on the charge current defined
with pin ISET and Bits in register CHCONFIG1. Pre-charge current is scaled to lower
currents in DPPM mode or when the charger is in thermal regulation.
22
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Feature Description (continued)
8.3.3.2 ITERM
The value for the termination current threshold can be set in register CHGCONFIG1 using Bits based on the charge current defined with pin ISET and Bits . Termination
current is not scaled in DPPM mode or when the charger is in thermal regulation.
8.3.3.3 Battery Detection and Recharge
The charger automatically detects if a battery is connected or removed. Once a charge cycle is complete, the
battery voltage is monitored. When the battery voltage falls below VRCH, the device determines if the battery has
been removed. A current, IBAT(DET), is pulled from the battery for a duration tDET. If the voltage on the BAT pin
remains above VLOWV, it indicates that the battery is still connected, but has discharged. If = 1, the
charger is turned on again to top off the battery. Recharge cycles are not indicated by the Bit.
If the BAT voltage falls below VLOWV during the battery detection test, it indicates that the battery has been
removed. The device then checks for battery insertion. The FET Q2 is turned on and sources IPRECHG out of BAT
for the duration of tDET. If the battery voltage does not rise above VRCH, it indicates that a battery has been
inserted, and a new charge cycle begins. If the voltage rises above VRCH, it is possible that a fully charged
battery has been inserted. To check for this, IBAT(DET) is pulled from the battery for tDET. If the voltage falls below
VLOWV, a battery is not present. The device continuously checks for the presence of a battery.
8.3.3.4 Charge Termination On/Off
Charge termination can be disabled by setting the Bit = 0. When termination is disabled, the device
goes through the pre-charge, fast-charge, and CV phases, then remains in the CV phase. During the CV phase,
the charger behaves like an LDO with an output voltage equal to VBAT(REG) and is able to source currents up to
ICHG or IINmax, whichever is less. Battery detection is not performed. The Bit = 0 once the current
falls below ITERM and does not go t o1 until the input power is toggled. When termination is disabled, the precharge and fast-charge safety timers are also disabled. Battery pack temperature sensing (TS pin functionality) is
also disabled if Bit = 0 and the TS pin is unconnected.
8.3.3.5 Timers
The charger in TPS6572x has internal safety timers for the pre-charge and fast-charge phases to prevent
potential damage to either the battery or the system. The default values for the timers can be changed in register
CHGCONFIG2.
The pre-charge timer and fast charge timer will run with their nominal speed defined in register CHCONFIG2 if
ICH_SCL[1,0] = 01, which equals a charge current of 50% defined with the ISET resistor. If ICH_SCL[1,0] are set
to higher or lower fast-charge current, the fast charge timers and precharge timers are scaled automatically. For
instance, with ICH_SCL[1,0] = 11, which equals 100% of fast charge current, the safety timers will time out in
half the time defined in register CHCONFIG2. Changing the pre-charge current with I_PRE[1,0] will not change
the precharge or fast-charge timers.
8.3.3.6 Dynamic Timer Function
During the fast-charge phase, several events increase the timer durations.
• The system load current activates the DPM loop, which reduces the available charging current
• The input current is reduced because the input voltage has fallen to VIN(LOW)
• The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
During each of these events, the internal timers are slowed down proportionately to the reduction in charging
current. For example, if the charging current is reduced by half, the fast-charge timer is twice as long as
programmed.
A modified charge cycle with the thermal loop active is shown in Figure 12.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
23
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Feature Description (continued)
PRECHARGE
THERMAL
REGULATION
CC FAST
CHARGE
CV TAPER
DONE
VO(REG)
IO(CHG)
Battery
Voltage
Battery
Current
V(LOWV)
TERM CURRENT = 1
I(PRECHG)
I(TERM)
IC junction
temperature, Tj
TJ(REG)
Figure 12. Thermal Loop
8.3.3.7 Charger Fault
If the precharge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault condition.
Additionally, if the battery current does not fall to ITERM before the fast-charge timer expires, a fault is indicated
by setting Bit = 1.
8.3.4 Thermal Regulation and Thermal Shutdown
The charger contains a thermal regulation loop that monitors the die temperature. If the temperature exceeds
TJ(REG), the device automatically reduces the charging current to prevent the die temperature from increasing
further. In some cases, the die temperature continues to rise despite the operation of the thermal loop,
particularly under high VAC and heavy system load conditions. Under these conditions, if the die temperature
increases to TJ(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the battery still powers
the load on SYS. Once the device die temperature cools by TJ(OFF-HYS), the input FET Q1 is turned on and the
device returns to thermal regulation. Continuous over-temperature conditions result in the pulsing of the Q1 FET.
Note that this feature monitors the die temperature of the charger. This is not synonymous with ambient
temperature. Self-heating exists due to the power dissipated in the IC because of the linear nature of the battery
charging algorithm and the LDO mode for SYS.
8.3.5 Battery Pack Temperature Monitoring
The TPS6572x features an external battery pack temperature monitoring input. The TS input connects to the
NTC resistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature
conditions. During charging, INTC is sourced to TS and the voltage at TS is continuously monitored. If, at any
time, the voltage at TS is outside of the operating range (VCOLD to VHOT), charging is suspended. The timers
maintain their values but suspend counting. When the voltage measured at TS returns to within the operation
24
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Feature Description (continued)
window, charging is resumed and the timers continue counting. When charging is suspended due to a battery
pack temperature fault, the CH_ACTIVE Bit remains 1 and continues to indicate charging. Battery pack
temperature sensing is disabled when termination is disabled () and the voltage at TS is greater
than VDIS(TS). The battery pack temperature monitoring is disabled by connecting a 10-kΩ resistor from TS to
GND.
TPS6572x contains a feature to shift the termination temperature to higher levels by setting Bits .
8.3.6 DCDC1 Converter
The TPS6572x step-down converter operates with typically 2.25-MHz fixed-frequency pulse width modulation
(PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter Power
Save Mode and operates then in PFM mode.
During PWM operation, the converter use a unique fast response voltage mode control scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is
turned on. The current flows now from the input capacitor through the high-side MOSFET switch through the
inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips
and the control logic will turn off the switch. The current-limit comparator will also turn off the switch in case the
current limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot through current,
the low-side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from
the inductor to the output capacitor and to the load. It returns back to the inductor through the low-side MOSFET
rectifier.
The next cycle will be initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on
the on the high-side MOSFET switch.
The DCDC1 converters output voltage is externally adjustable using a resistor-divider at FB_DCDC1.
8.3.7 Power Save Mode
The power save mode is enabled automatically with = 0, which is the default setting. If the load
current decreases, the converter will enter power save mode operation automatically. During power save mode
the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent
current to maintain high efficiency. The converter will position the output voltage typically +1% above the nominal
output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The
transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode. During the power save mode the output voltage
is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT
nominal +1%, the device starts a PFM current pulse. The high-side MOSFET switch will turn on, and the inductor
current ramps up. After the ON-time expires, the switch is turned off and the low-side MOSFET switch is turned
on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor
and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal
or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical
15-μA current consumption.
If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage
ripple during PFM mode operation can be kept small. The PFM pulse is time controlled, which allows to modify
the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage
ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value.
Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency
decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode
is entered in case the output current can not longer be supported in PFM mode. The power save mode can be
disabled by setting = 1. The converter will then operate in fixed-frequency PWM mode.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
25
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Feature Description (continued)
8.3.7.1 Dynamic Voltage Positioning
This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice
versa. The feature is active in power-save mode and regulates the output voltage 1% higher than the nominal
value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load
throw-off (see Figure 13).
Figure 13. DVS Transition
8.3.7.2 Soft Start
The step-down converter in TPS6572x has an internal soft start circuit that controls the ramp up of the output
voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250 μs. This limits the
inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high
impedance power source is used.
EN
95%
5%
VOUT
tStart
tRAMP
Figure 14. Soft Start
8.3.7.3 100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output
voltage. To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN the high-side MOSFET switch is turned on completely. In this case the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain regulation depends on the load current and output voltage, and can be calculated in
Equation 2:
26
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Feature Description (continued)
VINmin = VOmax + IOmax × RDS(on)max + RL)
where
•
•
•
•
IOmax = maximum output current plus inductor ripple current
RDS(on)max = maximum high side switch RDSon
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
(2)
8.3.7.4 Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the converters and LDOs. The under-voltage lockout threshold is
typically 2.2 V.
8.3.8 Short-Circuit Protection
All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.
8.3.9 Thermal Shutdown
There are two thermal sensors in TPS6572x located at the main sources of power dissipation: the charger and
the LDO. The maximum temperature of the charger is regulated by reducing its charge current. If the
temperature increases further, the charger is disabled. See details in Battery Charging.
The second sensor is enabled as soon as the LDO is enabled. As soon as the junction temperature, TJ, exceeds
typically 150°C, the device goes into thermal shutdown. In this mode, the low side and high side MOSFETs are
turned off. A thermal shutdown for the LDO will disable both, LDO and the DC-DC converter simultaneously.
8.3.10 LDO1
The low dropout voltage regulator is designed to operate well with low value ceramic input and output capacitors.
The regulator operates with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 160 mV
at rated output current. LDO1 supports a current limit feature. Its output voltage is adjustable using a resistordivider at FB_LDO1 for TPS65721. The LDO1 voltage is fixed to 1.85 V for TPS65720 and TPS657201. For
TPS657202, the default LDO1 voltage is 2.85 V.
8.3.10.1 Default Voltage Setting for LDOs and DCDC1
Following are the output voltages of the different versions:
• TPS65720
– DCDC1: externally adjustable
– LDO1: 1.85 V
• TPS657201
– DCDC1: 1.85 V
– LDO1: 1.85 V
• TPS657202
– DCDC1: 1.90 V
– LDO1: 2.85 V
• TPS65721
– DCDC1: externally adjustable
– LDO1: externally adjustable
The I2C registers allow changing the default voltage for LDO1 in a range of 0.8 V to 3.3 V. For DCDC1, the
register also allows setting any voltage in the range from 0.8 V to 3.3 V, however for the adjustable versions, the
change in the I2C register has no effect on the output voltage. The registers will be set to the default value when
the voltage at SYS drops below the undervoltage lockout threshold or by a reset event (RESET output is actively
pulled low). See Register Maps for more details.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
27
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Feature Description (continued)
8.3.10.2 Internal Analog Multiplexer (BAT, TS, TS_OUT); TPS657201, TPS657202 Only
The internal Multiplexer switches the analog voltage on Pin BAT (battery voltage) or on pin TS (battery NTC) to
pin TS_OUT. The input is selected by Bit in register CONTROL1. The input voltage range of
2.5 V to 4.5 V on pin BAT is internally scaled to a voltage of 0 V to 1.4 V on pin TS_OUT. If the battery
temperature is selected as the input by setting = 1, a temperature range of –20°C to 60°C is
scaled to a voltage of 0 V to 1.4 V on pin TS_OUT. If the charger is not active, the internal current source for the
NTC inside the battery pack is enabled automatically if the multiplexer is enabled with = 1 AND
temperature measurement is selected by = 1. If the analog multiplexer is disabled with
= 0, the output VBAT/TS_OUT is shorted internally to GND, allowing for offset correction at the
ADC. See Figure 15 for more details.
BAT
+
-
Vref
2V
+
-
VBAT / TS_OUT
+
-
TS
0.48 x V2V0
+
-
TS_COLD
0.144 x V2V0
+
-
TS_HOT
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Multiplexer Block Diagram
The transfer function for the battery voltage is given in the Figure 16:
ADC MULTIPLEXER: VBAT SELECTED
1.4
VTS_OUT = VBAT •b - a = VBAT • 0.58 -1.245
VTS_OUT - V
1.2
1
VTS_OUT
0.8
0.6
0.4
0.2
0
2.2 2.35 2.5 2.65 2.8 2.95 3.1 3.25 3.4 3.55 3.7 3.85
4
4.15 4.3 4.45
VBAT - V
Figure 16. TS Multiplexer Output
8.3.10.3 Internal Battery Voltage Comparator
An internal comparator supervises the battery voltage at pin BAT when the device is configured for Li-primary
battery (CH_EN = 0), compares it to a voltage defined with registers , and sets Bit
in register CHCONFIG3 accordingly. An interrupt can be generated if the battery voltage falls
below the threshold and the feature is unmasked in register IRMASK0. If the battery voltage comparator is
disabled with VBAT_COMP_EN = 0 in register CHCONFIG2, the register containing the comparator output
VBAT_COMP in CHCONFIG3 is read as a logic HIGH.
28
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Feature Description (continued)
8.3.10.4 GPIOs, LED Drivers
TPS6572x contains 4 standard input/output pins (GPIOs) named GPIO0 to GPIO3. The output driver/input buffer
is available in register GPIO_SSC while register GPIODIR selects the data direction and additional features.
After RESET, GPIO0 and GPIO1 are pre-defined as general purpose inputs while GPIO2 and GPIO3 are
configured as LED driver outputs which are high impedance. The LED driver outputs are designed to be constant
current sinks to GND, sinking a constant current of 5 mA when enabled. The GPIOs do not have internal pull-up
resistors. External pull-up resistors might be required if configured as inputs or outputs.
8.3.10.5
RESET Output
Actively low, open-drain reset output. Connect external pull-up resistor. The reset pin will go high impedance 100
ms after the reset condition is left. For TPS65720, TPS657201, TPS657202, reset is generated, depending on
the power-good signal of LDO1, when the output voltage is below the threshold or LDO1 is disabled. For
TPS65721, reset is generated depending on the voltage at pin THRESHOLD.
8.3.10.6 Threshold Input (TPS65721 Only)
This is an input to the comparator driving the RESET output. If the voltage applied at THRESHOLD is below the
threshold, RESET is pulled actively LOW. If the voltage rises above the threshold + hysteresis, the RESET
output is released after a delay time of 100 ms (typically).
8.3.10.6.1 ENABLE for DCDC1 and LDO1
The DCDC1 converter and LDO1 are enabled as soon as PB_IN is pulled LOW OR input voltage at pin AC is
detected ( = 1).
There is a power-hold pin for DCDC1 (HOLD_DCDC1) and one for LDO1 (HOLD_LDO1). When HOLD_DCDC1
is pulled HIGH, DCDC1 is kept enabled after PB_IN was released HIGH. HOLD_LDO1 serves the same function
and keeps LDO1 enabled after PB_IN was released HIGH. After first power-up by pulling PB_IN = LOW or
applying voltage at AC, the HOLD pins HOLD_DCDC1 and HOLD_LDO1 can also be used as enable pins, such
that they turn on LDO1 or DCDC1, respectively when they are pulled HIGH. This function is available as long as
there is a voltage at the battery. After the battery was removed or was discharged, first power-on needs to be
done by pulling PB_IN = LOW.
Disabling the DC-DC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as
defined in Electrical Characteristics. In this mode, the low and high side MOSFETs are turned off and the entire
internal control circuitry is switched-off. For proper operation the PB_IN, HOLD_DCDC1, EN_DLO1 pins must be
terminated and must not be left floating.
8.3.10.6.2
PB_IN Input
Enables DCDC1 and LDO1 if pulled to GND. Disables DCDC1 and LDO1 if pulled high. There is no internal pullup resistor, so a resistor is needed externally to SYS. SYS is preferred over BAT because it is powered by either
AC or BAT (whichever is higher). If BAT is used, the device may not get a valid HIGH signal if the battery is
deeply discharged even when there is voltage at AC.
The input signal is debounced internally by 50 ms. When PB_IN is pulled low, the DCDC1 converter and LDO1
will power up simultaneously. When PB_IN is deasserted, both converters are turned off. To leave the converters
on, the HOLD_DCDC1 and HOLD_LDO1 pin need to be asserted high. The HOLD register Bit
will keep both, DCDC1 and LDO1 enabled if set to 1. For proper operation the PB_IN, HOLD_DCDC1 and
HOLD_LDO1 pins must be terminated and must not be left floating.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
29
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Feature Description (continued)
PB_IN
PB_IN
(internally after
debounce)
HOLD_DCDC1
set HIGH by I2C write to
register (optional)
HOLD_DCDC1 Bit
VDCDC1
HOLD_LDO1
set HIGH by I2C write to
register (optional)
HOLD_LDO1 Bit
VLDO1
Figure 17. PB_IN Timing
8.3.10.6.3 HOLD_DCDC1 Input
Actively high hold input for DCDC1. Logically OR´d with the DCDC1 hold Bit . If the input is
driven HIGH after PB_IN was pulled LOW, the DCDC1 converter stays on after PB_IN was released.
8.3.10.6.4 HOLD_LDO1 Input
Actively high hold input for LDO1. Logically OR´d with the LDO1 hold Bit . If the input is driven
HIGH after PB_IN was pulled LOW, LDO1 stays on after PB_IN was released.
8.3.10.6.5
INT Output
Actively low, open-drain interrupt output. Connect external pull-up resistor. Interrupts are flagged in the registers
IR0, IR1 and IR2 if the interrupt is not masked by registers IRMASK0, IRMASK1 and IRMASK2. Per default, all
interrupts are masked. Interrupts which are unmasked will set the Bit in either on the rising edge or on both
edges. Details can be found in the register description for IR0, IR1, and IR2 (see Register Maps). Any Bit in IR0,
IR1 and IR2, set to 1 will drive the reset pin INT actively LOW.
The reset pin will go high impedance after the Bit generating the reset is read.
8.4 Device Functional Modes
8.4.1 Power Down
The charger remains in power-down mode when the input voltage at the AC pin is below the undervoltage
lockout threshold (UVLO). During the power-down mode, the host commands through the I2C interface are
ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that connects BAT to SYS is ON.
(If = 1, Q2 is off). During power-down mode, the VOUT(SC2) circuitry is active and monitors for
overload conditions on SYS.
8.4.2 Sleep Mode
The charger enters sleep mode when VAC is greater than UVLO, but below VBAT + VIN(DT). In sleep mode, the
host commands are ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that
connects BAT to SYS is ON. (If = 1, Q2 is off). During sleep mode, the VOUT(SC2) circuitry is active
and monitors for overload conditions on SYS.
30
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Device Functional Modes (continued)
8.4.3 Standby Mode
When VAC is greater than UVLO and VIN is greater than VBAT + VIN(DT), the device is in standby mode.
= 1 to indicate the valid power status and the host commands are read. The device enters
standby mode whenever = (1,1) or if an input overvoltage condition
occurs. In standby mode, Q1 is OFF and Q2 is ON. (If = 1, Q2 is off). During standby mode, the
VOUT(SC2) circuitry is active and monitors for overload conditions on SYS.
8.4.4 Power-On Reset Mode
The charger enters power-on reset mode when the input voltage at AC is within the valid range: VAC > UVLO
and VAC > VBAT + VIN(DT) and VAC < VOVP, and the Bits indicate that
the USB suspend mode is not enabled [≠ (1,1)]. During power-on reset
mode, all internal timers and other circuit blocks are activated. The device checks for short-circuits at the ISET
pin. If no short conditions exists, the device switches on the input FET Q1 with a 100-mA current limit to check
for a short circuit at SYS. If VOUT rises above VSC, the FET Q1 switches to the current-limit threshold set by
, and the device enters into the Idle mode.
8.4.5 Idle Mode
In the Idle mode, the system is powered by the input source (Q1 is on), and the device continuously monitors the
status of the host commands. It also continuously monitors the input voltage conditions. Q2 is turned on
whenever the input source cannot deliver the required load current (supplement mode). The device also enters
Idle mode whenever = 0 while the input voltage is in the valid range of operation.
8.5 Programming
8.5.1 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS6572x has a 7-bit
address: 100 1000, other addresses are available upon contact with the factory. Attempting to read data from
register addresses not listed in this section will result in 00h being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS6572x device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS6572x device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS6572x device must leave the data line high to enable the master to generate the stop
condition.
For the WQFN version, the voltage the pull-up resistors for the I2C interface at SCLK and SDAT are connected
to, should be monitored by the reset circuitry. This is done by connecting THRESHOLD with a voltage divider to
the voltage the SDAT and SCLK pins are pulled-up to. This is needed to ensure a falling supply voltage will
cause a reset to the I2C interface. Otherwise a START condition may be detected and the first access to the I2C
interface may return NO ACK (no acknowledge).
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
31
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Programming (continued)
SDAT
SCLK
Change
of data
allowed
Data line
stable;
data valid
Figure 18. Bit Transfer on the Serial Interface
SDAT
SCLK
STOP condition
START condition
Figure 19. START and STOP Conditions
...
SCLK
SDAT
A6
A5
...
A4 ...
A0
R/W ACK
0
Start
R7
R6
R5
...
...
R0 ACK
0
D7
D6
D5 ...
0
Slave Address
D0 ACK
0
Register Address
Stop
Data
NOTE: SLAVE =TPS65720
Figure 20. Serial I/f WRITE to TPS6572x Device
...
SCLK
SDAT
A6
..
...
A0
R/W ACK
0
R7
..
...
...
R0
ACK
0
A6
..
A0
R/W ACK
0
1
D7
Register
Address
Slave Address
Repeated
Start
NOTE: SLAVE =TPS65720
D0
ACK
0
Start
Slave Address
..
Slave
Drives
the Data
Stop
Master
Drives
ACK and Stop
Figure 21. Serial I/f READ From TPS6572x: Protocol A
32
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
Programming (continued)
SCLK
...
SDAT
A6 ..
...
A0
R/W ACK
0
Start
R7 ..
A6 ..
R0 ACK
0
0
Register
Address
Slave Address
...
..
A0
R/W ACK D7 ..
1
Stop Start
0
Slave Address
ACK
D0
Slave
Drives
the Data
NOTE: SLAVE=TPS65720
Stop
Master
Drives
ACK and Stop
Figure 22. Serial I/f READ From TPS6572x: Protocol B
8.6 Register Maps
All registers are set to their default value by one of the following events:
• Voltage at the SYS pin is below the undervoltage lockout voltage (UVLO)
• RESET is active; RESET output is pulled LOW and goes high with a 100-ms delay
Table 2. Register Summary
ADDRESS
NAME
SHORT DESCRIPTION
0x01h
CHGSTATUS
Battery Charger Statuses
0x02h
CHGCONFIG0
Battery Charger Configuration and Control
0x03h
CHGCONFIG1
Battery Charger Configuration and Control
0x04h
CHGCONFIG2
Battery Charger Configuration and Control
0x05h
CHGCONFIG3
Battery Charger Configuration and Control
0x06h
CHGSTATE
Battery Charger Current State Notification
0x07h
DEFDCDC1
DCDC1 Output Voltage Setting and Control
0x08h
LDO_CTRL
LDO1 Output Voltage Setting and Control
0x09h
CONTROL0
Power Good Statuses and Force PWM Control
0x0Ah
CONTROL1
Miscellaneous Device Control and Push Button Status
0x0Bh
GPIO_SSC
Input Data for GPIOs If Set to Input Mode
0x0Ch
GPIO_DIR
GPIOs Configuration and Control
0x0Dh
IRMASK0
Interrupt Masking Control
0x0Eh
IRMASK1
Interrupt Masking Control
0x0Fh
IRMASK2
Interrupt Masking Control
0x10h
IR0
Interrupt Reporting
0x11h
IR1
Interrupt Reporting
0x12h
IR2
Interrupt Reporting
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
33
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.1 CHGSTATUS Register Address: 01h (read only)
CHGSTATUS
Bit name and function
Default
B7
B6
B5
B4
TS_HOT
TS_COLD
OVP
x
x
x
0
R
R
R
R
B3
B2
B1
BO
CH_ACTIVE
CH_PGOOD
CH_THLOOP
x
x
x
0
R
R
R
R
Default value loaded by:
Read/write
Bit 7
TS_HOT:
0 = battery temperature is below high temperature threshold (45°C/50°C/55°C/60°C).
1 = battery temperature is above high temperature threshold (45°C/50°C/55°C/60°C).
Bit 6
TS_COLD:
0 = battery temperature is above low temperature threshold (0°C/5°C/10°C/15°C)
1 = battery temperature is below low temperature threshold (0°C/5°C/10°C/15°C)
Bit 5
OVP:
0 = Input overvoltage protection is not active (VAC6.6 V)
Bit 3
CH_ACTIVE:
0 = charger is not active
1 = charger is charging the battery
Bit 2
CH_PGOOD:
0 = no input voltage at pin AC or voltage not inside the voltage range for changing
1 = power source is present and in the range valid for charging
Bit 1
CH_THLOOP:
0 = thermal loop or DPPM not active
1 = thermal loop or DPPM active, charge current is reduced due to thermal loop, low input voltage or
system load.
34
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
8.6.2 CHGCONFIG0 Register Address: 02h (read/write)
CHGCONFIG0
B7
B6
B5
B4
B3
B2
B1
BO
VSYS1
VSYS0
AC input
current1
AC input
current0
TH_LOOP
DYN_TMR
TERM_EN
CH_EN
Default
For TPS65720,
TPS657201
0
1
1
0
1
1
1
1
Default for TPS657202
0
1
0
0
1
1
1
1
Default for TPS65721
1
0
1
0
1
1
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit name and function
Default value loaded by:
Read/write
Bit 7..6 VSYS1..VSYS0:
00 = the output voltage of the power path at pin SYS tracks the battery voltage;
VSYS = VBAT + 200 mV (Vbat > 3.3 V); VSYS = 3.4 V (VBAT ≤ 3.3 V); V_DPPM = 1 is forced in this
case
01 = the output voltage of the power path at pin SYS is regulated to 4.4 V
10 = the output voltage of the power path at pin SYS is regulated to 5 V
11 = the output voltage of the power path at pin SYS is regulated to 5.5 V
Bit 5..4 AC input current1.. AC input current0:
00 = 100 mA, input voltage DPPM enabled
01 = 500 mA, input voltage DPPM enabled
10 = 500 mA, input voltage DPPM disabled
11 = USB suspend mode; standby
Bit 3
TH_LOOP:
0 = the thermal loop is disabled
1 = the thermal loop is enabled and the charge current is reduced if the temperature exceeds 125°C
Bit 2
DYN_TMR (dynamic timer function):
0 = safety timers run with their normal clock speed
1 = clock speed for the safety timers is reduced based on the actual charge current if DPPM or
thermal loop is active
Bit 1
TERM_EN (charge termination enable):
0 = charge termination will not occur and the charger will always be on
1 = charge termination enabled based on timers and termination current
Bit 0
CH_EN:
0 = the charger is disabled
1 = the charger is enabled
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
35
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.3 CHGCONFIG1 Register Address: 03h (read/write)
CHGCONFIG1
Bit name and function
Default
For TPS65720,
TPS657201, TPS657202
Default for TPS65721
Default value loaded by:
Read/write
B7
B6
B5
B4
B3
B2
B1
BO
I_PRE1
I_PRE0
ICH_SCL1
ICH_SCL0
I_TERM1
I_TERM0
0
1
0
1
0
1
0
0
1
1
R
R
0
1
1
1
0
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7..6
I_PRE1..I_PRE0 (Pre-charge current factor):
00 = 5% of value defined with ICH_SCL1, ICH_SCL0
01 = 10% of value defined with ICH_SCL1, ICH_SCL0
10 = 15% of value defined with ICH_SCL1, ICH_SCL0
11 = 20% of value defined with ICH_SCL1, ICH_SCL0
Bit 5..4
ICH_SCL1..ICH_SCL0 (charge current scaling factor):
00 = 25% of value defined with ISET resistor; safety timer will time out at 2x SFTY_TMR[0,1]
01 = 50% of value defined with ISET resistor; safety timer runs at its nominal time defined in
SFTY_TMR[0,1]
10 = 75% of value defined with ISET resistor; safety timer will time out at 0.66x SFTY_TMR[0,1]
11 = 100% of value defined with ISET resistor; safety timer will time out at 0.5x SFTY_TMR[0,1]
Bit 3..2
I_TERM1..I_TERM0 (termination current scaling factor):
00 = 5% of value defined with ICH_SCL1, ICH_SCL0
01 = 10% of value defined with ICH_SCL1, ICH_SCL0
10 = 15% of value defined with ICH_SCL1, ICH_SCL0
11 = 20% of value defined with ICH_SCL1, ICH_SCL0
8.6.4 CHGCONFIG2 Register Address: 04h (read/write)
CHGCONFIG2
Bit name and function
Default
Default value loaded
by:
Read/write
B7
B6
B5
SFTY_TMR1 0
SFTY_TMR
PRE_TMR
0
1
0
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
B4
0
R
Bit 7..6
SFTY_TMR1..SFTY_TMR0 (charge safety timer value):
00 = 4h
01 = 5h
10 = 6h
11 = 8h
Bit 5
PRE_TMR (pre-charge timer value):
0 = 30 min
1 = 60 min
Bit 3
NTC (sensor resistance):
0 = 100k NTC (I = 7.5 µA)
1 = 10k NTC (I = 75 µA)
Bit 2
V_DPPM (dynamic power path threshold):
0 = VBAT + 100 mV
1 = 4.3 V
36
Submit Documentation Feedback
B3
B2
B1
NTC
V_DPPM
VBAT_COMP_EN
1
1
0
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
BO
0
R
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
Bit 1
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
VBAT_COMP_EN (battery voltage comparator enable):
0 = battery voltage comparator for Li-primary cells disabled; VBAT_COMP interrupt disabled
1 = battery voltage comparator for Li-primary cells enabled
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
37
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.5 CHGCONFIG3 Register Address: 05h (read/write)
CHGCONFIG3
Bit name and function
Default
Default value loaded by:
Read/write
B7
B6
B5
B4
B3
B2
B1
BO
CH_VLTG2
CH_VLTG1
CH_VLTG0
TMP_SHIFT1
TMP_SHIFT0
VBAT1
VBAT0
VBAT_COMP
0
1
0
0
0
0
0
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit 7..5
CH_VLTG2..CH_VLTG0 (charge voltage selection):
000 = 4.15 V
001 = 4.175 V
010 = 4.20 V
011 = 4.225 V
100 = 4.25 V
101 = 4.275 V
110 = 4.3 V
111 = 4.325 V
Bit 4..3
TMP_SHIFT1..TMP_SHIFT0 (battery temperature shift):
00 = the temperature for TS_COLD and TS_HOT is at 0°C/45°C
01 = the temperature window is shifted by 5°C to TS_COLD/TS_HOT = 5°C/50°C
10 = the temperature window is shifted by 10°C to TS_COLD/TS_HOT = 10°C/55°C
11 = the temperature window is shifted by 15°C to TS_COLD/TS_HOT = 15°C/60°C
Bit 2..1
VBAT1..VBAT0 (battery voltage comparator threshold; for Li primary cells):
00 = 2.2 V
01 = 2.3 V
10 = 2.4 V
11 = 2.5 V
Bit 0
VBAT_COMP (battery voltage comparator output):
0 = voltage above the threshold
1 = voltage below the threshold or comparator disabled
38
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
8.6.6 CHGSTATE Register Address: 06h (read only)
CHGSTATE
Bit name and function
B7
B6
B5
B4
B3
CH_PRECH CH_CC_CV
B2
B1
BO
CH_SUSP
CH_SLEEP
CH_RESET
CH_IDLE
CH_LDO
CH_FAULT
Default
X
X
X
X
X
X
X
X
Read/write
R
R
R
R
R
R
R
R
Bit 7
CH_SLEEP:
0 = charger is not in sleep state
1 = charger is in sleep state
Bit 6
CH_RESET:
0 = charger is not in reset state
1 = charger is in reset state
Bit 5
CH_IDLE:
0 = charger is not in idle state
1 = charger is in idle state
Bit 4
CH_PRECH:
0 = charger is not in precharge state
1 = charger is in precharge state
Bit 3
CH_CC_CV:
0 = charger is not in constant current mode or constant voltage mode
1 = charger is in constant current mode or constant voltage mode
Bit 2
CH_LDO:
0 = charger is not in LDO mode
1 = charger is in LDO mode
Bit 1
CH_FAULT:
0 = charger is not in fault state
1 = charger is in fault state
Bit 0
CH_SUSP:
0 = charger is not in suspend state
1 = charger is in suspend state
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
39
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.7 DEFDCDC1 Register Address: 07h (read/write)
DEFDCDC1
B7
B6
B5
B4
B3
B2
B1
BO
Bit name and
function
HOLD_
DCDC1
DCDC_DISCH
DCDC1[5]
DCDC1[4]
DCDC1[3]
DCDC1[2]
DCDC1[1]
DCDC1[0]
Default for
TPS65720,
TPS65721
0
0
1
0
1
0
0
1
Default for
TPS657201
0
0
1
0
0
1
0
1
Default for
TPS657202
0
0
1
0
0
1
1
0
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default value loaded
by:
Read/write
Bit 7
HOLD_DCDC1:
0 = DCDC1 is disabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH
1 = DCDC1 stays enabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH
Bit 6
DCDC_DISCH:
0 = DCDC1 output is not discharged when DCDC1 is disabled
1 = DCDC1 output is discharged when DCDC1 is disabled
Bit 5..0
Output voltage setting for DCDC1:
For reference only: A voltage change in the register will not have an effect on the output voltage for
TPS65720 and TPS65721 as the voltage is set by an external resistor divider. Contact TI in case a
fixed voltage version is needed.
A voltage change during operation must not exceed 8% of the value set in the register for each I2C
write access as this may trigger the internal power good comparator and will trigger the Reset of
the device. This limitation is only for a voltage step to higher voltages. There is no limitation for
programming lower voltages by I2C.
40
OUTPUT VOLTAGE [V]
B5
B4
B3
B2
B1
B0
0
0.800
0
0
0
0
0
0
1
0.825
0
0
0
0
0
1
2
0.850
0
0
0
0
1
0
3
0.875
0
0
0
0
1
1
4
0.900
0
0
0
1
0
0
5
0.925
0
0
0
1
0
1
6
0.950
0
0
0
1
1
0
7
0.975
0
0
0
1
1
1
8
1.000
0
0
1
0
0
0
9
1.025
0
0
1
0
0
1
10
1.050
0
0
1
0
1
0
11
1.075
0
0
1
0
1
1
12
1.100
0
0
1
1
0
0
13
1.125
0
0
1
1
0
1
14
1.150
0
0
1
1
1
0
15
1.175
0
0
1
1
1
1
16
1.200
0
1
0
0
0
0
17
1.225
0
1
0
0
0
1
18
1.250
0
1
0
0
1
0
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
OUTPUT VOLTAGE [V]
B5
B4
B3
B2
B1
B0
19
1.275
0
1
0
0
1
1
20
1.300
0
1
0
1
0
0
21
1.325
0
1
0
1
0
1
22
1.350
0
1
0
1
1
0
23
1.375
0
1
0
1
1
1
24
1.400
0
1
1
0
0
0
25
1.425
0
1
1
0
0
1
26
1.450
0
1
1
0
1
0
27
1.475
0
1
1
0
1
1
28
1.500
0
1
1
1
0
0
29
1.525
0
1
1
1
0
1
30
1.550
0
1
1
1
1
0
31
1.575
0
1
1
1
1
1
32
1.600
1
0
0
0
0
0
33
1.650
1
0
0
0
0
1
34
1.700
1
0
0
0
1
0
35
1.750
1
0
0
0
1
1
36
1.800
1
0
0
1
0
0
37
1.850
1
0
0
1
0
1
38
1.900
1
0
0
1
1
0
39
1.950
1
0
0
1
1
1
40
2.000
1
0
1
0
0
0
41
2.050
1
0
1
0
0
1
42
2.100
1
0
1
0
1
0
43
2.150
1
0
1
0
1
1
44
2.200
1
0
1
1
0
0
45
2.250
1
0
1
1
0
1
46
2.300
1
0
1
1
1
0
47
2.350
1
0
1
1
1
1
48
2.400
1
1
0
0
0
0
49
2.450
1
1
0
0
0
1
50
2.500
1
1
0
0
1
0
51
2.550
1
1
0
0
1
1
52
2.600
1
1
0
1
0
0
53
2.650
1
1
0
1
0
1
54
2.700
1
1
0
1
1
0
55
2.750
1
1
0
1
1
1
56
2.800
1
1
1
0
0
0
57
2.850
1
1
1
0
0
1
58
2.900
1
1
1
0
1
0
59
2.950
1
1
1
0
1
1
60
3.000
1
1
1
1
0
0
61
3.100
1
1
1
1
0
1
62
3.200
1
1
1
1
1
0
63
3.300
1
1
1
1
1
1
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
41
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.8 LDO_CTRL Register Address: 08h (read/write)
LDO_CTRL
B7
B6
B5
B4
B3
B2
B1
BO
HOLD_LDO1
LDO1_DISCH
LDO1[5]
LDO1[4]
LDO1[3]
LDO1[2]
LDO1[1]
LDO1[0]
Default except TPS657202
0
1
1
0
0
1
0
1
Default for TPS657202
0
1
1
1
1
0
0
1
Default value loaded by:
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit name and function
Read/write
Bit 7
HOLD_LDO1:
0 = LDO1 is disabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH
1 = LDO1 stays enabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH
Bit 6
LDO1_DISCH:
0 = LDO1 output is not discharged when LDO1 is disabled
1 = LDO1 output is discharged when LDO1 is disabled
Bit 5..0
LDO1 output voltage setting according to the table listed for DCDC1:
The voltage setting is only valid for TPS65720. For TPS65721, the LDO1 voltage is set by an
external resistor-divider. The voltage setting is according to the same table given for DEFDCDC1.
8.6.9 CONTROL0 Register Address: 09h (read/write)
CONTROL0
Bit name and function
Default
Default value loaded by:
Read/write
B7
B6
B5
B4
B3
B2
B1
BO
F_PWM
PGOODZ_DCDC1
PGOODZ_LDO1
0
PGOODDCDC1
PGOODLDO1
0
0
0
0
0
R
R
R
R
R
R
R
UVLO/R
R/W
Bit 7
F_PWM:
0 = DC-DC converter is in PWM/PFM mode
1 = DC-DC converter is in forced PWM mode
Bit 6
PGOODZ_DCDC1:
0 = indicates that the DC-DC converters output voltage is within its nominal range
1 = range indicates that the DC-DC converters output voltage is below the target regulation voltage or
disabled
Bit 5
PGOODZ_LDO1:
0 = indicates that the LDO1 output voltage is within its nominal range
1 = indicates that the LDO1 output voltage is below the target regulation voltage or disabled
42
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
8.6.10 CONTROL1 Register Address: 0Ah (read/write)
CONTROL1
B7
B6
Bit name and function
Default
0
R
B4
HOLD
PB_STAT
0
B3
0
Default value loaded by:
Read/write
B5
B1
BO
OPAMP
_
MUX
OPAMP_
EN
RESET_DELAY
1
0
1
UVLO/
R
UVLO/R
UVLO/R
R/W
R/W
R/W
0
UVLO/R
UVLO/R
R
R/W
R
B2
R
Bit 5
HOLD (ORed with PB_IN):
0 = DCDC1 and LDO1 switched off
1 = DCDC1 and LDO1 enabled
Bit 4
PB_STAT (push-button status, after debounce):
0 = push-button not pressed
1 = push-button pressed
Bit 2
OPAMP_MUX (only for TPS657201):
0 = battery voltage measurement
1 = temperature measurement
Bit 1
OPAMP_EN (only for TPS657201):
0 = OPAMP and MUX disabled; enabled automatically if = 1
1 = OPAMP and MUX enabled
Bit 0
RESET_DELAY:
0 = 11 ms
1 = 90 ms
8.6.11
GPIO_SSC Register Address: 0Bh (read/write)
GPIO_SSC
B7
B6
B5
B4
0
0
0
0
B3
B2
B1
BO
GPIO3
GPIO2
GPIO1
GPIO0
1
1
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R
R
R
R/W
Bit name and function
Default
Default value loaded by:
Read/write
R
R
R
R/W
Bit 3
GPIO3:
0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled
1 = data in input buffer / high impedance when configured as an output or LED driver
Bit 2
GPIO2:
0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled
1 = data in input buffer / high impedance when configured as an output or LED driver
Bit 1
GPIO1:
0 = data in input buffer / actively pulled low when configured as an output
1 = data in input buffer / high impedance when configured as an output
Bit 0
GPIO0:
0 = data in input buffer / actively pulled low when configured as an output
1 = data in input buffer / high impedance when configured as an output
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
43
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.12 GPIODIR Register Address: 0Ch (read/write)
GPIODIR
Bit name and function
Default
Default value loaded by:
Read/write
B7
B6
GPIO3_LED
GPIO2_LED
1
1
UVLO/R
UVLO/R
R/W
R/W
B5
B4
1
1
R
R
Bit 7
GPIO3_LED:
0 = GPIO3 is configured as a standard GPIO
1 = GPIO3 is configured as 5-mA LED driver
Bit 6
GPIO2_LED:
0 = GPIO2 is configured as a standard GPIO
1 = GPIO2 is configured as 5-mA LED driver
Bit 3
GPIO3_DIR:
0 = GPIO3 is configured as an output / LED driver
1 = GPIO3 is configured as an input
Bit 2
GPIO2_DIR:
0 = GPIO2 is configured as an output / LED driver
1 = GPIO2 is configured as an input
Bit 1
GPIO1_DIR:
0 = GPIO1 is configured as an output
1 = GPIO1 is configured as an input
Bit 0
GPIO0_DIR:
0 = GPIO0 is configured as an output
1 = GPIO0 is configured as an input
B3
B2
B1
BO
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
GPIO0_DIR
0
0
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
8.6.13 IRMASK0 Register Address: 0Dh (read/write)
IRMASK0
Bit name and
function
Default
Default value
loaded by:
Read/write
Bit 7..0
44
B7
B6
B5
B4
B3
B2
B1
BO
M_TS_HOT
M_TS_COLD
M_OVP
Reserved
M_CH_
ACTIVE
M_CH_
PGOOD
M_VBAT_
COMP
M_THLOOP
1
1
1
1
1
1
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
charger interrupt mask register:
0 = Interrupt not masked
1 = Interrupt masked (no interrupt based on the event)
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
8.6.14 IRMASK1 Register Address: 0Eh (read/write)
IRMASK1
Bit name and
function
B7
B6
B5
B4
M_CH_
SLEEP
M_CH_
RESET
M_CH_IDLE
M_CH_PRECH
1
1
1
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
Default
Default value
loaded by:
Read/write
Bit 7..0
B3
B2
B1
BO
M_CH_ FAULT
M_CH_
SUSP
1
1
1
UVLO/R
UVLO/R
UVLO/R
UVLO/R
R/W
R/W
R/W
R/W
M_CH_CC_ M_CH_ LDO
CV
charger state interrupt mask register:
0 = Interrupt not masked
1 = Interrupt masked (no interrupt based on the event)
8.6.15 IRMASK2 Register Address: 0Fh (read/write)
IRMASK2
Bit name
and function
Default
B7
B6
B5
B4
B3
B2
B1
M_GPIO3
M_GPIO2
M_GPIO1
M_GPIO0
M_PGOODZ_
DCDC1
M_PGOODZ_
LDO1
M_PB_ STAT
1
1
1
1
1
1
1
Default
value
loaded by:
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7..0
charger state interrupt mask register:
0 = Interrupt not masked
1 = Interrupt masked (no interrupt based on the event)
BO
1
R
8.6.16 IR0 Register Address: 10h (read only)
IR0
Bit name and
function
Default
Default value
loaded by:
Set by:
Read/write
Bit 7..2
B7
B6
B5
B4
B3
B2
B1
BO
TS_HOT
TS_COLD
OVP
Reserved
CH_ACTIVE
CH_PGOOD
VBAT_COMP
TH_LOOP
0
0
0
0
0
0
0
0
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
Rising edge of
TS_HOT
Rising edge of
TS_COLD
Rising edge of
OVP
Reserved
Rising edge of
VBAT_COMP*
Rising edge of
TH_LOOP
R
R
R
R
R
R
Rising edge
Rising edge
and falling edge and falling edge
of CH_ACTIVE of CH_PGOOD
R
R
interrupt register:
0 = no interrupt
1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK0
The VBAT_COMP interrupt is automatically disabled when the battery voltage comparator is disabled by
clearing Bit 1 in register 04h (VBAT_COMP_EN)
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
45
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
8.6.17 IR1 Register Address: 11h (read)
IR1
Bit name and
function
Default
Default value
loaded by:
Set by:
Read/write
Bit 7..0
B7
B6
B5
B4
B3
B2
B1
BO
CH_SLEEP
CH_RESET
CH_IDLE
CH_PRECH
CH_CC_CV
CH_LDO
CH_FAULT
CH_SUSP
0
0
0
0
0
0
0
0
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
Rising edge of
CH_SLEEP
Rising edge of
CH_RESET
Rising edge of
CH_IDLE
Rising edge of
CH_PRECH
Rising edge of
CH_CC_CV
Rising edge of
CH_LDO
Rising edge of
VBAT_FAULT*
Rising edge of
TH_SUSP
R
R
R
R
R
R
R
R
interrupt register:
0 = no interrupt
1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK1
8.6.18 IR2 Register Address: 12h (read)
IR2
Bit name and
function
Default
Default value
loaded by:
Set by:
Read/write
B7
B6
B5
B4
B3
B2
B1
GPIO3
GPIO2
GPIO1
GPIO0
PGOODZ_
DCDC1
PGOODZ_
LDO1
PB_STAT
0
0
0
0
0
0
0
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
UVLO/R
Rising and
falling edge of
GPIO3
Rising and
falling edge of
GPIO2
Rising and
falling edge of
GPIO1
Rising and
falling edge of
GPIO0
Rising edge of
PGOODZ_
DCDC1
Rising edge of
PGOODZ_
LDO1
Rising and
falling edge of
PB_ STAT
R
R
R
R
R
R
R
BO
Bit 7..4
GPIO interrupt register:
0 = GPIO status did not change
1 = GPIO status changed; cleared when read; interrupt not masked in register IRMASK2
Bit 3..2
power good interrupt register:
0 = no interrupt (power good)
1 = interrupt occurred (output voltage of DCDC converter or LDO too low); cleared when read
Bit 1
PB_STAT interrupt register:
0 = no interrupt
1 = interrupt occurred; cleared when read; interrupt not masked in register IRMASK2
46
Submit Documentation Feedback
0
R
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The intended applications for the TPS6572x device are small handheld or wearable devices powered from a
single cell Lithium-Ion battery. The input path current limit is great for charging from USB sources by allowing the
selection between 100-mA or 500-mA input supply current.
9.2 Typical Application
TPS65720
BAT
AC
BAT
1 µF
3 kΩ
for a charge
current of
150 mA
ISET
Charger and Power Path
10 kΩ
TS
SYS
SYS
R5
L1
DCDC1
200 mA
LiIon
NTC
4.7 µF / 6.3 V
2.2 µH
VDCDC1 = 2.05 V
R1
360 kΩ
FB_DCDC1
4.7 µF
22 pF
R2
150 kΩ
VINLDO1
Bluetooth Chip
2.2 µF
LDO1
200 mA
VLDO1 = 1.85 V
VLDO1
Vin
4.7 µF / 4 V
2 × 3.3 kΩ
2 × 100 kΩ
RESET
Reset Generator
and Startup Logic
SYS
Reset
INT
INT
HOLD_LDO1
R6
ON
or
OFF
GPIO
HOLD_DCDC1
PB_IN
SCLK
2
I C Interface
PGND
AGND
SCLK
SDAT
SDAT
GPIO0
GPIO or
5-mA Current
Sink
GPIO1
GPIO2
GPIO3
To SYS or VDCDC1
depending on LED
forward voltage
Indication LEDs
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Typical Bluetooth Application
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
47
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
With only a handful of required components to operate the TPS6572x, designing with the TPS6572x is easy.
After setting the output voltage of both the LDO and DC-DC, it is required to select appropriate output filter inorder to ensure best operation of the DC-DC. The TPS6572x requires appropriate input and output capacitors for
the DC-DC and LDO. The battery charger requires the charge current to be set by the use a resistor and may
require an NTC thermistor at the battery.
For noise sensitive devices it is required to use a larger inductance value in-order to reduce the output ripple.
Cascading the LDO from the DC-DC is great technique to reduce noise injected into the load and maintaining the
high efficiency step-down from the DC-DC input to the LDO output.
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Setting
9.2.2.1.1 DCDC1
For TPS65720 and TPS65721, the output voltage of the DCDC converter can be set with external resistor
network on Pin FB_DCDC1. The feedback voltage is 0.6 V.
TI recommends setting the total resistance of R1 + R2 to less than 1 MΩ. Route the FB_DCDC1 trace separate
from noise sources, such as the inductor trace (L1).
VFB-DCDC1 = 0.6 V
VO UT = V FB_DCDC1 ´
R1 + R2
R2
æ VOUT ö
R1 = R2 ´ ç
÷ - R2
è V FB_DCDC1 ø
(3)
Table 3. Typical Resistor Values
OUTPUT VOLTAGE
R1
R2
NOMINAL VOLTAGE
3.3 V
680 kΩ
150 kΩ
3.32 V
3V
510 kΩ
130 kΩ
2.95 V
2.85 V
560 kΩ
150 kΩ
2.84 V
2.5 V
510 kΩ
160 kΩ
2.51 V
2.05 V
360 kΩ
150 kΩ
2.04 V
2V
470 kΩ
200 kΩ
2.01 V
1.8 V
300 kΩ
150 kΩ
1.8 V
1.6 V
200 kΩ
120 kΩ
1.6 V
1.5 V
300 kΩ
200 kΩ
1.5 V
1.2 V
330 kΩ
330 kΩ
1.2 V
A feedforward capacitor in parallel to the resistor from Vout to FB_DCDC1 is required. Its value should be based
on transient performance and will be in the range from 4.7 pF to 22 pF.
For TPS657201, the output voltage of DCDC1 is fixed at 1.85 V per default and can be changed in register
DEFDCDC1. For TPS657202, the default output voltage is 1.9 V. The feedback connection has to be made from
pin FB_DCDC1 to the output capacitor directly. A voltage change to a higher voltage needs to be accomplished
in steps of 8% maximum otherwise the power-good comparator will detect a too low voltage, will trigger and
generate a reset. There is no limitation in programming output voltages to lower values.
9.2.2.1.2 LDO1
For TPS65720 and TPS657201, the default output voltage is 1.85 V while the default output voltage is 2.85 V for
TPS657202, defined by register LDO_CTRL. The programmable voltage range is 0.8 V to 3.3 V. A voltage
change to a higher voltage needs to be accomplished in steps of 8% maximum otherwise the power-good
comparator will detect a too low voltage, will trigger and generate a reset. There is no limitation in programming
output voltages to lower values.
48
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
For the TPS65721, the output voltage for LDO1 is externally adjustable using a resistor-divider at pin FB_LDO1.
The feedback voltage is 0.8 V and the total resistance of the voltage divider should be kept in the 100-kΩ to
1-MΩ range. A feed-forward capacitor in parallel to the resistor from Vout to FB_LDO1 is required. It´s value
should be based on transient performance and will be in the range from 4.7 pF to 22 pF.
The output voltage with an internal reference voltage VFB-LDO1 = 0.8 V is calculated by Equation 4:
VOUT = VFB_LDOx ´
æ V OUT ö
R3 = R4 ´ ç
÷ - R4
è VFB_LDO1 ø
R3 + R4
R4
(4)
Table 4. Typical Resistor Values
OUTPUT VOLTAGE
R3
R4
NOMINAL VOLTAGE
3.3 V
470 kΩ
150 kΩ
3.31 V
1.85 V
200 kΩ
150 kΩ
1.86 V
1.8 V
300 kΩ
240 kΩ
1.80 V
9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
9.2.2.2.1 Inductor Selection
The converter operates typically with 3.3-μH output inductor. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for
its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency
of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.
Equation 5 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 5. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
Vout
1DI
Vin
ILmax = Ioutm ax + L
DIL = Vout ´
L ´ ¦
2
where
•
•
•
•
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
(5)
The highest inductor current will occur at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. It must be considered, that the core material from inductor to inductor differs and will
have an impact on the efficiency especially at high switching frequencies.
Refer to Table 5 and the typical applications for possible inductors.
Table 5. Tested Inductors
INDUCTOR TYPE
INDUCTOR VALUE
SUPPLIER
COMMENTS
LQM21P
3.3 µH
Murata
For TPS65720
BRC1608T2R2M
2.2 µH
Taiyo Yuden
For TPS65720; Smallest solution size;
up to 150 mA of output current
VLS201610ET-2R2M
2.2 µH
TDK
For TPS65720, TPS65721,
TPS657201, TPS657202
GLFR1608T2R2M-LR
2.2 µH
TDK
For TPS65720; Smallest solution size;
up to 150 mA of output current
MIPSA2520
2.2 µH
FDK
For TPS65721, TPS657201,
TPS657202; highest efficiency
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
49
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
9.2.2.2.2 Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small
ceramic capacitors with a typical value of 10 μF, without having large output voltage under and overshoots during
heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are
therefore recommended. For an inductor value of 3.3 μH, an output capacitor with 4.7 μF can be used. Refer to
recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. Just for completeness the RMS ripple current is calculated by Equation 6:
Vout
11
Vin ´
IRMSCout = Vout ´
L ´ ¦
2 ´ 3
(6)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor, as calculated by Equation 7:
Vout
1ö
1
Vin ´ æ
DVout = Vout ´
+ ESR ÷
ç
L ´ ¦
è 8 ´ Cout ´ ¦
ø
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
9.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes (see Table 6). The converters need a ceramic input capacitor of 4.7 μF. The input capacitor can
be increased without any limit for better input voltage filtering.
Table 6. Tested Capacitors
50
TYPE
VALUE
VOLTAGE RATING
SIZE
SUPPLIER
MATERIAL
GRM155R60G475ME47D
GRM155R60J225ME15D
4.7 μF
4V
0402
Murata
Ceramic X5R
2.2 μF
6.3 V
0402
Murata
Ceramic X5R
GRM188R60J475K
4.7 μF
6.3 V
0603
Murata
Ceramic X5R
GMK107BJ105K
1 μF
35 V
0603
Taiyo Yuden
Ceramic X5R
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
9.2.2.3 Charger/Power Path
9.2.2.3.1 Charger Stability
To ensure stable operation of the charger including the power path, a list of components and their recommended
value is given in Table 7. These values represent the capacitance or inductance value in the application under
the given operating conditions. For example, ceramic capacitors will typically show a drop in capacitance when a
DC voltage is applied. Due to this dc bias effect, the capacitance in the applications when voltage is applied is
much less than the nominal capacitor value. See the capacitor manufacturer data sheet for derating.
At pin AC, a series inductance of may be used with a values as stated in Table 7.
Pins AC, SYS and BAT have been tested to be stable with the values given in Table 7:
Table 7. Recommended Components for Charger
PIN NAME
Cmin (μF)
Cmax (μF)
Lmin (μH)
lmax (μH)
AC
0.1
1
0
2
SYS
1
10
—
—
BAT
0.1
4.7
—
—
9.2.2.3.2 Setting the Charge Current
The charge current is set with an external resistor connected form ISET to GND.
The resulting charge current is calculated by Equation 8:
KSET
K SET
ICHARGE =
RSET =
R SET
ISET
(8)
Additionally, the charge current can be scaled to 100%, 75%, 50%, or 25% of the value set by Rset by software
in register CHCONFIG1 using Bits ICH_SCL[1,0]. Precharge current and termination current is scaled
accordingly.
9.2.2.3.3 Dynamic Power Path Management (DPPM)
The charger/power path in TPS6572x contains two different features to ensure there is sufficient power at the
load and the input voltage supplying the charger/power path does not collapse.
First there is output voltage DPPM, which is a control loop to keep the voltage at the output of the power path
above a certain limit. In TPS6572x, the voltage at the output of the power path (SYS) is regulated to what is
defined with VSYS[1,0] in register CHCONFIG0. When the current needed for the load and for charging the
battery exceeds the input current limit, the voltage at SYS will collapse. The DPPM loop will reduce the charge
current, such that the total current for the load and the charge current equals the input current limit. This is done
as soon as the voltage at SYS drops 100 mV below the target voltage.
Second there is input voltage DPPM. For this, the input voltage to the charger/power path at pin AC is sensed to
avoid the voltage from a USB port or dedicated charger to drop below a certain limit. This control loop will reduce
the input current limit for pin AC as soon as the voltage at AC drops below 4.5 V (typically). With Bits
ACinputcurrent[1,0] set to 00 or 01, input voltage DPPM is enabled, with ACinputcurrent=10, input voltage DPPM
is disabled.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
51
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
9.2.3 Application Curves
The graphs have been generated on the TPS65720YFF EVM with the inductors as mentioned in the graphs. See
the TPS65720EVM User's Guide for details on the layout.
Table 8. Table Of Graphs
FIGURE
TPS65720: Efficiency DCDC1 vs Load Current / PWM mode 200 mA;
L = Murata LQM21P 3.3 μH
VO = 2.05 V; Vi = 3 V, 3.6 V, 4.2 V, 5 V
Figure 24
TPS65720: Efficiency DCDC1 vs Load Current / PFM mode 200 mA;
L = Murata LQM21P 3.3 μH
VO = 2.05 V; Vi = 3 V, 3.6 V, 4.2 V, 5 V
Figure 25
TPS65720: Efficiency DCDC1 vs Load Current / PWM mode 200 mA;
L = FDK MIPSA2520 2.2 μH
VO = 2.05 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 26
TPS65720: Efficiency DCDC1 vs Load Current / PFM mode 200 mA;
L = FDK MIPSA2520 2.2 μH
VO = 2.05 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 27
TPS65721: Efficiency DCDC1 vs Load Current / PWM mode;
L = FDK MIPSA2520 2.2 μH
VO = 3.3 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 28
TPS65721: Efficiency DCDC1 vs Load Current / PFM mode 500 mA;
L = FDK MIPSA2520 2.2 μH
VO = 3.3 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 29
TPS65721: Efficiency DCDC1 vs Load Current / PWM mode;
L = FDK MIPSA2520 2.2 μH
VO = 1.8 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 30
TPS65721: Efficiency DCDC1 vs Load Current / PFM mode 500 mA;
L = FDK MIPSA2520 2.2 μH
VO = 1.8 V; VI = 3 V, 3.6 V, 4.2 V, 5 V
Figure 31
Load Transient Response DCDC1;
L = FDK MIPSA2520 2.2 μH, PFM mode
Scope plot
IO = 20 mA to 180 mA; VO = 2.05 V; VI = 3.6 V
Figure 32
Load Transient Response DCDC1;
L = FDK MIPSA2520 2.2 μH, PWM mode
Scope plot
IO = 50 μA to 60 mA; VO = 2.05 V; VI = 3.6 V
Figure 33
Load Transient Response DCDC1;
L = FDK MIPSA2520 2.2 μH, PWM mode
Scope plot
IO = 40 mA to 360 mA; VO = 3.3 V; VI = 3.6 V
Figure 34
Line Transient Response DCDC1;
L = FDK MIPSA2520 2.2 μH, PWM mode
Scope plot; VO = 2.05 V
VI = 3.6 V to 5 V to 3.6 V; IO = 60 mA
Figure 35
Output Voltage Ripple in PFM Mode; DCDC1
Scope plot: VI = 3.6 V
VO = 2.05 V;
IO = 50 μA (PFM); IO = 60 mA (PWM)
Figure 36
Output Voltage Ripple in PWM Mode; DCDC1
Scope plot: VI = 3.6 V
VO = 2.05 V;
IO = 60 mA (PWM)
Figure 37
Load Transient Response LDO1
Scope plot; V = 1.85 V; VI = 2.05 V
I = 50 μA to 60 mA to 50 μA
Figure 38
Line Transient Response LDO1
Scope plot; VO = 1.85 V; VI = 5 V to 3.6 V to 5 V
Figure 39
Efficiency vs Lout for DCDC1 = 2.05 V, LDO1 = 1.85 V,
VinLDO = VDCDC1
52
Submit Documentation Feedback
Figure 40
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
100
100
VO = 2.05 V
VO = 2.05 V
VI = 2.5 V
90
90
VI = 2.5 V
VI = 3 V
80
80
VI = 3.6 V
60
70
Efficiency - %
70
Efficiency - %
VI = 3 V
VI = 4.2 V
50
VI = 5 V
40
VI = 3.6 V
60
VI = 4.2 V
50
30
30
20
20
10
10
0
0.00001
0.01
0.001
IO - Output Current - A
0.0001
PWM Mode
0.1
VI = 5 V
40
0
0.00001
1
Inductor: LQM21P 3.3 µH
Figure 24. TPS65720 Efficiency of DCDC1 vs Load Current
0.01
0.001
IO - Output Current - A
0.0001
PFM Mode
0.1
1
Inductor: LQM21P 3.3 µH
Figure 25. TPS65720 Efficiency of DCDC1 vs Load Current
100
100
VO = 2.05 V
VO = 2.05 V
90
90
VI = 2.5 V
VI = 2.5 V
80
80
VI = 3 V
60
50
VI = 4.5 V
40
VI = 5 V
40
20
20
10
10
0.01
0.001
IO - Output Current - A
PWM Mode
0.1
VI = 4.2 V
50
30
0.0001
VI = 5 V
0
0.00001
1
Inductor: MIPSA2520 2.2 µH
Figure 26. TPS65720 Efficiency of DCDC1 vs Load Current
VI = 3.6 V
60
30
0
0.00001
VI = 3 V
70
VI = 3.6 V
Efficiency - %
Efficiency - %
70
0.01
0.001
IO - Output Current - A
0.0001
PFM Mode
Inductor: MIPSA2520 2.2 µH
100
VO = 3.3 V
VO = 3.3 V
90
90
80
VI = 3.4 V
80
VI = 3.4 V
VI = 3.6 V
70
Efficiency - %
Efficiency - %
70
VI = 3.6 V
60
VI = 4.2 V
40
VI = 5 V
50
30
20
10
10
PWM Mode
0.01
0.001
IO - Output Current - A
0.1
1
Inductor: MIPSA2520 2.2 µH
Figure 28. TPS65721 Efficiency of DCDC1 vs Load Current
VI = 5 V
40
20
0.0001
VI = 4.2 V
60
30
0
0.00001
1
Figure 27. TPS65720 Efficiency of DCDC1 vs Load Current
100
50
0.1
0
0.00001
0.0001
PFM Mode
0.01
0.001
IO - Output Current - A
0.1
1
Inductor: MIPSA2520 2.2 µH
Figure 29. TPS65721 Efficiency of DCDC1 vs Load Current
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
53
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
100
100
VO = 1.8 V
VO = 1.8 V
80
70
VI = 3.6 V
60
VI = 4.2 V
50
VI = 5 V
40
VI = 5 V
20
10
10
PWM Mode
0.1
1
Inductor: MIPSA2520 2.2 µH
Figure 30. TPS65721 Efficiency of DCDC1 vs Load Current
VI = 4.2 V
40
20
0.01
0.001
IO - Output Current - A
VI = 3.6 V
50
30
0.0001
VI = 3 V
60
30
0
0.00001
VI = 2.5 V
80
VI = 3 V
70
Efficiency - %
90
VI = 2.5 V
Efficiency - %
90
0
0.00001
0.01
0.001
IO - Output Current - A
0.0001
PFM Mode
0.1
1
Inductor: MIPSA2520 2.2 µH
Figure 31. TPS65721 Efficiency of DCDC1 vs Load Current
VI = 3.6 V
VI = 3.6 V
IO = 20 mA to 180 mA
IO = 50 mA to 60 mA
VO = 2.05 V
VO = 2.05 V
Time - 100 ms/div
Time - 100 ms/div
Figure 32. Load Transient Response PFM Mode
VI = 3.6 V
Figure 33. Load Transient Response PWM Mode
IO = 60 mA
VI = 3.6 V to 5 V to 3.6 V
IO = 40 mA to 360 mA
VO = 3.3 V
VO = 2.05 V
Time - 100 ms/div
Time - 100 ms/div
Figure 34. Load Transient Response PWM Mode
54
Submit Documentation Feedback
Figure 35. Line Transient Response PWM Mode
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
VI = 3.6 V,
PWM IO = 60 mA
VI = 3.6 V,
PFM IO = 50 mA
VO = 2.05 V
VO = 2.05 V
20 mV/div
20 mV/div
Time - 2 ms/div
Time - 1 ms/div
Figure 36. Output Voltage Ripple on DCDC1 PFM Mode
Figure 37. Output Voltage Ripple on DCDC1 PWM Mode
VI = 2.05 V
IO = 60 mA
IO = 50 mA to 60 mA to 50 mA
VI = 5 V to 3.6 V to 5 V
VO = 1.85 V
VO = 1.85 V
Time - 40 ms/div
Time - 100 ms/div
Figure 38. Load Transient Response LDO1
Figure 39. Line Transient Response LDO1
100
90
VI = 3 V
VI = 3.6 V
80
70
Efficiency - %
VI = 2.5 V
VI = 4.2 V
60
VI = 5 V
50
40
30
20
10
0
0.00001
0.0001
0.01
0.001
IO - Output Current - A
LDO1 powered by DCDC1
with VDCDC1 = 2.05 V
0.1
1
VLDO1 = 1.85 V
Figure 40. Efficiency vs Output Current for the Complete System
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
55
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
10 Power Supply Recommendations
The TPS6572x device has two paths for input supply, battery and AC adaptor or USB input. The AC pin the main
input supply can be operated with a power supply from a USB or AC adaptor. The input voltage on the AC pin is
recommended to be operated with a voltage between the VAC_LOW and VOVP of the device for most cases and
charging capabilities. The battery can be supplied through the BAT pin and a Li-Ion signal cell battery is
recommended for most applications.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulators may show poor line or load regulation, and additional stability
issues as well as EMI problems. Providing a low impedance ground path is critical. Therefore, use wide and
short traces for the main current paths. The input capacitors must be placed as close as possible to the IC pins
as well as the inductor and output capacitor.
For TPS65721, connect the PGND pin of the device to the thermal pad land of the PCB and connect the analog
ground connection (GND) to the PGND at the thermal pad. Keep the common path to the GND pin, which returns
the small signal components, and the high current of the output capacitors as short as possible to avoid ground
noise. The FB line should be connected right to the output capacitor and routed away from noisy components
and traces (for example, the L1 line). See the TPS65720EVM User's Guide for details about the layout.
11.2 Layout Example
Csys
Csys
RSET
CAC
AC
SYS
CLDO
BAT
L1
LDO
VINL
DO
AGN
D
FB
PGN
D
Cbat
CLDO
ISET
CIN
R2
Cff
IND
R1
CDCDC
CDCDC
Figure 41. Layout Recommendation
56
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
TPS65720, TPS657201, TPS657202, TPS65721
www.ti.com
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Basic Calculation of a Buck Converter's Power Stage application report
• Texas Instruments, Dynamic Power-Path Management and Dynamic Power Management application report
• Texas Instruments, Optimizing Resistor Dividers at a Comparator Input application report
• Texas Instruments, TPS65720EVM user's guide
• Texas Instruments, TPS65720 Power Management IC (PMIC) for Wearable and Fitness Devices
• Texas Instruments, TPS65721EVM user's guide
• Texas Instruments, Understanding the Absolute Maximum Ratings of the SW Node application report
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65720
Click here
Click here
Click here
Click here
Click here
TPS65721
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
Submit Documentation Feedback
57
TPS65720, TPS657201, TPS657202, TPS65721
SLVS979C – OCTOBER 2009 – REVISED MAY 2018
www.ti.com
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
58
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS65720 TPS65721
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS657201YFFR
ACTIVE
DSBGA
YFF
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS657201
TPS657201YFFT
PREVIEW
DSBGA
YFF
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS657201
TPS657202YFFR
PREVIEW
DSBGA
YFF
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS657202
TPS657202YFFT
PREVIEW
DSBGA
YFF
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS657202
TPS65720YFFR
ACTIVE
DSBGA
YFF
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65720
TPS65720YFFT
ACTIVE
DSBGA
YFF
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65720
TPS65721RSNR
ACTIVE
QFN
RSN
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65721
TPS65721RSNT
ACTIVE
QFN
RSN
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65721
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
