TPS715
SLVS338S – MAY 2001 – REVISED AUGUST 2022
TPS715 50-mA, 24-V, 3.2-μA Quiescent Current, Low-Dropout Linear Regulator
1 Features
2 Description
•
•
•
•
•
The TPS715 low-dropout (LDO) linear voltage
regulators are low quiescent current devices that
offer the benefits of a wide input voltage range and
low-power operation in miniaturized packaging. The
low dropout voltage and low quiescent current of
the TPS715 allows operation at extremely low power
levels. Thus, the TPS715 is designed for batterypowered applications and as a power-management
attachment to low-power microcontrollers.
•
•
•
•
Input voltage range: 2.5 V to 24 V (30 V max)
Very low IQ: 3.2 μA at 50-mA load current
Output current: Up to 50 mA
Stable with output capacitor ≥ 0.47 μF
Available output voltage options:
– Fixed: 1.8 V, 1.9 V, 2.3 V, 2.5 V, 3 V,
3.3 V, 3.45 V, 5 V
– Adjustable: 1.2 V to 15 V
Overcurrent protection
Package: 5-pin SC70 (DCK)
Specified junction temperature: –40°C to +125°C
For an 80-mA rated current and higher power
package, see the TPS715A
Applications
Home and building automation
Retail automation and payment
Grid infrastructure
Medical applications
Lighting applications
Package Information(1)
PART NUMBER
TPS715
(1)
PACKAGE
SC70 (5)
BODY SIZE (NOM)
2.00 mm × 1.25 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS716
IN
Li-Ion
Battery
•
•
•
•
•
The TPS715 is available in both fixed and adjustable
versions. For more flexibility or higher output voltages,
the adjustable version uses feedback resistors to set
the output voltage from 1.205 V to 15 V. The TPS715
LDOs support a low dropout of typically 415 mV at
50 mA of load current. The low quiescent current
(3.2 μA typically) is stable over the entire range of
output load current (0 mA to 50 mA). The TPS715
also features an internal soft-start to lower the inrush
current. The built-in overcurrent limit helps protect the
regulator in the event of a load short or fault.
OUT
MCU
GND
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLVS338S – MAY 2001 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
Applications........................................................................ 1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Electrical Characteristics.............................................6
5.6 Typical Characteristics................................................ 7
6 Detailed Description......................................................10
6.1 Overview................................................................... 10
6.2 Functional Block Diagrams....................................... 10
6.3 Feature Description...................................................10
6.4 Device Functional Modes..........................................12
7 Application and Implementation.................................. 13
7.1 Application Information............................................. 13
7.2 Typical Application.................................................... 13
7.3 Best Design Practices...............................................18
7.4 Power Supply Recommendations.............................18
7.5 Layout....................................................................... 18
8 Device and Documentation Support............................20
8.1 Device Support......................................................... 20
8.2 Documentation Support............................................ 20
8.3 Receiving Notification of Documentation Updates....20
8.4 Support Resources................................................... 20
8.5 Trademarks............................................................... 20
8.6 Electrostatic Discharge Caution................................21
8.7 Glossary....................................................................21
9 Mechanical, Packaging, and Orderable Information.. 21
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (February 2015) to Revision S (August 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed document title......................................................................................................................................1
• Changed Features section..................................................................................................................................1
• Changed Applications section............................................................................................................................ 1
• Changed Description section..............................................................................................................................1
• Changed descriptions of FB and NC pins in Pin Functions table, split fixed and adjustable pin outs apart ...... 3
• Added M3-specific plots to Typical Characteristics section................................................................................ 7
• Changed Overview section...............................................................................................................................10
• Changed block diagrams in Functional Block Diagrams section...................................................................... 10
• Changed Low Quiescent Current section and title........................................................................................... 10
• Changed Dropout Voltage (VDO) section.......................................................................................................... 11
• Deleted Disabled row from Device Functional Mode Comparison table...........................................................12
• Changed Dropout Operation section................................................................................................................ 12
• Changed External Capacitor Requirements section.........................................................................................14
• Added Input and Output Capacitor Requirements section............................................................................... 14
• Changed Reverse Current section................................................................................................................... 14
• Changed output voltage value when no CFF is used from 0.8 V to 1.205 V .................................................... 15
• Added Power Dissipation (PD) section............................................................................................................. 15
• Added M3-specific plots to Application Curves section.................................................................................... 17
• Added second row and deleted second footnote from Device Nomenclature table......................................... 20
Changes from Revision Q (January 2014) to Revision R (February 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Changed front-page figure .................................................................................................................................1
• Changed Pin Configuration and Functions section; updated table format .........................................................3
2
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4 Pin Configuration and Functions
NC
1
GND
2
NC
3
5
OUT
4
IN
FB
1
GND
2
NC
3
Not to scale
5
OUT
4
IN
Not to scale
Figure 4-1. DCK Package (Fixed), 5-Pin SC70
(Top View)
Figure 4-2. DCK Package (Adjustable), 5-Pin SC70
(Top View)
Table 4-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
FIXED
ADJUSTABLE
FB
—
1
I
GND
2
2
—
IN
4
4
I
NC
1, 3
3
—
No connect pin. This pin is not connected internally. Connect to ground for best thermal
performance or leave floating.
5
5
O
Output of the regulator. Any output capacitor ≥ 0.47 μF can be used for stability.
OUT
In the adjustable configuration, this pin is used to set the output voltage with help of the feedback
divider. For the fixed output version, this pin can either be left floating or connected to GND.
Ground
Input supply
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5 Specifications
5.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1) (2)
MIN
Voltage
VIN
–0.3
30
VOUT
–0.3
VIN + 0.3
–0.3
4.5
VFB
Current
Peak output current
Temperature
(1)
(2)
MAX
UNIT
V
Internally limited
Junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground terminal.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VIN
Input supply voltage
VOUT
MAX
UNIT
24
Output voltage
1.205
15
V
IOUT
Output current
0
50
mA
CIN
Input capacitor(2)
COUT
Output capacitor(3)
TJ
Operating junction temperature
(1)
(2)
(3)
4
NOM
2.5
0
0.047
0.47
1
-40
V
µF
µF
125
°C
All voltages are with respect to GND.
An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.047 μF is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system
level instability such as ringing or oscillation, especially in the presence of load transients.
All capacitor values are assumed to derate to 50% of the nominal capacitor value.
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5.4 Thermal Information
THERMAL METRIC(1)
TPS715
TPS715M3
DCK
[SC70]
DCK
[SC70]
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
253.8
195.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.7
88.2
°C/W
RθJB
Junction-to-board thermal resistance
84.6
40.7
°C/W
ψJT
Junction-to-top characterization parameter
1.1
11.2
°C/W
ψJB
Junction-to-board characterization parameter
83.9
40.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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5.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 μF
(unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
VIN
Input voltage TPS715 (1)
VOUT
Output voltage Range
(TPS71501)
VOUT
Over VIN,
Accuracy (1) (2) IOUT, and
Temp
IGND
Ground pin current
ΔVOUT (ΔIOUT)
Load regulation
(3)
MIN
TYP
Output voltage line regulation
(1)
24
IO = 50 mA
3
24
1.2
15
V
–4
4
%
VOUT + 1 V ≤ VIN ≤ 24 V,
100 µA ≤ IOUT ≤ 50 mA
0 ≤ IOUT ≤ 50 mA , TJ = –40°C to
85°C
3.2
4.2
0 mA ≤ IOUT ≤ 50 mA
3.2
4.8
V
μA
5.8
IOUT = 100 μA to 50 mA
22
VOUT(NOM) + 1 V ≤ VIN ≤ 24 V
20
mV
60
mV
Vn
Output noise voltage (non-M3 BW = 200 Hz to 100 kHz,
device) (4)
COUT = 10 μF, IOUT = 50 mA
575
μVrms
Vn
Output noise voltage (M3
device)(4)
425
μVrms
ICL
PSRR
VDO
(1)
(2)
(3)
(4)
BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA
125
750
VOUT = 0 V, VIN < 3.5 V
90
750
Output current limit
(TPS715M3)
VOUT = 0 V, VIN ≥ 3.5 V
175
450
VOUT = 0 V, VIN < 3.5 V
90
Power-supply ripple rejection
f = 100 kHz, COUT = 10 μF
Output current limit (TPS715)
6
UNIT
2.5
0 mA ≤ IOUT ≤ 50 mA , VIN = 24 V
ΔVOUT (ΔVIN)
MAX
IO = 10 mA
Dropout
voltage
TPS715
Dropout
voltage
TPS715M3
VIN =
VOUT(nom) –
0.1 V
VOUT = 0 V, VIN ≥ 3.5 V
mA
450
60
415
dB
750
IOUT = 50 mA
mV
415
600
Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
For adjustable device, output accuracy excludes the tolerance and mismatch associated with external resistors used for setting up the
output voltage level.
See Figure 6.1 . The TPS715 family employs a leakage null control circuit. This circuit is active only if output current is less than pass
FET leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is
greater than 100°C.
See Section 10.1.2 for clarification about M3 and Non-M3 devices.
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5.6 Typical Characteristics
3.32
3.320
VIN = 4.3 V
COUT = 1 mF
TJ = 25°C
VIN = 4.3V
COUT = 1µF
T = 25°C
3.315
VOUT - Output Voltage - V
VOUT − Output Voltage − V
3.315
3.310
3.305
3.300
3.295
3.31
3.305
3.3
3.295
3.290
0
10
20
30
40
50
3.29
IO − Output Current − mA
0
Figure 5-1. Output Voltage vs Output Current
VOUT - Output Voltage - V
VOUT − Output Voltage − V
3.31
IOUT = 1 mA
3.30
IOUT = 50 mA
3.29
3.28
3.27
VIN = 4.3 V
COUT = 1 mF
50
1mA
50mA
3.3
3.29
3.28
3.27
3.26
3.25
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 5-3. Output Voltage vs Junction Temperature
3.25
-55
-25
5
35
65
95
TJ - Junction Temperature - °C
125
150
Figure 5-4. Output Voltage vs Junction Temperature for M3
Devices
4.5
4.5
VIN = 4.3 V
VOUT = 3.3 V
IOUT = 1 mF
IGND - Ground Current - µA
IGND − Ground Current − mA
40
3.32
3.31
4
20
30
IOUT - Output Current - mA
Figure 5-2. Output Voltage vs Output Current for M3 Devices
3.32
3.26
10
3.5
3
2.5
4
3.5
3
2.5
2
−40 −25 −10 5
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 5-5. Quiescent Current vs Junction Temperature
2
-55
-25
5
35
65
95
TJ - Junction Temperature - °C
125
150
Figure 5-6. Quiescent Current vs Junction Temperature for M3
Devices
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5.6 Typical Characteristics (continued)
Hz
8
VIN = 4.3 V
VOUT = 3.3 V
COUT = 1 mF
m V/
IOUT = 1 mA
Output Spectral Noise Density - µV/Hz
7
Output Spectral Noise Density −
6
5
IOUT = 50 mA
4
3
2
1
0
100
1k
10 k
f − Frequency − Hz
1
0.1
Integrated Noise from
200Hz to 100KHz
0.01
1mA : 583VRMS
50mA : 771VRMS
102
103
104
105
Frequency - Hz
106
107
Figure 5-8. Output Voltage Spectral Noise Density vs Frequency
for M3 Devices
600
600
VIN = 3.2 V
COUT = 1 mF
500
VDO - Dropout Voltage - mV
V DO − Dropout Voltage − mV
1mA
50mA
0.001
101
100 k
Figure 5-7. Output Voltage Spectral Noise Density vs Frequency
20
10
TJ = 125°C
400
TJ = 25°C
300
200
TJ = −40°C
100
-55°C
-40°C
0°C
500
400
25°C
85°C
125°C
150°C
VIN = 3.2V
COUT = 1µF
300
200
100
0
0
10
20
30
40
IOUT − Output Current − mA
50
0
0
Figure 5-9. Dropout Voltage vs Output Current
40
50
1000
1
IOUT = 50 mA
VDO - Dropout Voltage - mV
TJ = 125°C
0.7
TJ = 25°C
0.6
0.5
0.4
IOUT = 50mA
900
0.8
V DO − Dropout Voltage − V
20
30
IOUT - Output Current - mA
Figure 5-10. Dropout Voltage vs Output Current for M3 Devices
0.9
TJ = −40°C
0.3
0.2
0.1
800
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
700
600
500
400
300
200
100
0
0
3
6
9
12
15
VIN − Input Voltage − V
0
0
Figure 5-11. TPS71501 Dropout Voltage vs Input Voltage
8
10
2.5
5
7.5
10
VIN - Input Voltage - V
12.5
15
Figure 5-12. TPS71501 Dropout Voltage vs Input Voltage for M3
Devices
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5.6 Typical Characteristics (continued)
600
600
10mA
50mA
500
VDO - Dropout Voltage - mV
V DO − Dropout Voltage − mV
VIN = 3.2 V
IOUT = 50 mA
400
300
200
IOUT = 10 mA
100
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
300
200
100
-25
5
35
65
95
TJ - Junction Temperature - °C
125
150
Figure 5-14. Dropout Voltage vs Junction Temperature for M3
Devices
100
100
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
TJ = 25°C
90
80
Power Supply Ripple Rejection - dB
PSRR − Power Supply Ripple Rejection − dB
400
0
-55
TJ − Junction Temperature − °C
Figure 5-13. Dropout Voltage vs Junction Temperature
500
70
60
IOUT = 1 mA
50
40
30
20
IOUT = 50 mA
10
0
10
100
1k
10k
100k
1M
10 M
f − Frequency − Hz
Figure 5-15. Power-Supply Ripple Rejection vs Frequency
1mA
50mA
90
80
70
60
50
40
30
20
10
VIN = 6 V
VOUT = 5 V
COUT = 10uF
0
101
102
103
104
105
Frequency - Hz
106
107
Figure 5-16. Power-Supply Ripple Rejection vs Frequency for
M3 Devices
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6 Detailed Description
6.1 Overview
The TPS715 family of low-dropout regulators (LDOs) consume only 3.2 μA of quiescent current across the entire
output current range, while offering a wide input voltage range and low-dropout voltage in a small package.
The devices, which operate over an input range of 2.5 V to 24 V, are stable with any output capacitor greater
than or equal to 0.47 μF. The low quiescent current across the complete load current range, makes the TPS715
designed for powering battery-operated applications. The TPS715 family has internal soft-start to control inrush
current into the output capacitor. These LDOs also have overcurrent protection during a load-short or fault
condition on the output.
6.2 Functional Block Diagrams
V(IN)
V(OUT)
Current
Sense
Leakage Null
Control Circuit
R1
GND
–
+
ILIM
GND
FB
GND
R2
Bandgap
Reference
VREF = 1.205 V
GND
Figure 6-1. Functional Block Diagram—Adjustable Version
V(IN)
V(OUT)
Current
Sense
Leakage Null
Control Circuit
–
+
R1
GND
ILIM
GND
GND
R2
Bandgap
Reference
VREF = 1.205 V
GND
Figure 6-2. Functional Block Diagram—Fixed Version
6.3 Feature Description
6.3.1 Wide Supply Range
This device has an operational input supply range of 2.5 V to 24 V, allowing for a wide range of applications. This
wide supply range is designed for applications that have either large transients or high DC voltage supplies.
6.3.2 Low Quiescent Current
This device only requires 3.2 μA (typical) of quiescent current across the complete load current range (0 mA to
50 mA) from –40°C to +85°C and has a maximum current consumption of 5.8 μA at –40°C to +125°C.
10
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6.3.3 Dropout Voltage (VDO)
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. In dropout operation, the pass transistor is in the ohmic or triode region of operation,
and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal
programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls
to less than the value required to maintain output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (RDS(ON)) of
the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage
for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
(1)
6.3.4 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 6-3 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 6-3. Current Limit
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6.4 Device Functional Modes
Table 6-1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 6-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
IOUT
Normal
VIN > VOUT(nom) + VDO
IOUT < ICL
Dropout
VIN < VOUT(nom) + VDO
IOUT < ICL
6.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than 125°C
6.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
12
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7 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 Application Information
The TPS715 family of LDO regulators is a good choice for battery powered applications as well as a good
attachment to low power micro-controllers such as MSP430, due to its low IQ performance across load current
range. The ultra-low-supply current of the TPS715 device maximizes efficiency at light loads, its high input
voltage range makes and flexibility of output voltage selection in adjustable configuration and fixed output levels
makes the device suitable for supplies such as unconditioned solar panels.
7.2 Typical Application
VIN
IN
C1
0.1 mF
TPS71533
OUT
GND
VOUT
0.47 mF
Figure 7-1. Typical Application Circuit (Fixed-Voltage Version)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
IN
VOUT
OUT
TPS71501
R1
0.1mF
GND
CFB
0.47mF
FB
R2
R1 ö
æ
VOUT = VREF ´ ç 1 +
÷
è R2 ø
OUTPUT
VOLTAGE
R1
R2
1.8 V
0.499 MW
1 MW
2.8 V
1.33 MW
1 MW
5.0 V
3.16 MW
1 MW
Figure 7-2. TPS71501 Adjustable LDO Regulator Programming
7.2.1 Detailed Design Procedure
7.2.1.1 Setting VOUT for the TPS71501 Adjustable LDO
The TPS715 family contains an adjustable version, the TPS71501, which sets the output voltage using an
external resistor divider as shown in Figure 7-2. The output voltage operating range is 1.2 V to 15 V, and is
calculated using:
R1 ö
æ
VOUT = VREF ´ ç 1 +
÷
è R2 ø
(2)
where:
•
VREF = 1.205 V (typical)
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Choose resistors R1 and R2 allows approximately 1.5 μA of current through the resistor divider. Lower value
resistors can be used for improved noise performance, but consume more power. Avoid higher resistor values
because leakage current into or out of FB across R1 / R2 creates an offset voltage that is proportional to VOUT
divided by VREF. The recommended design procedure is to choose R2 = 1 MΩ to set the divider current at
1.5 μA, and then calculate R1 using Equation 3:
V
R1 = VOUT − 1 × R2
REF
(3)
Figure 7-2 depicts this configuration.
7.2.1.2 External Capacitor Requirements
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
7.2.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
7.2.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
PMOS pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades
the long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V. These conditions are:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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Figure 7-3 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
CIN
COUT
GND
GND
GND
GND
Figure 7-3. Example Circuit for Reverse Current Protection Using a Schottky Diode
7.2.1.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.
CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π × CFF × R1)
(4)
fP = 1 / (2 × π × CFF × (R1 || R2))
(5)
CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 μA. Equation 6 calculates the
feedback divider current.
IFB_Divider = VOUT / (R1 + R2)
(6)
To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs.
For an output voltage of 1.205 V with the FB pin tied to the OUT pin, no CFF is used.
7.2.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(7)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
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The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(8)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
7.2.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(9)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(10)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
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7.2.2 Application Curves
8
8
VOUT = 3.3 V
RL = 66 W
COUT = 10 mF
5
4
3
VIN
2
VOUT
1
6
5
4
3
2
0
2
4
6
8 10 12 14
t − Time − ms
16 18
20
0
0
2
4
6
8
10 12 14
t - Time - ms
16
10
VOUT = 3.3 V
IOUT = 50 mA
COUT = 10 mF
100
50
−50
5.3
20
150
VIN
VOUT 100
9.5
0
18
22
Figure 7-5. Power-Up and Power-Down for M3
Devices
VIN - Input Voltage - V
9
50
8.5
0
8
-50
VOUT = 5V
IOUT = 50mA
COUT = 10F
dV/dt = 0.2V/s
7.5
7
-100
-150
6.5
-200
6
-250
4.3
0
5.5
50 100 150 200 250 300 350 400 450 500
0
50
100
t − Time − ms
Figure 7-6. Line Transient Response
150
200 250 300
t - Time - µs
350
VIN = 6V
VOUT = 5V
COUT = 10F
dI/dt = 0.5A/s
140
IOUT - Output Current - mA
200
0
-200
60
40
20
0
0 100 200 300 400 500 600 700 800 900 1000
ms
t − Time −
Figure 7-8. Load Transient Response
450
-300
500
Figure 7-7. Line Transient Response for M3
Devices
160
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
400
400
120
100
600
IOUT
VOUT 400
200
0
80
-200
60
-400
40
-600
20
-800
0
0
300
600
AC Coupled Output Voltage - mV
VIN − Input Voltage − V
∆VOUT − Change in
Output Voltage − mV
Figure 7-4. Power-Up and Power-Down
DVOUT - Change in
Output Voltage - mV
VOUT
1
0
IOUT - Output Current - mA
VIN
AC Coupled Output Voltage - mV
VIN − Input Voltage − V
VOUT − Output Voltage − V
6
VOUT = 5 V
IOUT = 50 mA
COUT = 10 µF
7
VOUT - Output Voltage - V
VIN - Input Voltage - V
7
-1000
900 1200 1500 1800 2100 2400 2700 3000
t - Time - us
Figure 7-9. Load Transient Response for M3
Devices
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30
7
6
20
5
15
4
10
3
5
2
0
VOUT - Output Voltage - V
25
VIN - Inout Voltage - V
VIN
VOUT
IOUT = 50mA
COUT = 10F
dV/dt = 0.66V/s
1
0
0.5
1
1.5
2
2.5
t - Time - ms
3
3.5
4
Figure 7-10. Dropout Exit Transient Response for M3 Devices
7.3 Best Design Practices
Place at least one 0.47-µF capacitor as close as possible to the OUT and GND terminals of the regulator.
Do not connect the output capacitor to the regulator using a long, thin trace.
Connect an input capacitor as close as possible to the IN and GND terminals of the regulator for best
performance.
Do not exceed the absolute maximum ratings.
7.4 Power Supply Recommendations
The TPS715 is designed to operate from an input voltage supply range between 2.5 V and 24 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
7.5 Layout
7.5.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the printed-circuit-board and
as near as practical to the respective LDO pin connections. Place ground return connections for the input
and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do
not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the
resistor divider because this practice negatively affects system performance. This grounding and layout scheme
minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases
circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or
located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy
of the output voltage and shield the LDO from noise.
7.5.1.1 Power Dissipation
To ensure reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the
power dissipation the regulator can handle in any given application. To ensure the junction temperature is within
acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which
must be less than or equal to PD(max).
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The maximum-power-dissipation limit is determined using Equation 11:
PD(max) =
TJ max - TA
RqJA
(11)
where
•
•
•
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable)
TA is the ambient temperature
The regulator dissipation is calculated using Equation 12:
PD = (VIN - VOUT ) ´ IOUT
(12)
For a higher power package version of the TPS715, see the TPS715A.
7.5.2 Layout Example
GND
R2
NC
CIN
VIN
GND
FB
TPS71501DCK
IN
R1
OUT
COUT
GND
VOUT
Figure 7-11. Example Layout for the TPS71501DCK
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
8.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS715.
The TPS71533EVM evaluation module (and related user's guide) can be requested at the TI website through the
product folders or purchased directly from the TI eStore.
8.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS715 is available through the product folders under Tools
& Software.
8.1.2 Device Nomenclature
Table 8-1. Device Nomenclature(1)
PRODUCT
TPS715xx yyy z
TPS715xxyyyxM3
(1)
VOUT
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
M3 is a suffix designator for newer high density chip re-designs, fabricated on the latest
TI process technology. Compared to Non-M3 devices, M3 devices support similar or better
performance.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS71533EVM LDO Evaluation Module user guide
• Texas Instruments, TPS735 High Input Voltage, Micropower SON-Packaged, 80-mA LDO Linear Regulators
data sheet
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PTPS71501DCKRM3
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 125
Samples
PTPS71533DCKRM3
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 125
Samples
PTPS71550DCKRM3
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 125
Samples
TPS71501DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ARB
Samples
TPS71501DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ARB
Samples
TPS71518DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ARD
Samples
TPS71518DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ARD
Samples
TPS71519DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
BOX
Samples
TPS71523DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
BNX
Samples
TPS71525DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AQL
Samples
TPS71525DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
AQL
Samples
TPS71530DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AQM
Samples
TPS71530DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
AQM
Samples
TPS71533DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AQI
Samples
TPS71533DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AQI
Samples
TPS715345DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
BNY
Samples
TPS71550DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
T48
Samples
TPS71550DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
T48
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
NIPDAUAG
NIPDAUAG
NIPDAUAG
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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