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TPS720
SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
TPS720 350 mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator With Bias Pin
1 Features
•
•
•
1
•
•
•
•
•
•
•
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•
350-mA High-Performance LDO
Low Quiescent Current: 38 μA
Excellent Load Transient Response:
±15 mV for ILOAD = 0 mA to 350 mA in 1 μs
Excellent Line Transient Response:
ΔVOUT = ±2 mV for ΔVBIAS = ±600 mV in 1 μs
ΔVOUT = ±200 μV for ΔVIN = ±400 mV in 1 μs
Low Noise: 48 μVRMS (10 Hz to 100 kHz)
80 dB VIN PSRR (10 Hz to 10 kHz)
70 dB VBIAS PSRR (10 Hz to 10 kHz)
Fast Start-Up Time: 140 μs
Built-In Soft-Start With Monotonic VOUT Rise and
Start-Up Current Limited to 100 mA + ILOAD
Overcurrent and Thermal Protection
Low Dropout: 110 mV at ILOAD = 350 mA
Stable with 2.2-μF Output Capacitor
Available in 1.33 mm × 0.96 mm DSBGA-5 and 2
mm × 2 mm SON-6 Packages
The TPS720 supports a novel feature in which the
output of the LDO regulates under light loads when
the IN pin is left floating. The light-load drive current
is sourced from VBIAS under this condition. This
feature is particularly useful in power-saving
applications where the DC-DC converter connected
to the IN pin is disabled but the LDO is still required
to regulate the voltage to a light load.
The TPS720 is stable with ceramic capacitors and
uses an advanced BICMOS fabrication process that
yields a dropout of 110 mV at a 350-mA output load.
The TPS720 has the unique feature of providing a
monotonic VOUT rise (overshoot limited to 3%) with
VIN inrush current limited to 100 mA + ILOAD with an
output capacitor of 2.2 μF.
The TPS720 uses a precision voltage reference and
feedback loop to achieve overall accuracy of 2% over
load, line, process, and temperature extremes. An
ultra-small DSBGA package makes the TPS720 ideal
for handheld applications. The TPS720 is also
available in a SON-8 package. This family of devices
is fully specified over the temperature range of
TJ = –40°C to 125°C.
2 Applications
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•
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•
Digital Cameras
Cellular Camera Phones
Wireless LAN
Handheld Products
Device Information(1)
PART NUMBER
TPS720
BODY SIZE (NOM)
1.36 mm × 0.96 mm
SON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
Simplified Schematic
The TPS720 family of dual rail, low-dropout linear
regulators (LDOs) offers outstanding ac performance
(PSRR, load and line transient response), while
consuming a very low quiescent current of 38 μA.
The VBIAS rail that powers the control circuit of the
LDO draws very low current (on the order of the
quiescent current of the LDO) and can be connected
to any power supply that is equal to or greater than
1.4 V above the output voltage. The main power path
is through VIN, which can be a lower voltage than
VBIAS; it can be as low as VOUT + VDO, increasing the
efficiency of the solution in many power-sensitive
applications. For example, VIN can be an output of a
high-efficiency, DC-DC step-down regulator.
PACKAGE
DSBGA (5)
VBATT
CBIAS
BIAS
Standalone
dc/dc
Converter
or PMU
1.8 V
IN
OUT
1.3 V
VCORE
TPS720xx
CIN
EN
GND
COUT
VEN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS720
SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
5
7
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
17
17
17
18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
12.1 Package Mounting ................................................ 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2009) to Revision E
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision C (September, 2008) to Revision D
Page
•
Added electrical specifications for DRV package ................................................................................................................... 5
•
Noted electrical specifications for YZU package .................................................................................................................... 5
2
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SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DRV Package
6-Pin SON With Exposed Thermal Pad
Top View
OUT
1
NC
2
EN
3
Thermal
Pad
(1)
6
IN
5
GND
4
BIAS
YZU Package
5-Pin DSBGA
Top View
C3
C1
BIAS
EN
B2
GND
A3
A1
OUT
(1)
IN
TI recommends connecting the SON (DRV)
package thermal pad to ground.
Pin Functions
PIN
I/O
DESCRIPTION
A3
O
Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground, for stability and to provide
load transients. See Input and Output Capacitor Requirements.
2
—
—
No connection.
EN
3
C3
I
Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to
OUT. A logic low on this pin turns off the device.
BIAS
4
C1
I
Bias supply pin. TI recommends bypassing this input with a ceramic capacitor to ground for better
transient performance. See Input and Output Capacitor Requirements.
GND
5
B2
—
IN
6
A1
I
NAME
DRV
YZU
OUT
1
NC
Ground pin.
Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a
ceramic capacitor to ground. See Input and Output Capacitor Requirements.
6 Specifications
6.1 Absolute Maximum Ratings
At TJ = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND. (1)
VIN (2)
Input voltage (steady-state)
VIN_PEAK (4)
Peak transient input
VBIAS
Bias voltage
VEN
Enable voltage
VOUT
Output voltage
IOUT
Peak output current
MIN
MAX
UNIT
–0.3
VBIAS or 5 (3)
V
5.5
V
–0.3
6
V
–0.3
6
V
–0.3
5
V
Internally limited
Output short circuit duration
Indefinite
PDISS
Total continuous power dissipation
TJ
Operating junction temperature
–55
125
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
(3)
(4)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To ensure proper operation of the device it is necessary that VIN ≤ VBIAS under all conditions.
Whichever is less.
For durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device.
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SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
Machine model (MM)
±100
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage (steady-state)
VBIAS
Bias voltage
VOUT
Output voltage
IOUT
Peak output current
CIN
Input capacitance
CBIAS
Bias capacitance
COUT (3)
Output capacitance
(1)
(2)
(3)
NOM
MAX
UNIT
1.1
VBIAS or 4.5 (1)
V
2.5 or or VOUT + 1.4 (2)
5.5
V
0.9
3.6
V
0
350
mA
1
µF
0.1
µF
2.2
µF
Whichever is less
Whichever is greater
Maximum ESR should be less than 250 mΩ.
6.4 Thermal Information
TPS720
THERMAL METRIC (1)
DRV (SON)
YZU (WSCP)
6 PINS
5 PINS
UNIT
144.9
°C/W
RθJA
Junction-to-ambient thermal resistance
66.5
RθJC(top)
Junction-to-case (top) thermal resistance
86.2
1.1
°C/W
RθJB
Junction-to-board thermal resistance
36.1
27.5
°C/W
ψJT
Junction-to-top characterization parameter
1.7
4.1
°C/W
ψJB
Junction-to-board characterization parameter
36.6
27.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.4
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V ) or 2.5 V (whichever is greater); VIN ≥ VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN
Input voltage
1.1 (1)
VBIAS or
4.5 (2)
VBIAS
Bias voltage
2.5
5.5
Output voltage (4)
0.9
3.6
–3
3
VOUT (3)
ΔVOUT/ΔVIN
Output
accuracy
Nominal
TJ = 25°C
Over VBIAS, VIN, IOUT,
TJ = –40°C to 125°C
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA
–2%
2%
Over VBIAS, VIN, IOUT,
TJ = –40°C to 125°C
DRV package only:
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA,
VOUT < 1.2 V
–25
25
Over VBIAS, VIN, IOUT,
TJ = –10°C to 85°C
YZU package only:
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA
1.6 V ≤ VOUT ≤ 3.3 V
–1%
1%
VIN floating
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
0 μA ≤ IOUT ≤ 500 μA
VIN line regulation
ΔVOUT/ΔVBIAS VBIAS line regulation
UNIT
V
V
V
mV
mV
±1%
VIN = (VOUT + 0.5 V) to 4.5 V, IOUT = 1 mA
16
μV/V
VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is
greater) to 5.5 V, IOUT = 1 mA
16
μV/V
VIN line transient
ΔVIN = 400 mV, tRISE = tFALL = 1 μs
±200
μV
VBIAS line transient
ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs
±0.8
mV
Load regulation
0 mA ≤ IOUT ≤ 350 mA (no load to full load)
–15
μV/mA
Load transient
0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs
±15
mV
VDO_IN
VIN dropout voltage (5)
VIN = VOUT(NOM) – 0.1 V,
(VBIAS – VOUT(NOM)) = 1.4 V,
IOUT = 350 mA
110
VDO_BIAS
VBIAS dropout voltage (6)
VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
ΔVOUT/ΔIOUT
PSRR
(1)
(2)
(3)
(4)
(5)
(6)
VIN power-supply rejection ratio
420
200
1.09
1.4
V
525
800
mA
IOUT = 100 μA
38
IOUT = 0 mA to 350 mA
54
80
0.5
2
VEN ≤ 0.4 V, TJ = –40°C to 85°C
VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
mV
f = 10 Hz
85
f = 100 Hz
85
f = 1 kHz
85
f = 10 kHz
80
f = 100 kHz
70
f = 1 MHz
50
μA
μA
dB
Performance specifications are ensured up to a minimum VIN = VOUT + 0.5 V.
Whichever is less.
Minimum VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater) and VIN= VOUT + 0.5 V.
VO nominal value is factory programmable through the onchip EEPROM.
Measured for devices with VOUT(NOM) ≥ 1.2 V.
VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1 V. Measured for devices with VOUT(NOM) ≥ 1.8 V.
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Electrical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V ) or 2.5 V (whichever is greater); VIN ≥ VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
PSRR
VBIAS power-supply rejection ratio
TEST CONDITIONS
VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
MIN
TYP
f = 10 Hz
80
f = 100 Hz
80
f = 1 kHz
75
f = 10 kHz
65
f = 100 kHz
55
f = 1 MHz
35
VN
Output noise voltage
BW = 10 Hz to 100 kHz, VBIAS ≥ 2.5 V,
VIN = VOUT + 0.5 V
IVIN_INRUSH
Inrush current on VIN
VBIAS = (VOUT +1.4 V) or 2.5 V (whichever is
greater), VIN = VOUT + 0.5 V
tSTR
Start-up time
VOUT = 95% VOUT(NOM), IOUT = 350 mA,
COUT = 2.2 μF
VEN(HI)
Enable pin high (enabled)
1.1
VEN(LO)
Enable pin low (disabled)
0
IEN
Enable pin current
VEN = 5.5 V , VIN = 4.5 V, VBIAS = 5.5 V
Undervoltage lockout
VBIAS rising
Hysteresis
VBIAS falling
150
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
UVLO
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
6
2.41
UNIT
dB
48
–40
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MAX
μVRMS
100 +
ILOAD
mA
140
μs
V
2.45
0.4
V
1
μA
2.49
V
mV
°C
125
°C
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SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater); VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1.40
1.40
1.38
1.38
1.36
1.36
-40°C
1.32
1.30
1.28
+105°C
1.26
1.32
1.30
1.28
+105°C
+125°C
1.24
1.22
1.22
1.20
1.20
2.5
3.0
3.5
4.5
4.0
2.5
3.0
3.5
VIN (V)
IOUT = 350 mA
Figure 1. VIN Line Regulation (TPS72013YZU)
1.40
1.38
1.38
+85°C
-10°C
+25°C
1.34
1.36
-40°C
1.32
1.30
1.28
+105°C
1.26
1.30
1.28
+105°C
+125°C
1.24
1.22
-40°C
1.32
1.26
+125°C
1.24
+85°C
-10°C
+25°C
1.34
VOUT (V)
VOUT (V)
Figure 2. VIN Line Regulation (TPS72013YZU)
1.40
1.36
4.5
4.0
VIN (V)
IOUT = 0 mA
1.22
1.20
1.20
2.5
3.0
3.5
4.5
4.0
5.5
5.0
2.5
3.0
3.5
5.5
IOUT = 350 mA
Figure 3. VBIAS Line Regulation (TPS72013YZU)
Figure 4. VBIAS Line Regulation (TPS72013YZU)
1.40
1.40
1.38
1.38
+85°C
-10°C
+25°C
1.34
5.0
VBIAS (V)
IOUT = 0 mA
1.36
4.5
4.0
VBIAS (V)
1.36
-40°C
1.32
1.30
1.28
+105°C
1.26
1.30
1.28
+105°C
+125°C
1.24
1.22
-40°C
1.32
1.26
+125°C
1.24
+85°C
+25°C -10°C
1.34
VOUT (V)
VOUT (V)
-40°C
1.26
+125°C
1.24
+85°C
-10°C
+25°C
1.34
VOUT (V)
VOUT (V)
+85°C
-10°C
+25°C
1.34
1.22
1.20
1.20
0
1
2
3
4
5
6
7
8
9
10
0
IOUT (mA)
50
100
150
200
250
300
350
IOUT (mA)
Figure 5. Load Regulation Under Light Loads
(TPS72013YZU)
Figure 6. Load Regulation (TPS72013YZU)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater); VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1.40
1.40
TJ = +25°C
1.38
1.36
1.36
1.34
VBIAS = 3.0V
1.32
VBIAS = 4.0V
1.34
VBIAS = 5.0V
VOUT (V)
VOUT (mA)
VBIAS = 2.7V
1.38
1.30
1.28
TJ = +125°C
1.32
1.30
TJ = -40°C
1.28
TJ = +25°C
1.26
1.26
1.24
VBIAS = 2.7V
1.22
VBIAS = 3.5V
0
0.5
1.0
1.5
2.0
2.5
3.0
TJ = +85°C
1.22
VBIAS = 5.5V
1.20
TJ = 0°C
1.24
VBIAS = 4.5V
TJ = +105°C
1.20
4.0
3.5
0
0.1
0.2
0.3
0.4
IOUT (mA)
Figure 7. Load Regulation With VIN Floating (TPS72013YZU)
0.7
0.8
0.9
1.0
1.15
+125°C
+105°C
120
100
80
60
-10°C -40°C
+25°C
40
VDO_BIAS = VBIAS - VOUT (V)
1.14
140
VDO_IN (mV)
0.6
Figure 8. Load Regulation With VIN Floating (TPS72013YZU)
160
+85°C
20
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
VOUT = VOUT(NOM) - 0.1
IOUT = 350mA
1.05
1.04
0
0
50
100
150
200
250
300
350
-40 -25 -10
5
20
IOUT (mA)
35
50
65
80
95
110 125
TJ (°C)
Figure 9. VIN Dropout Voltage vs Output Current
(TPS72013YZU)
Figure 10. VBIAS Dropout Voltage vs Temperature
(TPS72033YZU)
1.345
50
45
1.325
IOUT = 1mA
40
IOUT = 0mA
35
IOUT = 1mA
1.305
IGND (mA)
VOUT (V)
0.5
IOUT (mA)
1.285
IOUT = 350mA
30
25
20
+125°C +105°C
+85°C
+25°C
-10°C
-40°C
15
1.265
10
5
1.245
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
2.5
TJ (°C)
3.5
4.0
4.5
5.0
5.5
VBIAS (V)
Figure 11. Output Voltage vs Temperature (TPS72013YZU)
8
3.0
Figure 12. Ground Pin Current vs VBIAS Input Voltage
(TPS72013YZU)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater); VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
70
60
IOUT = 350mA
60
+125°C +105°C
+85°C
50
+25°C
40
IGND (mA)
IGND (mA)
50
40
30
20
-40°C
-10°C
20
30
10
10
0
0
0
50
100
150
200
250
350
300
-40 -25 -10
5
20
35
50
65
80
95
110 125
IOUT (mA)
TJ (°C)
Figure 13. Ground Pin Current vs Output Current
(TPS72013YZU)
Figure 14. Ground Pin Current vs Temperature
(TPS72013YZU)
3.0
675
2.5
650
-10°C
+25°C
-40°C
+25°C
-10°C
-40°C
+85°C
1.5
+125°C
ICL (mA)
ISHDN (mA)
2.0
625
600
1.0
+85°C
+105°C
+105°C
+125°C
575
0.5
0
550
2.5
3.0
3.5
4.5
4.0
5.0
5.5
2.5
3.0
3.5
VBIAS (V)
Figure 15. Shutdown Current vs VBIAS Input Voltage
(TPS72013YZU)
5.0
5.5
Figure 16. Current Limit vs VBIAS Input Voltage
(TPS72013YZU)
675
120
-10°C
+25°C
4.5
4.0
VBIAS (V)
-40°C
100
650
(VIN - VOUT) = 0.5V
(VBIAS - VOUT) = 1.4V
IOUT = 0mA
PSRR (dB)
ICL (mA)
80
625
600
+85°C
+105°C
IOUT = 50mA
60
IOUT = 350mA
40
+125°C
575
20
550
0
2.5
3.0
3.5
4.5
4.0
10
VIN (V)
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 17. Current Limit vs VIN Input Voltage
(TPS72013YZU)
Figure 18. VIN Power-Supply Ripple Rejection vs Frequency
(TPS72015YZU)
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TPS720
SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater); VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
100
100
IOUT = 350mA
(VIN - VOUT) = 350mV
80
80
PSRR (dB)
PSRR (dB)
IOUT = 1mA
60
(VIN - VOUT) = 300mV
40
60
40
(VIN - VOUT) = 250mV
IOUT = 350mA
20
20
(VIN - VOUT) = 0.5V
(VBIAS - VOUT) = 1.4V
0
0
10
100
1k
10k
100k
1M
10M
10
100
1k
Frequency (Hz)
Figure 19. VIN Power-Supply Ripple Rejection
vs Frequency (TPS72015YZU)
Output Spectral Noise Density (mV/ÖHz)
10k
100k
1M
10M
Frequency (Hz)
Figure 20. VBIAS Power-Supply Ripple Rejection vs
Frequency (TPS72015YZU)
10
VOUT = 1.3V
IIN-PEAK = 110mA
1
IIN
50mA/div
0.1
EN
500mV/div
200mV/div
VOUT
0.01
100
1k
100k
10k
20ms/div
Frequency (Hz)
VIN = 1.8 V
IOUT = 0 mA
Figure 21. Output Spectral Noise Density vs Frequency
(TPS72015YZU)
VOUT = 1.3 V
VBIAS = 2.7 V
Figure 22. VIN Inrush Current
VOUT = 1.3V
IIN-PEAK = 400mA
1mV/div
VOUT
IIN
200mA/div
2.0V
EN
500mV/div
200mV/div
200mV/div
VIN 1.6V
VOUT
100ms/div
20ms/div
VIN = 1.8 V
IOUT = 350 mA
VOUT = 1.3 V
VBIAS = 2.7 V
VIN
VIN = 1.6 to 2 V
Slew Rate = 1 V/μs
VBIAS = 2.7 V
Figure 24. VIN Line Transient Response
Figure 23. VIN Inrush Current
10
VOUT = 1.3 V
IOUT = 350 mA
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TPS720
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SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater); VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1mV/div
VOUT
10mV/div
VOUT
3.3V
200mV/div
300mA
VBIAS 2.7V
100mA/div
IOUT 0mA
100ms/div
VIN = 1.8 V
VOUT = 1.3 V
VBIAS Slew Rate = 600 m/μs
100ms/div
VBIAS = 2.7 V to 3.3 V
IOUT = 350 mA
VIN = 1.8 V
tRISE = 1 μs
Figure 25. VBIAS Line Transient Response
VOUT = 1.3 V
VBIAS = 2.7 V
Figure 26. Load Transient Response
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Product Folder Links: TPS720
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TPS720
SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The TPS720 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve ultrawide bandwidth and high loop gain, resulting in extremely high PSRR (up to 1 MHz) at very low headroom (VIN –
VOUT). The implementation of the BIAS pin on the TPS720 vastly improves efficiency of low VOUT applications by
allowing the use of a preregulated, low-voltage input supply. The TPS720 supports a novel feature in which the
output of the LDO regulates under light loads (
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