Sample &
Buy
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
TPS720-Q1
350-mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator With BIAS Pin
1 Features
3 Description
•
•
The TPS720-Q1 family of dual-rail, low-dropout linear
regulators (LDOs) offers outstanding ac performance
(PSRR, load and line transient response) and
consume a very low quiescent current of 38 μA.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
Input Voltage Range: 1.1 V to 4.5 V
Output Voltage Range: 0.9 V to 3.6 V
High-Performance LDO: 350 mA
Low Quiescent Current: 38 μA
Excellent Load Transient Response:
±15 mV for ILOAD = 0 mA to 350 mA in 1 μs
Low Noise: 48 μVRMS (10 Hz to 100 kHz)
80-dB VIN PSRR (10 Hz to 10 kHz)
70-dB VBIAS PSRR (10 Hz to 10 kHz)
Fast Start-Up Time: 140 μs
Built-In Soft-Start With Monotonic VOUT Rise and
Start-Up Current Limited to 100 mA + ILOAD
Overcurrent and Thermal Protection
Low Dropout: 110 mV at ILOAD = 350 mA
Stable With a 2.2-μF Output Capacitor
Package: 2.00 mm × 2.00 mm, 6-Pin WSON
2 Applications
•
•
•
•
The VBIAS rail that powers the control circuit of the
LDO draws very low current (on the order of the LDO
quiescent current) and can be connected to any
power supply that is equal to or greater than 1.4 V
above the output voltage. The main power path is
through VIN and can be a lower voltage than VBIAS;
this path can be as low as VOUT + VDO, increasing the
efficiency of the solution in many power-sensitive
applications. For example, VIN can be an output of a
high-efficiency, dc-dc, step-down regulator.
The TPS720-Q1 supports a novel feature where the
output of the LDO regulates under light loads when
the IN pin is left floating. The light-load drive current
is sourced from VBIAS under this condition. This
feature is particularly useful in power-saving
applications where the dc-dc converter connected to
the IN pin is disabled but the LDO is still required to
regulate the voltage to a light load.
The TPS720-Q1 is stable with ceramic capacitors and
uses an advanced BICMOS fabrication process that
yields a dropout of 110 mV at a 350-mA output load.
The TPS720-Q1 provides a monotonic VOUT rise
(overshoot limited to 3%) with VIN inrush current
limited to 100 mA + ILOAD with an output capacitor of
2.2 μF.
The TPS720-Q1 uses a precision voltage reference
and feedback loop to achieve overall accuracy of 2%
over load, line, process, and temperature extremes.
The TPS720-Q1 is available in a 6-pin WSON
package. This family of devices is fully specified over
the temperature range of TJ = –40°C to +125°C.
Camera Modules
FPD Link Power
Automotive Infotainment
USB HUB Power
Simplified Schematic
VBATT
Device Information(1)
CBIAS
PART NUMBER
TPS720-Q1
BIAS
Standalone
DC-DC
Converter
or PMU
2.3 V
IN
OUT
1.8 V
VCORE
PACKAGE
WSON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPS720-Q1
CIN
EN
GND
COUT
VEN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
16
16
17
17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (February 2016) to Revision A
Page
•
Changed Output Voltage Range bullet in Features section from "0.9 V to 3.0 V" to "0.9 V to 3.6 V" ................................... 1
•
Changed maximum value of "output voltage" parameter from 3.0 V to 3.6 V in Recommended Operating Conditions
table ........................................................................................................................................................................................ 4
•
Reformatted Thermal Information table note ......................................................................................................................... 4
•
Changed maximum value of output voltage parameter from 3.0 V to 3.6 V in Electrical Characteristics table .................... 5
•
Changed output voltage range in table note from "0.9 V to 3.0 V" to "0.9 V to 3.3 V" in Device Nomenclature section..... 18
•
Changed formatting of Related Documentation section ...................................................................................................... 18
•
Added Receiving Notification of Documentation Updates section ...................................................................................... 18
2
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
(1)
OUT
1
NC
2
EN
3
Thermal
Pad
(1)
6
IN
5
GND
4
BIAS
TI recommends connecting the WSON (DRV) package thermal pad to ground.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
OUT
1
O
Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground for stability and to provide load
transients; see Input and Output Capacitor Requirements
NC
2
—
No connection.
EN
3
I
Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT.
A logic low on this pin turns the device off.
BIAS
4
I
Bias supply pin. For better transient performance, TI recommends bypassing this input with a ceramic
capacitor to ground; see Input and Output Capacitor Requirements
GND
5
—
IN
6
I
Ground pin.
Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a ceramic
capacitor to ground; see Input and Output Capacitor Requirements.
6 Specifications
6.1 Absolute Maximum Ratings
at TJ = –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND (1)
MIN
VIN
(2)
Input voltage (steady-state)
VIN_PEAK (4)
Peak transient input
VBIAS
Bias voltage
VEN
VOUT
IOUT
Peak output current
–0.3
MAX
VBIAS or 5
UNIT
(3)
V
5.5
V
–0.3
6
V
Enable voltage
–0.3
6
V
Output voltage
–0.3
5
V
Internally limited
Output short-circuit duration
Indefinite
PDISS
Total continuous power dissipation
TJ
Operating junction temperature
–55
125
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
(3)
(4)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To ensure proper device operation, VIN must be less than or equal to VBIAS under all conditions.
Whichever is less.
For durations no longer than 1 ms each, for a total of no more than 1000 occurrences over the lifetime of the device.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
3
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
Machine model (MM)
±100
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
MAX
UNIT
VBIAS or 4.5 (1)
V
2.6 or VOUT + 1.4 (2)
5.5
V
0.9
3.6
V
Peak output current
0
350
mA
Enable voltage
0
5.5
Input voltage (steady-state)
VBIAS
Bias voltage
VOUT
Output voltage
IOUT
VEN
CIN
Input capacitance
CBIAS
Bias capacitance
COUT (3)
Output capacitance
(1)
(2)
(3)
NOM
1.1
VIN
V
1
µF
0.1
µF
2.2
µF
Whichever is less.
Whichever is greater.
Maximum ESR must be less than 250 mΩ.
6.4 Thermal Information
TPS720-Q1
THERMAL METRIC (1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
66.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
86.2
°C/W
RθJB
Junction-to-board thermal resistance
36.1
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
36.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V ) or 2.6 V (whichever is greater), VIN ≥ VOUT
+ 0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
1.1 (1)
VBIAS or
4.5 (2)
VBIAS
Bias voltage
2.6
5.5
V
Output voltage (4)
0.9
3.6
V
–2%
2%
–25
25
VOUT (3)
ΔVOUT/ΔVIN
Output
accuracy
Over VBIAS, VIN, IOUT,
TJ = –40°C to +125°C
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA
Over VBIAS, VIN, IOUT,
TJ = –40°C to +125°C
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA, VOUT < 1.2 V
VIN floating
VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
0 μA ≤ IOUT ≤ 500 μA
VIN line regulation
ΔVOUT/ΔVBIAS VBIAS line regulation
V
mV
±1%
VIN = (VOUT + 0.5 V) to 4.5 V, IOUT = 1 mA
16
μV/V
VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is
greater) to 5.5 V, IOUT = 1 mA
16
μV/V
VIN line transient
ΔVIN = 400 mV, tRISE = tFALL = 1 μs
±200
VBIAS line transient
ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs
±0.8
mV
Load regulation
0 mA ≤ IOUT ≤ 350 mA (no load to full load)
–15
μV/mA
Load transient
0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs
±15
mV
VDO_IN
VIN dropout voltage (5)
VIN = VOUT(NOM) – 0.1 V,
(VBIAS – VOUT(NOM)) = 1.4 V,
IOUT = 350 mA
110
200
mV
VDO_BIAS
VBIAS dropout voltage (6)
VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA
1.09
1.4
V
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
600
800
mA
ΔVOUT/ΔIOUT
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
PSRR
PSRR
VIN power-supply rejection ratio
VBIAS power-supply rejection ratio
420
IOUT = 100 μA
38
IOUT = 0 mA to 350 mA
54
80
0.5
2.5
VEN ≤ 0.4 V
VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
f = 10 Hz
85
f = 100 Hz
85
f = 1 kHz
85
f = 10 kHz
80
f = 100 kHz
70
f = 1 MHz
50
f = 10 Hz
80
f = 100 Hz
80
f = 1 kHz
75
f = 10 kHz
65
f = 100 kHz
55
f = 1 MHz
35
VN
Output noise voltage
Bandwidth = 10 Hz to 100 kHz, VBIAS ≥ 2.6 V,
VIN = VOUT + 0.5 V
IVIN_INRUSH
Inrush current on VIN
VBIAS = (VOUT +1.4 V) or 2.6 V (whichever is
greater), VIN = VOUT + 0.5 V
VEN(HI)
Enable pin high (enabled)
1.1
VEN(LO)
Enable pin low (disabled)
0
(1)
(2)
(3)
(4)
(5)
(6)
μV
μA
μA
dB
dB
48
μVRMS
100 + ILOAD
mA
V
0.4
V
Performance specifications are ensured to a minimum VIN = VOUT + 0.5 V.
Whichever is less.
Minimum VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater) and VIN = VOUT + 0.5 V.
VO nominal value is factory programmable through the on-chip EEPROM.
Measured for devices with VOUT(NOM) ≥ 1.2 V.
VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1 V. Measured for devices with VOUT(NOM) ≥ 1.8 V.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
5
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Electrical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V ) or 2.6 V (whichever is greater), VIN ≥ VOUT
+ 0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
IEN
UVLO
TEST CONDITIONS
MIN
TYP
Enable pin current
VEN = 5.5 V, VIN = 4.5 V, VBIAS = 5.5 V
Undervoltage lockout
VBIAS rising
UVLO hysteresis
VBIAS falling
150
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
MAX
1
2.35
2.45
–40
2.59
UNIT
µA
V
mV
°C
125
°C
MAX
UNIT
6.6 Timing Requirements
MIN
tSTR
6
Start-up time
VOUT = 95%, VOUT (NOM), IOUT = 350 mA, COUT = 2.2 μF
Submit Documentation Feedback
NOM
140
µs
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
6.7 Typical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater), VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
1.83
1.83
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.82
Output Voltage (V)
Output Voltage (V)
1.82
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.81
1.8
1.81
1.8
1.79
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Input Voltage (V)
1.79
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Input Voltage (V)
IOUT = 0 mA
IOUT = 350 mA
Figure 1. VIN Line Regulation (No Load)
Figure 2. VIN Line Regulation (350 mA)
1.83
1.83
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.82
Output Voltage (V)
Output Voltage (V)
1.82
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.81
1.8
1.81
1.8
1.79
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Bias Voltage (V)
1.79
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Input Voltage (V)
IOUT = 0 mA
IOUT = 350 mA
Figure 3. VBIAS Line Regulation (No Load)
Figure 4. VBIAS Line Regulation (350 mA)
1.83
1.83
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.82
Output Voltage (V)
Output Voltage (V)
1.82
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.81
1.8
1.81
1.8
1.79
1.79
0
1
2
3
4
5
6
7
Output Current (mA)
8
9
10
0
Figure 5. Load Regulation Under Light Loads
50
100
150
200
250
Output Current (mA)
300
Figure 6. Load Regulation
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
350
7
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater), VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
2
2
VBIAS = 3.2 V
VBIAS = 3.5 V
VBIAS = 4 V
VBIAS = 4.5 V
VBIAS = 5 V
VBIAS = 5.5 V
1.92
Output Voltage (V)
1.88
1.84
TJ = 125qC
TJ = 105qC
TJ = 85qC
TJ = 25qC
TJ = 0qC
TJ = -40qC
1.96
1.92
Output Voltage (V)
1.96
1.8
1.76
1.72
1.88
1.84
1.8
1.76
1.72
1.68
1.68
1.64
1.64
1.6
1.6
0
0.5
1
1.5
2
2.5
Output Current (mA)
3
0
3.5
0.25
0.5
Output Current (mA)
0.75
1
VBIAS = 3.2 V
Figure 7. Load Regulation With VIN Floating
Figure 8. Load Regulation With VIN Floating
1.15
160
125°C
105°C
VDO_IN (mV)
120
100
80
60
-10°C -40°C
25°C
40
VDO_BIAS = VBIAS - VOUT (V)
1.14
140
85°C
20
1.13
1.12
1.11
1.1
1.09
1.08
1.07
1.06
1.05
1.04
0
0
50
100
150
200
250
300
350
-40 -25 -10
5
20
35
50
65
95
110 125
IOUT = 350 mA
VOUT = VOUT(NOM) – 0.1 V
Figure 9. VIN Dropout Voltage vs Output Current
Figure 10. VBIAS Dropout Voltage vs Junction Temperature
50
1.83
IOUT = 0 mA
IOUT = 1 mA
IOUT = 350 mA
45
40
1.82
35
IGND (mA)
Output Voltage (V)
80
Junction Temperature (°C)
Output Current (mA)
1.81
30
25
125°C
20
105°C
85°C
25°C
-10°C
-40°C
15
1.8
10
5
1.79
-40
0
-25
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
2.5
3
3.5
4
4.5
5
5.5
VBIAS (V)
IOUT = 1 mA
Figure 11. Output Voltage vs Junction Temperature
8
Figure 12. Ground Pin Current vs VBIAS Voltage
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater), VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
70
60
60
125°C 105°C
85°C
50
25°C
40
IGND (mA)
IGND (mA)
50
40
30
-10°C
20
30
20
-40°C
10
10
0
0
0
50
100
150
200
250
350
300
-40 -25 -10
Output Current (mA)
5
20
35
50
65
80
95
110 125
Junction Temperature (°C)
IOUT = 350 mA
Figure 13. Ground Pin Current vs Output Current
Figure 14. Ground Pin Current vs Junction Temperature
675
3
2.5
650
-10°C
25°C
-40°C
-10°C
25°C
-40°C
85°C
1.5
125°C
ICL (mA)
ISHDN (mA)
2
625
600
1
85°C
105°C
0.5
125°C
550
0
2.5
3
3.5
4.5
4
5
5.5
2.5
3
3.5
4.5
4
5
5.5
VBIAS (V)
VBIAS (V)
Figure 15. Shutdown Current vs VBIAS Voltage
Figure 16. Current Limit vs VBIAS Voltage
120
675
-10°C
25°C
IOUT = 0 mA
-40°C
100
VIN PSRR (dB)
650
ICL (mA)
105°C
575
625
600
85°C
105°C
125°C
575
80
IOUT = 50 mA
60
IOUT = 350 mA
40
20
0
550
2.5
3
3.5
4.5
4
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Input Voltage (V)
VIN – VOUT = 0.5 V, VBIAS – VOUT = 1.4 V
Figure 17. Current Limit vs Input Voltage
Figure 18. VIN Power-Supply Rejection Ratio vs Frequency
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
9
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater), VIN = VOUT +
0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
100
100
(VIN - VOUT) = 350 mV
80
80
VIN PSRR (dB)
VIN PSRR (dB)
IOUT = 1 mA
60
(VIN - VOUT) = 300 mV
40
60
40
(VIN - VOUT) = 250 mV
IOUT = 350 mA
20
20
0
0
10
100
1k
10k
100k
1M
10M
10
100
Frequency (Hz)
10k
100k
1M
10M
Frequency (Hz)
IOUT = 350 mA
VIN – VOUT = 0.5 V
Figure 19. VIN Power-Supply Rejection Ratio vs Frequency
Output Spectral Noise Density (mV/ÖHz)
1k
VBIAS – VOUT = 1.4 V
Figure 20. VBIAS Power-Supply Rejection Ratio vs Frequency
10
VOUT
1 mV/div
1
0.1
VIN
200 mV/div
0.01
100
1k
100k
10k
100 ms/div
Frequency (Hz)
VIN = 2.1 to 2.5 V
VIN slew rate = 1 V/μs
VOUT = 1.8 V
IOUT = 350 mA
VBIAS = 3.2 V
Figure 22. VIN Line Transient Response
Figure 21. Output Spectral Noise Density vs Frequency
VOUT
VOUT
10 mV/div
1 mV/div
300 mA
VBIAS
IOUT
0 mA
100 mA/div
200 mV/div
100 ms/div
100 ms/div
VIN = 2.3 V
VOUT = 1.8 V
VBIAS slew rate = 600 m/μs
VBIAS = 3.2 V to 3.8 V
IOUT = 350 mA
VIN = 2.3 V
Figure 23. VBIAS Line Transient Response
10
Submit Documentation Feedback
VOUT = 1.8 V
tRISE = 1 μs
VBIAS = 3.2 V
Figure 24. Load Transient Response
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
7 Detailed Description
7.1 Overview
The TPS720-Q1 family of LDO regulators uses innovative circuitry to achieve ultra-wide bandwidth and high loop
gain, resulting in extremely high PSRR (up to 1 MHz) at very low headroom (VIN – VOUT). The implementation of
the BIAS pin on the TPS720-Q1 vastly improves efficiency of low VOUT applications by allowing the use of a preregulated, low-voltage input supply. The TPS720-Q1 supports a novel feature where the output of the LDO
regulates under light loads (< 500 μA) when the IN pin is left floating. The light-load drive current is sourced from
VBIAS under this condition. This feature is particularly useful in power-saving applications where the dc-dc
converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load.
These features, combined with low noise, low ground pin current, and ultra-small packaging, make this device
ideal for portable applications. This family of regulators offers sub-band-gap output voltages, current limit, and
thermal protection, and is fully specified from –40°C to +125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
BIAS
UVLO
Band Gap
EN
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS720-Q1 internal current limits help protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output
voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The NMOS pass transistor dissipates (VIN – VOUT) × IOUT
until thermal shutdown is triggered and the device is turned off. When the device cools down, the internal thermal
shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit
and thermal shutdown; see Thermal Considerations for more details.
The NMOS pass element in the TPS720-Q1 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, TI recommends external limiting to 5% of rated output current.
7.3.2 Inrush Current Limit
The TPS720-Q1 family of LDO regulators implements a novel inrush current limit circuit architecture: the current
drawn through the IN pin is limited to a finite value. This IINRUSHLIMIT charges the output to the final voltage. All
current drawn through VIN charges the output capacitance when the load is disconnected. Equation 1 shows the
inrush current limit performed by the circuit.
I INRUSHLIMIT ( A )
COUT( PF ) x 0.454545(V / Ps) I LOAD (A)
(1)
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
11
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Feature Description (continued)
Assuming a COUT of 2.2 μF with the load disconnected (that is, ILOAD = 0), the IINRUSHLIMIT is calculated to be
100 mA. The inrush current charges the LDO output capacitor. If the output of the LDO regulates to 1.3 V, then
the LDO charges the output capacitor to the final output value in approximately 28.6 μs.
Another consideration is when a load is connected to the output of an LDO. The TPS720-Q1 inrush current limit
circuit employs a technique that supplies not only the IINRUSHLIMIT, but the additional current required by the load.
If ILOAD = 350 mA, then IINRUSHLIMIT calculates to be approximately 450 mA (from Equation 1).
7.3.3 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to the IN pin.
7.3.4 Undervoltage Lockout (UVLO)
The TPS720-Q1 uses an undervoltage lockout circuit on the BIAS pin to keep the output shut off until the internal
circuitry is operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot transients
on the input if these transients are less than 50 μs in duration.
7.4 Device Functional Modes
Driving the EN pin over 1.1 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter
shutdown mode. In shutdown, the current consumption of the device is typically reduced to 500 nA.
12
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Requirements
Although a capacitor is not required for stability on the IN pin, good analog design practice is to connect a 0.1-μF
to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if
the device is located far from the power source. If source impedance is not sufficiently low, a 0.1-μF input
capacitor may be necessary to ensure stability.
The BIAS pin does not require an input capacitor because BIAS does not source high currents. However, if
source impedance is not sufficiently low, TI recommends a small 0.1-µF bypass capacitor.
The TPS720-Q1 is designed to be stable with standard ceramic capacitors with values of 2.2 μF or larger at the
output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR must be less than 250 mΩ.
8.1.2 Output Regulation With the IN Pin Floating
The TPS720-Q1 supports a novel feature where the output of the LDO regulates under light loads when the IN
pin is left floating. Under normal conditions when the IN pin is connected to a power source, the BIAS pin draws
only tens of milliamperes. However, when the IN pin is floating, an innovative circuit allows a maximum current of
500 μA to be drawn by the load through the BIAS pin and maintains the output in regulation. This feature is
particularly useful in power-saving applications where a dc-dc converter connected to the IN pin is disabled, but
the LDO is required to regulate the output voltage to a light load.
Figure 25 shows an application example where a microcontroller is not turned off (to maintain the state of the
internal memory), but where the regulated supply (shown as the TPS62xxx) is turned off to reduce power. In this
case, the TPS720-Q1 BIAS pin provides sufficient load current to maintain a regulated voltage to the
microcontroller.
10 mH
2.6 V to 5.5 V
VIN
TPS62xxx
EN
IN
SW
GND
Control to turn on or off the dc-dc.
FB
BIAS
OUT
TPS720-Q1
10 mF
EN
2.2 mF
GND
Microcontroller
The output of the dc-dc is floating when
the TPS62xxx EN pin is low.
Figure 25. Floating IN Pin Regulation Example
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
13
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Application Information (continued)
8.1.3 Dropout Voltage
The TPS720-Q1 uses a NMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the NMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the NMOS pass element. VDO approximately scales with output current because the
NMOS device behaves like a resistor in dropout.
PSRR and transient response are degraded when (VIN – VOUT) approaches dropout. This effect is shown in
Figure 19.
8.1.4 Transient Response
Increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration
of the transient response.
8.1.5 Minimum Load
The TPS720-Q1 is stable with no output load. Although some LDOs suffer from low loop gain at very light output
loads, the TPS720-Q1 employs an innovative, low-current mode circuit under very light or no-load conditions
which improves output voltage regulation performance.
8.2 Typical Application
VBATT
CBIAS
BIAS
1.8 V
Standalone
dc/dc
Converter
or PMU
IN
OUT
1.3 V
VCORE
TPS720xx
CIN
EN
COUT
GND
VEN
Figure 26. Typical Application Schematic
8.2.1 Design Requirements
Table 1 lists the parameters for this design example.
Table 1. Design Parameters
14
DESIGN PARAMETER
EXAMPLE VALUE
VIN
2.3 V
VBIAS
3.2 V
VOUT
1.8 V
IOUT
10-mA typical, 350-mA peak
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
8.2.2 Detailed Design Procedures
TI recommends selecting the minimum component size; a small size solution for this design example is desired.
Set CIN = 1 µF, C BIAS = 100 nF, and COUT = 2.2 µF.
8.2.3 Application Curves
1.83
1.83
Output Voltage (V)
1.82
1.81
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.82
Output Voltage (V)
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
1.81
1.8
1.8
1.79
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Input Voltage (V)
1.79
0
50
100
150
200
250
Output Current (mA)
300
350
IOUT = 350 mA
Figure 27. VIN Line Regulation
Figure 28. Load Regulation
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
15
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
9 Power Supply Recommendations
The input supply and bias supply for the LDO must be within the recommended operating conditions and must
provide adequate headroom for the device to have a regulated output. The minimum capacitor requirements
must be met, and if the input supply is noisy, additional input capacitors with low ESR can improve transient
performance.
10 Layout
10.1 Layout Guidelines
TI recommends designing the board with separate ground planes for VIN and VOUT, with the ground plane
connected only at the GND pin of the device to improve ac performance (such as PSRR, output noise, and
transient response.) In addition, the ground connection for the output capacitor must be connected directly to the
GND pin of the device. High equivalent series resistance (ESR) capacitors can degrade PSRR. The BIAS pin
draws very little current and can be routed as a signal. Take care to shield the BIAS pin from high frequency
coupling.
10.2 Layout Example
Ground Plane
To Bias Supply
4
BIAS
5
GND
EN
3
NC
2
To Enable
Signal
Thermal Pad
CBIAS
COUT
CIN
6
IN
OUT
1
To Load
To Input Supply
Ground Plane
Figure 29. Recommended Layout
16
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from
damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to a maximum of +125°C. To estimate the margin of
safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C
above the maximum expected ambient condition of the particular application. This configuration produces a
worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS720-Q1 is designed to protect against overload conditions. This
circuitry is not intended to replace proper heat sinking. Continuously running the TPS720-Q1 into thermal
shutdown degrades device reliability.
10.4 Power Dissipation
The printed-circuit-board (PCB) area around the device that is free of other components moves the heat from the
device to ambient air. Performance data for JEDEC boards are given in the Thermal Information table. Using
heavier copper increases the effectiveness in removing heat from the device. The addition of plated throughholes to heat-dissipating layers also improves the heat sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2:
PD (VIN
VOUT ) u I OUT
(2)
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
17
TPS720-Q1
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS720Q1. The TPS720xxDRVEVM evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 2. Device Nomenclature (1) (2)
(1)
(2)
PRODUCT
VOUT
TPS720xx(x)QyyyzQ1
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
yyy is the package designator.
z is the package quantity. R is for 3000 pieces, T is for 250 pieces.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.9 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• High-Efficiency Step-Down Low Power DC-DC Converter (SGLS243).
• TPS720xxDRVEVM Evaluation Module (SBVU024).
• Using New Thermal Metrics (SBVA025).
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
18
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
TPS720-Q1
www.ti.com
SBVS278A – FEBRUARY 2016 – REVISED OCTOBER 2016
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS720-Q1
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS72009QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11P
TPS720105QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15G
TPS72010QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11Q
TPS720115QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15H
TPS72011QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11I
TPS72012QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11R
TPS72015QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11J
TPS72018QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11K
TPS72025QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11W
TPS72027QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15I
TPS720285QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11M
TPS72028QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11L
TPS72029QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11N
TPS72030QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
11O
TPS72033QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
