TPS74401-EP
TP
S7
44x
x
TP
S7
44
xx
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SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
3.0-A ULTRA-LDO WITH PROGRAMMABLE SOFT-START
Check for Samples: TPS74401-EP
FEATURES
APPLICATIONS
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
Soft-Start (SS) Pin Provides a Linear Startup
with Ramp Time Set by External Capacitor
1% Accuracy Over Line, Load, and
Temperature
Supports Input Voltages as Low as 0.9 V with
External Bias Supply
Adjustable Output (0.8 V to 3.6 V)
Ultra-Low Dropout: 115 mV at 3.0 A (typ)
Stable with Any or No Output Capacitor
Excellent Transient Response
Available in 5 mm × 5 mm × 1 mm QFN
Package
Active High Enable
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
ADJUSTABLE VOLTAGE VERSION
VIN
IN
CIN
1mF
R3
BIAS TPS74401
VBIAS
VOUT
OUT
R1
SS
CBIAS
1mF
VPG
PG
EN
GND
FB
CSS
COUT
R2
Optional
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Ranges (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
FIXED VOLTAGE VERSION
VIN
IN
CIN
1mF
R3
BIAS TPS744xx
VBIAS
GND
VOUT
OUT
SS
CBIAS
1mF
VPG
PG
EN
SNS
COUT
CSS
Optional
Figure 1. Typical Application Circuit
Custom temperature ranges available
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS74401-EP
SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The TPS74401 low-dropout (LDO) linear regulator provides an easy-to-use robust power management solution
for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by
reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many
different types of processors and ASICs. The enable input and power-good output allow easy sequencing with
external regulators. This complete flexibility permits the user to configure a solution that will meet the sequencing
requirements of FPGAs, DSPs, and other applications with specific start-up requirements.
A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each
LDO is stable with low-cost ceramic output capacitors and the device is fully specified from –55°C to 125°C.
CSS = 0mF
VOUT
CSS = 0.001mF
CSS = 0.0047mF
500mV/div
1.1V
1V/div
VEN
0V
Time (1ms/div)
Figure 2. Turn-On Response
Table 1. ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
(2)
2
PACKAGE (2)
QFN (RGW)
Reel of 3000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS74401MRGWREP
TPS74401EP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
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SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –55°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
UNIT
VIN, VBIAS
Input voltage range
–0.3 to +6
V
VEN
Enable voltage range
–0.3 to +6
V
VPG
Power-good voltage range
–0.3 to +6
V
IPG
PG sink current
0 to +1.5
mA
VSS
SS pin voltage range
–0.3 to +6
V
VFB
Feedback pin voltage range
–0.3 to +6
V
VOUT
Output voltage range
–0.3 to VIN + 0.3
V
IOUT
Maximum output current
Internally limited
Output short circuit duration
Indefinite
TJ
Operating junction temperature range
–55 to +125
°C
TSTG
Storage junction temperature range
–65 to +150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TPS74401-EP
RGW (20 PINS)
qJA
Junction-to-ambient thermal resistance
36.3
qJCtop
Junction-to-case (top) thermal resistance
34.3
qJB
Junction-to-board thermal resistance
10.8
yJT
Junction-to-top characterization parameter
0.3
yJB
Junction-to-board characterization parameter
11.9
qJCbot
Junction-to-case (bottom) thermal resistance
2.4
(1)
(2)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
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ELECTRICAL CHARACTERISTICS
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CIN = CBIAS = 0.1 mF, COUT = 10 mF, IOUT = 50 mA, VBIAS = 5.0 V,
and TJ = –55°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range
VBIAS
Bias pin voltage range
VREF
Internal reference (Adj.)
Output voltage range
VOUT
Accuracy
VOUT/VIN
VOUT/IOUT
MIN
UNIT
5.5
V
2.375
5.25
V
0.792
0.808
V
VREF
3.6
V
±0.2
+1
%
0.0005
0.05
VIN = 5 V, IOUT = 1.5 A, VBIAS = 5 V
2.97 V ≤ VBIAS ≤ 5.25 V,
50 mA ≤ IOUT ≤ 3.0 A
(1)
Line regulation
VOUT
Load regulation
VIN dropout voltage
VDO
MAX
VOUT + VDO
(2)
(NOM)
+ 0.3 ≤ VIN ≤ 5.5 V
0.013
%/mA
50 mA ≤ IOUT ≤ 3.0 A
0.03
%/A
IOUT = 3.0 A, VBIAS – VOUT (NOM) ≥ 1.62 V
120
IOUT = 3.0 A, VIN = VBIAS
ICL
Current limit
VOUT = 80% × VOUT (NOM)
IBIAS
Bias pin current
IOUT = 0 mA to 3.0 A
ISHDN
Shutdown supply current
(VIN)
VEN ≤ 0.4 V
IFB
Feedback pin current (3)
IOUT = 50 mA to 3.0 A
PSRR (4)
Power-supply rejection
(VBIAS to VOUT)
%/V
0mA ≤ IOUT ≤ 50 mA
VBIAS dropout voltage (2)
Power-supply rejection
(VIN to VOUT)
–1
TYP
195
mV
1.62
V
6.0
A
2
4
mA
0.4
1
mA
95
250
nA
3.7
–250
1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
73
800 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
42
1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
62
800 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
50
dB
dB
Noise
Output noise voltage
100 Hz to 100 kHz, IOUT = 1.5 A,
CSS = 0.001 mF
16 × VOUT
mVRMS
VTRAN
%VOUT droop during load
transient
IOUT = 100 mA to 3.0 A at 1 A/ms,
COUT = 0 mF
4
%VOUT
tSTR
Minimum startup time
IOUT = 1.5 A, CSS = open
ISS
Soft-start charging current
VSS = 0.4 V
VEN, HI
Enable input high level
VEN, LO
Enable input low level
VEN, HYS
Enable pin hysteresis
50
mV
VEN, DG
Enable pin deglitch time
20
ms
IEN
Enable pin current
VEN = 5 V
VIT
PG trip threshold
VOUT decreasing
VHYS
PG trip hysteresis
VPG,
IPG,
LO
LKG
IPG = 1 mA (sinking), VOUT < VIT
PG leakage current
VPG = 5.25 V, VOUT > VIT
Operating junction
temperature
TSD
Thermal shutdown
temperature
(1)
(2)
(3)
(4)
4
ms
1
mA
1.1
5.5
V
0
0.4
86
0.73
V
0.1
1
mA
90
93.5
%VOUT
3
PG output low voltage
TJ
100
0.5
0.03
–55
Shutdown, temperature increasing
+155
Reset, temperature decreasing
+140
%VOUT
0.3
V
1
mA
+125
°C
°C
Adjustable devices tested at 0.8 V; external resistor tolerance is not taken into account.
Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
IFB current flow is out of the device.
See Figure 10 to Figure 13 for PSRR at different conditions.
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SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
BLOCK DIAGRAM
IN
Current
Limit
BIAS
UVLO
OUT
VOUT
Thermal
Limit
0.73mA
R1
SS
CSS
Soft-Start
Discharge
VOUT = 0.8 x (1 +
0.8V
Reference
R1
)
R2
FB
PG
Hysteresis
and De-Glitch
EN
R2
0.9 ´ VREF
GND
Table 2. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1/R2)
Table 3. Standard Capacitor Values for Programming the Soft-Start Time (1)
(1)
CSS
SOFT-START TIME
Open
0.1 ms
470 pF
0.5 ms
1000 pF
1 ms
4700 pF
5 ms
0.01 mF
10 ms
0.015 mF
16 ms
–7
tSS(s) = 0.8 × CSS(F)/7.3 × 10
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IN
NC
NC
NC
OUT
5
4
3
2
1
RGW PACKAGE
(TOP VIEW)
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB/SNS
11
12
13
14
15
EN
GND
NC
NC
SS
TPS74401
GND
PIN DESCRIPTIONS
NAME
NO.
DESCRIPTION
IN
5–8
Unregulated input to the device.
EN
11
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator
into shutdown mode. This pin must not be left floating.
SS
15
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin
is left floating, the regulator output soft-start ramp time is typically 100ms.
BIAS
10
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
9
Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT.
When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state.
When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up
resistor from 10kΩ to 1MΩ should be connected from this pin to a supply up to 5.5V. The
supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if
output monitoring is not necessary.
FB
16
This pin is the feedback connection to the center tap of an external resistor divider network
that sets the output voltage. This pin must not be left floating.
OUT
1, 18–20
NC
2–4, 13, 14, 17
GND
12
PAD/TAB
6
Regulated output voltage. No capacitor is required on this pin for stability.
No connection. This pin can be left floating or connected to GND to allow better thermal
contact to the top-side plane.
Ground
Should be soldered to the ground plane for increased thermal performance.
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SBVS122B – MARCH 2010 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS
At TJ = +25°C, VOUT = 1.5 V, VIN = VOUT(TYP) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 mF, CBIAS = 1 mF, CSS = 0.01 mF, and COUT = 10
mF, unless otherwise noted.
LOAD REGULATION
LOAD REGULATION
1.0
0.050
Referred to IOUT = 50mA
0.9
Referred to IOUT = 50mA
0.025
0.7
0.6
-40°C
0.5
0.4
+25°C
0.3
0
Change in VOUT (%)
Change in VOUT (%)
0.8
0.2
-0.025
+25°C
-0.050
-40°C
-0.075
+125°C
-0.100
0.1
+125°C
0
-0.125
-0.150
-0.1
0
10
20
30
40
50
50
500
1000
IOUT (mA)
1500
2000
2500
3000
IOUT (mA)
Figure 3.
Figure 4.
LINE REGULATION
VIN DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
0.05
200
0.04
0.02
Dropout Voltage (mV)
Change in VOUT (%)
0.03
TJ = -40°C
0.01
0
-0.01
TJ = +25°C
TJ = +125°C
-0.02
150
+125°C
100
50
-0.03
-40°C
-0.04
0
-0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
500
1000
VIN - VOUT (V)
1500
2000
2500
Figure 6.
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
200
IOUT = 3.0A
IOUT = 1.5A
180
250
160
Dropout Voltage (mV)
+125°C
200
+25°C
150
3000
IOUT (mA)
Figure 5.
300
Dropout Voltage (mV)
+25°C
100
140
120
+125°C
100
+25°C
80
60
40
50
-40°C
-40°C
20
0
0
0.9
1.4
1.9
2.4
2.9
3.4
3.9
0.9
VBIAS - VOUT (V)
1.4
1.9
2.4
2.9
3.4
3.9
VBIAS - VOUT (V)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5 V, VIN = VOUT(TYP) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 mF, CBIAS = 1 mF, CSS = 0.01 mF, and
COUT = 10 mF, unless otherwise noted.
VBIAS DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
1400
+125°C
Power-Supply Rejection Ratio (dB)
VIN = VBIAS
1300
Dropout Voltage (mV)
VBIAS PSRR vs FREQUENCY
80
+25°C
1200
1100
1000
-40°C
900
800
700
600
IOUT = 3.0A
70
60
50
40
30
20
10
0
500
0
500
1000
1500
2000
2500
3000
10
100
1k
IOUT (mA)
10k
Figure 9.
COUT = 100mF C
OUT = 10mF
70
60
50
40
30
20
COUT = 0mF
10
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
VIN = 1.8, VOUT = 1.5V, IOUT = 100mA
80
VIN = 1.8, VOUT = 1.5V, IOUT = 1.5A
90
80
70
COUT = 100mF
60
COUT = 10mF
50
40
30
20
10
COUT = 0mF
0
0
10
100
1k
10k
100k
1M
10
10M
100
Figure 11.
Figure 12.
COUT = 100mF
COUT = 10mF
40
30
20
10
COUT = 0mF
0
100
1k
10k
100k
1kHz
70
700kHz
60
50
40
300kHz
30
1M
10M
100kHz
20
COUT = 22mF
IOUT = 1.5A
10
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Frequency (Hz)
VIN - VOUT (V)
Figure 13.
8
10M
80
0
10
1M
90
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
70
50
100k
VIN PSRR vs VIN – VOUT
80
60
10k
Frequency (Hz)
VIN = 1.8, VOUT = 1.5V, IOUT = 3A
90
1k
Frequency (Hz)
VIN PSRR vs FREQUENCY
100
10M
VIN PSRR vs FREQUENCY
100
90
1M
Figure 10.
VIN PSRR vs FREQUENCY
100
100k
Frequency (Hz)
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5 V, VIN = VOUT(TYP) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 mF, CBIAS = 1 mF, CSS = 0.01 mF, and
COUT = 10 mF, unless otherwise noted.
NOISE SPECTRAL DENSITY
Output Spectral Noise Density (mV/ÖHz)
Output Spectral Noise Density (mV/ÖHz)
NOISE SPECTRAL DENSITY
1
IOUT = 3A
VOUT = 1.1V
CSS = 1nF
CSS = 0nF
0.1
CSS = 10nF
0.01
100
1k
10k
1
VOUT = 3.3V
VOUT = 2.5V
0.1
VOUT = 1.5V
VOUT = 1.1V
VOUT = 0.8V
0.01
100
100k
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 15.
Figure 16.
IBIAS vs IOUT AND TEMPERATURE
100k
IBIAS vs VBIAS AND VOUT
2.85
3.0
+125°C
2.8
2.65
TJ = +125°C
2.6
2.45
Bias Current (mA)
Bias Current (mA)
VBIAS: VOUT + 1.62V
IOUT: 3A
CIN: 1mF (Ceramic)
COUT: 1mF (Ceramic)
R1, R2: (see Table 1)
2.25
2.05
+25°C
1.85
1.65
-40°C
2.4
2.2
2.0
TJ = +25°C
1.8
1.6
TJ = -40°C
1.4
1.45
1.2
1.25
1.0
0
500
1000
1500
2000
2500
3000
2.0
2.5
3.0
3.5
IOUT (mA)
VBIAS (V)
Figure 17.
Figure 18.
4.0
4.5
5.0
IBIAS SHUTDOWN vs TEMPERATURE
0.45
0.40
VBIAS = 2.375V
Bias Current (mA)
0.35
0.30
VBIAS = 5.5V
0.25
0.20
0.15
0.10
0.05
0
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5 V, VIN = VOUT(TYP) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 mF, CBIAS = 1 mF, CSS = 0.01 mF, and
COUT = 10 mF, unless otherwise noted.
SOFT-START CHARGING CURRENT (ISS)
vs TEMPERATURE
LOW-LEVEL PG VOLTAGE vs PG CURRENT
1.0
VOL Low-Level PG Voltage (V)
765
750
ISS (nA)
735
720
705
690
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
675
-40
-20
0
20
40
60
80
100
120
0
Junction Temperature (°C)
4
6
8
10
12
PG Current (mA)
Figure 20.
10
2
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5 V, VIN = VOUT(TYP) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 mF, CBIAS = 1 mF, CSS = 0.01 mF, and
COUT = 10 mF, unless otherwise noted.
LOAD TRANSIENT RESPONSE
50mV/div
50mV/div
50mV/div
COUT = 2 x 470mF (OSCON)
VBIAS LINE TRANSIENT (3A)
COUT = 2 x 470mF (OSCON)
10mV/div
COUT = 100mF Cer.
COUT = 100mF (Cer.)
10mV/div
COUT = 10mF Cer.
COUT = 10mF (Cer.)
10mV/div
COUT = 0mF
10mV/div
50mV/div
COUT = 0mF
4.3V
3.0A
1A/ms
2A/div
1V/ms
500mV/div
100mA
3.3V
Time (50ms/div)
Time (50ms/div)
Figure 22.
Figure 23.
VIN LINE TRANSIENT (3A)
TURN-ON RESPONSE
COUT = 2 x 470mF
10mV/div
10mV/div
10mV/div
VOUT = 1.2V
(OSCON)
10mV/div
CSS = 0mF
CSS = 0.0047mF
500mV/div
COUT = 10mF (Cer.)
COUT = 0mF
1.1V
2.5V
1V/ms
500mV/div
VOUT
CSS = 0.001mF
COUT = 100mF (Cer.)
1V/div
VEN
0V
1.5V
Time (50ms/div)
Time (1ms/div)
Figure 24.
Figure 25.
POWER-UP/POWER-DOWN
OUTPUT SHORT-CIRCUIT RECOVERY
VOUT = 0.8V
1V/div
VIN = VBIAS = VEN
VPG (500mV/div)
IOUT
1A/div
VOUT
50mV/div
Output Shorted
VOUT
Output Open
Time (20ms/div)
Time (20ms/div)
Figure 26.
Figure 27.
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APPLICATION INFORMATION
The TPS74401 belongs to a family of new
generation ultra-low dropout regulators that feature
soft-start and tracking capabilities. These regulators
use a low current bias input to power all internal
control circuitry, allowing the NMOS pass transistor to
regulate very low input and output voltages.
The use of an NMOS-pass FET offers several critical
advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect
on loop stability. This architecture allows the
TPS74401 to be stable with any or even no output
capacitor. Transient response is also superior to
PMOS topologies, particularly for low VIN
applications.
The
TPS74401
features
a
programmable,
voltage-controlled soft-start circuit that provides a
smooth, monotonic start-up and limits startup inrush
currents that may be caused by large capacitive
loads. A power-good (PG) output is available to allow
supply monitoring and sequencing of other supplies.
An enable (EN) pin with hysteresis and deglitch
allows slow-ramping signals to be used for
sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and
efficient linear regulation between the multiple supply
voltages often present in processor intensive
systems.
Figure 28 illustrates a typical application circuit for the
TPS74401 adjustable output device.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 28. Refer to
Table 2 for sample resistor values of common output
voltages. In order to achieve the maximum accuracy
specifications, R2 should be ≤ 4.99 kΩ.
VIN
IN
CIN
1mF
R3
BIAS TPS74401
VBIAS
VOUT
OUT
R1
SS
CBIAS
1mF
VPG
PG
EN
FB
GND
CSS
COUT
Optional
R2
VOUT = 0.8 ´
(
1+
R1
R2
)
INPUT, OUTPUT, AND BIAS CAPACITOR
REQUIREMENTS
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
is designed to be stable for all available types and
values of output capacitance. The device is also
stable with multiple capacitors in parallel, of any type
or value.
The capacitance required on the IN and BIAS pins
strongly depends on the input supply source
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for VIN
and VBIAS is 1 mF. If VIN and VBIAS are connected to
the same supply, the recommended minimum
capacitor for VBIAS is 4.7 mF. Good quality, low ESR
capacitors should be used on the input; ceramic X5R
and X7R capacitors are preferred. These capacitors
should be placed as close the pins as possible for
optimum performance.
TRANSIENT RESPONSE
The TPS74401 was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300 mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance. With a solid input supply, adding
additional output capacitance reduces undershoot
and overshoot during a transient at the expense of a
slightly longer VOUT recovery time. Refer to Figure 22
in the Typical Characteristics section. Since the
TPS74401 is stable without an output capacitor,
many applications may allow for little or no
capacitance at the LDO output. For these
applications, local bypass capacitance for the device
under power may be sufficient to meet the transient
requirements of the application. This design reduces
the total solution cost by avoiding the need to use
expensive high-value capacitors at the LDO output.
Figure 28. Typical Application Circuit for the
TPS74401 (Adjustable)
12
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DROPOUT VOLTAGE
VIN
The TPS74401 offers industry-leading dropout
performance, making it well-suited for high-current
low VIN/low VOUT applications. The extremely low
dropout of the TPS74401 allows the device to be
used in place of a DC/DC converter and still achieve
good efficiencies. This efficiency allows users to
rethink the power architecture for their applications to
achieve the smallest, simplest, and lowest cost
solution.
There are two different specifications for dropout
voltage with the TPS74401. The first specification
(see Figure 29) is referred to as VIN Dropout and is
for users that wish to apply an external bias voltage
to achieve low dropout. This specification assumes
that VBIAS is at least 1.62 V above VOUT, which is the
case for VBIAS when powered by a 3.3-V rail with 5%
tolerance and with VOUT = 1.5V. If VBIAS is higher than
3.3 V × 0.95 or VOUT is less than 1.5 V, VIN dropout is
less than specified.
BIAS
IN
Reference
VBIAS = 5V ± 5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
FB
Simplified Block Diagram
Figure 29. Typical Application of the TPS74401
Using an Auxiliary Bias Rail
The second specification (see Figure 30) is referred
to as VBIAS Dropout and is for users that wish to tie IN
and BIAS together. This option allows the device to
be used in applications where an auxiliary bias
voltage is not available or low dropout is not required.
Dropout is limited by BIAS in these applications
because VBIAS provides the gate drive to the pass
FET and therefore must be 1.62 V above VOUT.
Because of this usage, IN and BIAS tied together
easily consume huge power. Pay attention not to
exceed the power rating of the IC package.
BIAS
Reference
IN
VBIAS = 3.3V ± 5%
VIN = 3.3V ± 5%
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
FB
Simplified Block Diagram
Figure 30. Typical Application of the TPS74401
Without an Auxiliary Bias
PROGRAMMABLE SOFT-START
The TPS74401 features a programmable, monotonic,
voltage-controlled soft-start that is set with an
external capacitor (CSS). This feature is important for
many applications because it eliminates power-up
initialization problems when powering FPGAs, DSPs,
or other processors. The controlled voltage ramp of
the output also reduces peak inrush current during
start-up, minimizing start-up transients to the input
power bus.
To achieve a linear and monotonic soft-start, the
TPS74401 error amplifier tracks the voltage ramp of
the external soft-start capacitor until the voltage
exceeds the internal reference. The soft-start ramp
time depends on the soft-start charging current (ISS),
the soft-start capacitance (CSS), and the internal
reference voltage (VREF), and can be calculated using
Equation 1:
ǒVREF CSSǓ
t SS +
I SS
(1)
If large output capacitors are used, the device current
limit (ICL) and the output capacitor may set the
start-up time. In this case, the start-up time is given
by Equation 2:
t SSCL +
ǒVOUT(NOM)
COUTǓ
I CL(MIN)
(2)
VOUT(NOM) is the nominal set output voltage as set by
the user, COUT is the output capacitance, and ICL(MIN)
is the minimum current limit for the device. In
applications where monotonic startup is required, the
soft-start time given by Equation 1 should be set to
be greater than Equation 2.
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The maximum recommended soft-start capacitor is
0.015 mF. Larger soft-start capacitors can be used
and will not damage the device; however, the
soft-start capacitor discharge circuit may not be able
to fully discharge the soft-start capacitor when
re-enabled. Soft-start capacitors larger than 0.015 mF
could be a problem in applications where the user
needs to rapidly pulse the enable pin and still
requires the device to soft-start from ground. CSS
must be low-leakage; X7R, X5R, or C0G dielectric
materials are preferred. Refer to Table 3 for
suggested soft-start capacitor values.
SEQUENCING REQUIREMENTS
The device can have VIN, VBIAS, and VEN sequenced
in any order without causing damage to the device.
However, for the soft-start function to work as
intended, certain sequencing rules must be applied.
Enabling the device after VIN and VBIAS are present is
preferred, and can be accomplished using a digital
output from a processor or supply supervisor. An
analog signal from an external RC circuit, as shown
in Figure 31, can also be used as long as the delay
time is long enough for VIN and VBIAS to be present.
VIN
IN
VOUT
OUT
CIN
1mF
R1
BIAS TPS74401
FB
R2
R
VBIAS
CBIAS
1mF
EN
GND
C
SS
CSS
Figure 31. Soft-Start Delay Using an RC Circuit
on Enable
If a signal is not available to enable the device after
IN and BIAS, simply connecting EN to IN is
acceptable for most applications as long as VIN is
greater than 1.1 V and the ramp rate of VIN and VBIAS
is faster the set soft-start ramp rate. If the ramp rate
of the input sources is slower than the set soft-start
time, the output will track the slower supply minus the
dropout voltage until it reaches the set output voltage.
If EN is connected to BIAS, the device will soft-start
as programmed provided that VIN is present before
VBIAS. If VBIAS and VEN are present before VIN is
applied and the set soft-start time has expired then
VOUT will track VIN.
NOTE: When VBIAS and VEN are present and VIN is
not supplied, this device outputs approximately 50 mA
of current from OUT. Although this condition will not
cause any damage to the device, the output current
may charge up the OUT node if total resistance
between OUT and GND (including external feedback
resistors) is greater than 10 kΩ.
14
OUTPUT NOISE
The TPS74401 provides low output noise when a
soft-start capacitor is used. When the device reaches
the end of the soft-start cycle, the soft-start capacitor
serves as a filter for the internal reference. By using a
0.001-mF soft-start capacitor, the output noise is
reduced by half and is typically 19 mVRMS for a 1.2-V
output (100 Hz to 100 kHz). Because most of the
output noise is generated by the internal reference,
the noise is a function of the set output voltage. The
RMS noise with a 0.001-mF soft-start capacitor is
given in Equation 3.
ǒmVV Ǔ
V NǒmVRMSǓ + 16
RMS
V OUT(V)
(3)
The low output noise of the TPS74401 makes it a
good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
ENABLE/SHUTDOWN
The enable (EN) pin is active high and is compatible
with standard digital signaling levels. VEN below 0.4 V
turns the regulator off, while VEN above 1.1 V turns
the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with
relatively slow-ramping analog signals. This
configuration allows the TPS74401 to be enabled by
connecting the output of another supply to the EN
pin. The enable circuitry typically has 50 mV of
hysteresis and a deglitch circuit to help avoid on-off
cycling because of small glitches in the VEN signal.
The enable threshold is typically 0.8 V and varies with
temperature and process variations. Temperature
variation is approximately –1 mV/°C; therefore,
process variation accounts for most of the variation in
the enable threshold. If precise turn-on timing is
required, a fast rise-time signal should be used to
enable the TPS74401.
If not used, EN can be connected to either IN or
BIAS. If EN is connected to IN, it should be
connected as close as possible to the largest
capacitance on the input to prevent voltage droops on
that line from triggering the enable circuit.
POWER-GOOD (QFN Package Only)
The power-good (PG) pin is an open-drain output and
can be connected to any 5.5 V or lower rail through
an external pull-up resistor. This pin requires at least
1.1 V on VBIAS in order to have a valid output. The PG
output is high-impedance when VOUT is greater than
VIT + VHYS. If VOUT drops below VIT or if VBIAS drops
below 1.9 V, the open-drain output turns on and pulls
the PG output low. The PG pin also asserts when the
device is disabled. The recommended operating
condition of PG pin sink current is up to 1 mA, so the
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pull-up resistor for PG should be in the range of 10
kΩ to 1 MΩ. The pull-up resistor for PG should be in
the range of 10 kΩ to 1 MΩ. PG is only provided on
the QFN package. If output voltage monitoring is not
needed, the PG pin can be left floating.
The internal protection circuitry of the TPS74401 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74401 into thermal
shutdown degrades device reliability.
INTERNAL CURRENT LIMIT
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
The TPS74401 features a factory-trimmed, accurate
current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply
surges of up to 3.5 A and maintain regulation. The
current limit responds in about 10 ms to reduce the
current during a short-circuit fault. Recovery from a
short-circuit condition is well-controlled and results in
very little output overshoot when the load is removed.
See Figure 27 in the Typical Characteristics section
for short-circuit recovery performance.
The internal current limit protection circuitry of the
TPS74401 is designed to protect against overload
conditions. It is not intended to allow operation above
the rated current of the device. Continuously running
the TPS74401 above the rated current degrades
device reliability.
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +155°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates
excessive
power
dissipation
or
inadequate
heatsinking.
For
reliable
operation,
junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+30°C above the maximum expected ambient
condition of the application. This condition produces a
worst-case junction temperature of +125°C at the
highest
expected
ambient
temperature
and
worst-case load.
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should be
connected as close as possible to the device. This
capacitance also minimizes the effects of parasitic
inductance and resistance of the input source and
can therefore improve stability. To achieve optimal
transient performance and accuracy, the top side of
R1 in Figure 28 should be connected as close as
possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense
point of the input supply as possible. This connection
minimizes the voltage droop on BIAS during transient
conditions and can improve the turn-on response.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
the device depends on input voltage and load
conditions, and can be calculated using Equation 4:
P D + ǒVIN * VOUTǓ
I OUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
The primary conduction path for heat is through the
exposed pad or tab to the printed circuit board (PCB).
The pad or tab can be connected to ground or be left
floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure
the device does not overheat. The maximum
junction-to-ambient thermal resistance depends on
the maximum ambient temperature, maximum device
junction temperature, and power dissipation of the
device, and can be calculated using Equation 5:
ǒ)125°C * T AǓ
R qJA +
PD
(5)
Knowing the maximum RqJA and system air flow, the
minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using
Figure 32 through Figure 34.
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
0.5in
TA
1.0in
RqJA = RqJC + RqCS + RqSA
2.0in
2
2
2
55
50
0 LFM
qJA (°C/W)
45
40
150 LFM
35
250 LFM
30
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 32. PCB Layout and Corresponding RqJA Data, Buried Thermal Plane, No Vias Under Thermal Pad
16
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
0.5in
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
1.0in
TA
2.0in
2
2
2
RqJA = RqJC + RqCS + RqSA
50
45
0 LFM
qJA (°C/W)
40
150 LFM
35
30
250 LFM
25
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 33. PCB Layout and Corresponding RqJA Data, Buried Thermal Plane, Vias Under Thermal Pad
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
RqSA
0.5in
TA
1.0in
2.0in
2
2
2
RqJA = RqJC + RqCS + RqSA
90
80
qJA (°C/W)
70
0 LFM
60
150 LFM
50
40
250 LFM
30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 34. PCB Layout and Corresponding RqJA Data, Top Layer Thermal Plane
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS74401MRGWREP
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
TPS
74401EP
V62/10611-01XE
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
TPS
74401EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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