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TPS780
SBVS083E – JANUARY 2007 – REVISED JANUARY 2015
TPS780xx 150-mA Low-Dropout Regulator, Ultralow-Power, IQ 500 nA With Pin-Selectable,
Dual-Level Output Voltage
1 Features
3 Description
•
•
The TPS780 family of low-dropout (LDO) regulators
offer the benefits of ultralow power, miniaturized
packaging, and selectable dual-level output voltage
levels with the VSET pin.
1
•
•
•
•
•
•
•
•
•
Low IQ: 500 nA
150-mA, Low-Dropout Regulator With PinSelectable Dual Voltage Level Output
Low Dropout: 200 mV at 150 mA
3% Accuracy Over Load, Line, and Temperature
Available in Dual-Level, Fixed-Output Voltages
From 1.5 V to 4.2 V
Available in an Adjustable Version from 1.22 V to
5.25 V or a Dual-Level Output Version
VSET Pin Toggles Output Voltage Between Two
Factory-Programmed Voltage Levels
Stable with a 1.0-μF Ceramic Capacitor
Thermal Shutdown and Overcurrent Protection
CMOS Logic Level-Compatible Enable Pin
Available in DDC (TSOT23-5) or DRV (2-mm ×
2-mm SON-6) Package Options
The ultralow-power and dynamic voltage scaling
(DVS) capability which provides dual-level output
voltages let designers customize power consumption
for specific applications. Designers can now shift to a
lower voltage level in a battery-powered design when
the microprocessor is in sleep mode, further reducing
overall system power consumption. The two voltage
levels are preset at the factory and are stored using
EPROM and are available on fixed output voltage
devices.
The TPS780 series of LDOs are designed to be
compatible with the TI MSP430 and other similar
products. The enable pin is compatible with standard
CMOS logic. The TPS780 series also come with
thermal shutdown and current limit to protect the
device during fault conditions. All packages have an
operating temperature range of TJ = –40°C to 125°C.
For more cost-sensitive applications requiring a duallevel voltage option and only on par IQ, consider the
TPS781 series, with an IQ of 1.0 μA and dynamic
voltage scaling.
2 Applications
•
•
•
•
TI MSP430™ Attach Applications
Power Rails With Programming Mode
Dual Voltage Levels for Power-Saving Mode
Wireless Handsets, Smart Phones, PDAs, MP3
Players, and Other Battery-Operated Handheld
Products
Device Information(1)
PART NUMBER
TPS780xx
PACKAGE
BODY SIZE (NOM)
SOT (5)
2.90 mm x 1.60 mm
SON (6)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4.2V to 5.5V
VIN
2.2V to 3.3V
IN
VOUT
OUT
1mF
1mF
TPS780
On
Off
EN
VSET High = VOUT(LOW)
VSET Low = VOUT(HIGH)
VSET
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS780
SBVS083E – JANUARY 2007 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
15
15
15
16
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
8.3 Do's and Don'ts ....................................................... 19
9
Power Supply Recommendations...................... 20
9.1 Powering the MSP430 Microcontroller.................... 20
10 Layout................................................................... 22
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
22
23
23
23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2012) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Dissipation Ratings table; see Thermal Information ................................................................................................ 4
•
Changed parametric symbol for line and load regulation ...................................................................................................... 5
Changes from Revision C (May 2008) to Revision D
•
2
Page
Updated Figure 47 and Figure 48 ....................................................................................................................................... 12
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SBVS083E – JANUARY 2007 – REVISED JANUARY 2015
5 Pin Configuration and Functions
SOT
5 Pins
Top View
SON
6 Pins
Top View
(1)
OUT
1
N/C
2
VSET/FB
3
Thermal
Pad
(1)
6
IN
5
GND
4
EN
IN
1
GND
2
EN
3
5
OUT
4
VSET/FB
It is recommended that the SON package
thermal pad be connected to ground.
Pin Functions
PIN
I/O
DESCRIPTION
5
O
Regulated output voltage pin. A small (1-μF) ceramic capacitor is needed from this pin to
ground to assure stability. See Input and Output Capacitor Requirements for more details.
2
—
—
Not connected.
VSET/FB
3
4
I
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions. Drive the select
pin (VSET) below 0.4 V to select preset output voltage high. Drive the VSET pin over 1.2 V
to select preset output voltage low.
EN
4
3
I
Enable pin. Drive this pin over 1.2 V to turn on the regulator. Drive this pin below 0.4 V to
put the regulator into shutdown mode, reducing operating current to 18 nA typical.
GND
5
2
—
IN
6
1
I
Thermal
pad
—
—
—
NAME
SON
SOT
OUT
1
N/C
Ground pin. Tie all ground pins to ground for proper operation.
Input pin. A small capacitor is needed from this pin to ground to assure stability. A typical
input capacitor is 1.0 μF. Tie back both input and output capacitor ground to the IC
ground, with no significant impedance between them.
(SON package only) Connect the thermal pad to ground.
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SBVS083E – JANUARY 2007 – REVISED JANUARY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage
Current
(1)
MIN
MAX
VIN
–0.3
+6.0
VEN and VVSET
–0.3
VIN + 0.3 (2)
VOUT
–0.3
VIN + 0.3
IOUT
Indefinite
Total continuous power dissipation, PDISS
(1)
(2)
V
Internally limited
Output short-circuit duration
Temperature
UNIT
See Thermal Information
Operating junction, TJ
–40
125
°C
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VEN and VVSET absolute maximum rating are VIN + 0.3V or +6.0V, whichever is less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage
2.2
5.5
V
VOUT
Output voltage
1.8
4.2
V
VEN
Enable voltage
0
VIN
V
IOUT
Output current
0
150
mA
TJ
Junction temperature
–40
125
°C
6.4 Thermal Information
TPS780xx
THERMAL METRIC (1)
DDC
DRV
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
193.0
65.9
RθJC(top)
Junction-to-case (top) thermal resistance
40.1
87.3
RθJB
Junction-to-board thermal resistance
34.3
35.4
ψJT
Junction-to-top characterization parameter
0.9
1.7
ψJB
Junction-to-board characterization parameter
34.1
35.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
6.1
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VVSET = VEN = VIN, COUT = 1.0 μF, fixed or adjustable, unless otherwise noted. Typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range
VOUT (1)
DC output accuracy
VFB
Internal reference (2)
(adjustable version only)
MIN
TYP
2.2
Nominal
TJ = 25°C, VSET = high/low
Over VIN, IOUT, VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V,
temperature
0 mA ≤ IOUT ≤ 150 mA, VSET = high/low
(3) (4)
MAX
–2%
±1%
+2%
–3.0%
±2.0%
+3.0%
TJ = 25°C, VIN = 4.0 V, IOUT = 75 mA
V
5.25
V
Output voltage range
(adjustable version only)
VIN = 5.5 V, IOUT = 100 μA (2)
ΔVOUT(ΔVIN)
Line regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V,
IOUT = 5 mA
–1%
+1%
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 150 mA
–2%
+2%
VDO
Dropout voltage (5)
VIN = 95% VOUT(nom), IOUT = 150 mA
Vn
Output noise voltage
BW = 100 Hz to 100 kHz, VIN = 2.2 V,
VOUT = 1.2 V, IOUT = 1 mA
VHI
VSET high (output VOUT(LO) selected),
or EN high (enabled)
VLO
VSET low (output VOUT(HI) selected),
or EN low (disabled)
ICL
Output current limit
VOUT = 0.90 × VOUT(nom)
250
1.2
VIN
V
0
0.4
V
mA
230
400
420
800
IOUT = 150 mA
5
IOUT = 0 mA
Ground pin current
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4 V, 2.2 V ≤ VIN < 5.5 V,
TJ = –40°C to 100°C
IVSET
VSET pin current
IEN
EN pin current
mV
μVRMS
86
(6)
IGND
V
1.216
VOUT_RANGE
VFB
UNIT
5.5
150
130
nA
VEN = VVSET = 5.5 V
70
nA
VEN = VVSET = 5.5 V
40
nA
IFB
FB pin current (7)
(Adjustable version only)
VIN = 5.5 V, VOUT = 1.2 V, IOUT = 100 μA
10
nA
PSRR
Power-supply rejection ratio
VIN = 4.3 V,
VOUT = 3.3 V,
IOUT = 150 mA
tTR(H→L)
VOUT transition time (high-to-low)
VOUT = 97% × VOUT(HI)
VOUT_LOW = 2.2 V, VOUT(HI) = 3.3 V,
IOUT = 10 mA
800
μs
tTR(L→H)
VOUT transition time (low-to-high)
VOUT = 97% × VOUT(LO)
VOUT_HIGH = 3.3 V, VOUT(LO) = 2.2 V,
IOUT = 10 mA
800
μs
tSTR
Start-up time (8)
COUT = 1.0 μF, VOUT = 10% VOUT(nom) to
VOUT = 90% VOUT(nom)
500
μs
500 (10)
μs
Shutdown, temperature increasing
160
°C
Reset, temperature decreasing
140
(9)
tSHDN
Shutdown time
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
18
nA
μA
f = 10 Hz
40
f = 100 Hz
20
f = 1kHz
15
IOUT = 150 mA, COUT = 1.0 μF,
VOUT = 2.8 V,
VOUT = 90% VOUT(nom) to
VOUT = 10% VOUT(nom)
–40
dB
°C
125
°C
The output voltage for VSET = low/high is programmed at the factory.
Adjustable version only.
No VSET pin on the adjustable version.
No dynamic voltage scaling on the adjustable version.
VDO is not measured for devices with VOUT(nom) < 2.3 V because minimum VIN = 2.2 V.
IGND = 800 nA (max) up to 100°C.
The TPS78001 FB pin is tied to VOUT. Adjustable version only.
Time from VEN = 1.2 V to VOUT = 90% (VOUT(nom)).
Time from VEN = 0.4 V to VOUT = 10% (VOUT(nom)).
See Shutdown for more details.
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6.6 Typical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
1.0
0.3
0.8
0.2
0.6
VOUT (%)
VOUT (%)
TJ = +25°C
TJ = +125°C
0
-0.1
TJ = +25°C
TJ = +85°C
0.4
0.1
0.2
0
-0.2
TJ = +125°C
-0.4
-0.6
-0.2
TJ = +85°C
TJ = -40°C
-0.8
-1.0
-0.3
2.2
2.7
3.2
IOUT = 5 mA
3.7
4.2
VIN (V)
4.7
5.2
2.7
5.7
VOUT(nom) = 1.22 V
3.2
3.7
IOUT = 5 mA
Figure 1. TPS78001 Line Regulation
4.2
VIN (V)
4.7
5.2
VVSET = 1.2 V
5.7
VOUT(nom) = 2.2 V
Figure 2. TPS780330220 Line Regulation
3
1.0
0.8
2
TJ = -40°C
0.6
TJ = +25°C
0.4
TJ = +25°C
VOUT (%)
1
VOUT (%)
TJ = -40°C
TJ = -40°C
0
-1
0.2
0
-0.2
TJ = +85°C
-0.4
TJ = +85°C
-2
-0.6
-0.8
-3
-1.0
2.7
3.2
3.7
IOUT = 150 mA
4.2
VIN (V)
4.7
5.2
VVSET = 1.2 V
5.7
3.8
VOUT(nom) = 2.2 V
4.2
4.4
IOUT = 5 mA
Figure 3. TPS780330220 Line Regulation
4.6
4.8
VIN (V)
5.0
5.2
VVSET = 0.4 V
5.4
5.6
VOUT(nom) = 3.3 V
Figure 4. TPS780330220 Line Regulation
1.5
3
2
1.0
1
TJ = +125°C
TJ = -40°C
VOUT (%)
VOUT (%)
4.0
0
0.5
TJ = +25°C
0
-1
-0.5
-2
TJ = +85°C
TJ = +25°C
TJ = +85°C
3.8
4.0
IOUT = 150 mA
4.2
4.4
4.6
4.8
VIN (V)
5.0
VVSET = 0.4 V
5.2
5.4
5.6
VOUT(nom) = 3.3 V
0
25
50
75
IOUT (mA)
100
125
150
VOUT(nom) = 3.3 V
Figure 5. TPS780330220 Line Regulation
6
TJ = -40°C
-1.0
-3
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Figure 6. TPS78001 Load Regulation
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
3
3.0
2.5
2
2.0
TJ = -40°C
1
1.0
0.5
VOUT (%)
VOUT (%)
1.5
TJ = -40°C
0
0
-1
-0.5
TJ = +25°C
-1.0
-1.5
TJ = +85°C
-2.0
0
25
50
VVSET = 1.2 V
-3
75
IOUT (mA)
100
125
VIN = 2.7 V
0
150
VOUT(nom) = 2.2 V
Figure 7. TPS780330220 Load Regulation
50
75
IOUT (mA)
100
125
VIN = 3.8 V
150
VOUT(nom) = 3.3 V
Figure 8. TPS780330220 Load Regulation
250
180
TJ = +125°C
TJ = +85°C
160
140
TJ = +125°C
120
100
80
60
40
TJ = +85°C
150
100
50
TJ = -40°C
TJ = +25°C
20
200
VDO (VIN - VOUT) (mV)
VDO (VIN - VOUT) (mV)
25
VVSET = 0.4 V
200
TJ = -40°C
TJ = +25°C
0
0
0
25
50
75
IOUT (mA)
100
VOUT(nom) = 3.3 V
125
0
150
VIN = 0.95 × VOUT(nom)
25
VVSET = 0.4 V
Figure 9. TPS78001 Dropout Voltage vs Output Current
50
75
IOUT (mA)
VOUT(nom) = 3.3 V
100
125
150
VIN = 0.95 × VOUT(nom)
Figure 10. TPS780330220 Dropout Voltage vs Output
Current
250
200
150mA
150
100mA
100
50mA
50
VDO (VIN - VOUT) (mV)
250
VDO (VIN - VOUT) (mV)
TJ = +85°C
-2
TJ = +25°C
200
150mA
150
100mA
100
50mA
50
10mA
10mA
0
0
-40 -25 -10
VOUT(nom) = 3.3
5
20 35 50 65
Temperature (°C)
80
95
110 125
VIN = 0.95 × VOUT(nom)
Figure 11. TPS78001 Dropout Voltage vs Temperature
-40 -25 -10
VVSET = 0.4 V
5
20 35 50 65
Temperature (°C)
VOUT(nom) = 3.3 V
80
95
110 125
VIN = 0.95 × VOUT(nom)
Figure 12. TPS780330220 Dropout Voltage vs Temperature
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
6
8
5
TJ = +85°C
TJ = +125°C
TJ = +125°C
6
IGND (mA)
4
IGND (mA)
TJ = +85°C
7
3
2
5
4
3
TJ = +25°C
TJ = +25°C
TJ = -40°C
2
1
1
TJ = -40°C
0
0
2.2
2.7
IOUT = 50 mA
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
2.2
VOUT(nom) = 1.22 V
2.7
IOUT = 150 mA
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
VOUT(nom) = 1.22 V
Figure 13. TPS78001 Ground Pin Current vs Input Voltage
Figure 14. TPS78001 Ground Pin Current vs Input Voltage
1000
1000
TJ = +125°C
900
800
700
600
IGND (nA)
IGND (nA)
800
TJ = +85°C
700
500
400
300
TJ = +25°C
200
TJ = +125°C
900
TJ = +85°C
600
500
400
300
TJ = -40°C
TJ = +25°C
200
100
TJ = -40°C
100
0
0
2.7
3.2
3.7
IOUT = 0 mA
4.2
VIN (V)
4.7
VVSET = 1.2 V
5.2
5.7
2.7
VOUT(nom) = 2.2 V
3.2
3.7
IOUT = 1 mA
4.2
VIN (V)
4.7
VVSET = 1.2 V
5.2
5.7
VOUT(nom) = 2.2 V
Figure 15. TPS780330220 Ground Pin Current vs Input
Voltage
Figure 16. TPS780330220 Ground Pin Current vs Input
Voltage
6
12
11
10
5
TJ = +125°C
TJ = +85°C
9
IGND (mA)
IGND (mA)
TJ = +125°C
8
4
3
TJ = +85°C
7
6
5
4
2
TJ = +25°C
3
TJ = -40°C
TJ = +25°C
2
1
TJ = -40°C
1
0
0
2.7
3.2
IOUT = 50 mA
3.7
4.2
VIN (V)
4.7
VVSET = 1.2 V
5.2
5.7
VOUT(nom) = 2.2 V
Figure 17. TPS780330220 Ground Pin Current vs Input
Voltage
8
2.7
3.2
IOUT = 150 mA
3.7
4.2
VIN (V)
4.7
VVSET = 1.2 V
5.2
5.7
VOUT(nom) = 2.2 V
Figure 18. TPS780330220 Ground Pin Current vs Input
Voltage
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
1000
1000
900
900
TJ = +125°C
800
TJ = +85°C
600
TJ = +85°C
700
TJ = +25°C
IGND (nA)
700
IGND (nA)
TJ = +125°C
800
500
400
300
600
500
400
300
200
TJ = -40°C
200
TJ = -40°C
100
100
0
0
3.8
4.0
4.2
4.4
IOUT = 0 mA
4.6
4.8
VIN (V)
5.0
VVSET = 0.4 V
5.2
5.4
5.6
3.8
VOUT(nom) = 3.3 V
4.0
4.2
4.4
IOUT = 1 mA
4.6
4.8
VIN (V)
5.0
VVSET = 0.4 V
5.2
5.4
5.6
VOUT(nom) = 3.3 V
Figure 19. TPS780330220 Ground Pin Current vs Input
Voltage
Figure 20. TPS780330220 Ground Pin Current vs Input
Voltage
6
9
8
5
TJ = +85°C
TJ = +125°C
TJ = +125°C
TJ = +85°C
7
4
6
IGND (mA)
IGND (mA)
TJ = +25°C
3
2
5
4
3
TJ = +25°C
TJ = -40°C
TJ = +25°C
2
TJ = -40°C
1
1
0
0
3.8
4.0
4.2
4.4
IOUT = 50 mA
4.6
4.8
VIN (V)
5.0
5.2
VVSET = 0.4 V
5.4
5.6
3.8
VOUT(nom) = 3.3 V
4.2
4.4
IOUT = 150 mA
4.6
4.8
VIN (V)
5.0
VVSET = 0.4 V
5.2
5.4
5.6
VOUT(nom) = 3.3 V
Figure 21. TPS780330220 Ground Pin Current vs Input
Voltage
Figure 22. TPS780330220 Ground Pin Current vs Input
Voltage
10
10
8
8
TJ = +125°C
TJ = +85°C
6
4
2
TJ = +125°C
TJ = +85°C
IGND (mA)
IGND (mA)
4.0
6
4
2
TJ = +25°C
TJ = -40°C
TJ = -40°C
TJ = +25°C
0
0
0
25
VVSET = 1.2 V
50
75
IOUT (mA)
100
VIN = 5.5 V
125
150
VOUT(nom) = 2.2 V
Figure 23. TPS780330220 Ground Pin Current vs Output
Current
0
25
VVSET = 0.4 V
50
75
IOUT (mA)
100
VIN = 5.5 V
125
150
VOUT(nom) = 3.3 V
Figure 24. TPS780330220 Ground Pin Current vs Output
Current
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
60
280
270
50
TJ = -40°C
Current Limit (mA)
TJ = +85°C
IGND (nA)
40
30
TJ = +25°C
20
260
250
TJ = +25°C
240
230
220
10
0
200
2.2
2.7
3.2
3.7
4.2
VIN (V)
IOUT = 0 mA
4.7
5.2
5.7
2.2
2.7
VVSET = 0.4 V
3.2
3.7
4.2
VIN (V)
4.7
VOUT = 90% VOUT(nom)
Figure 25. TPS78001 Shutdown Current vs Input Voltage
5.2
5.7
VOUT(nom) = 1.22 V
Figure 26. TPS78001 Current Limit vs Input Voltage
300
300
290
290
280
Current Limit (mA)
280
Current Limit (mA)
TJ = +85°C
210
TJ = -40°C
TJ = -40°C
270
260
250
TJ = +25°C
240
TJ = +85°C
230
220
TJ = -40°C
260
250
TJ = +25°C
240
TJ = +85°C
230
220
TJ = +125°C
210
270
TJ = +125°C
210
200
200
2.7
3.2
VVSET = 1.2 V
3.7
4.2
VIN (V)
4.7
VOUT = 95% VOUT(nom)
5.2
5.7
3.8
VOUT(nom) = 2.2 V
4.0
4.2
VVSET = 0.4 V
4.4
4.6
4.8
VIN (V)
5.0
VOUT = 95% VOUT(nom)
5.2
5.4
5.6
VOUT(nom) = 3.3
V
Figure 27. TPS780330220 Current Limit vs Input Voltage
1.0
4
0.8
3
0.6
IVSET (nA)
IFB (nA)
Figure 28. TPS780330220 Current Limit vs Input Voltage
5
2
TJ = +25°C
TJ = -40°C
TJ = +85°C
0.4
VIN max
1
VIN min
0
0
-40 -25 -10
IOUT = 0 mA
5
20 35 50 65
Temperature (°C)
80
95
110 125
2.7
3.2
IOUT = 100 μA
VOUT(nom) = 1.22 V
Figure 29. TPS78001 Feedback Pin Current vs Temperature
10
0.2
3.7
4.2
VIN (V)
VVSET = 1.2 V
4.7
5.2
5.7
VOUT(nom) = 2.2 V
Figure 30. TPS780330220 VSET Pin Current vs Input Voltage
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
2.5
2.0
TJ = +125°C
1.8
2.0
1.6
1.4
IEN (nA)
IVSET (nA)
1.5
1.0
TJ = -40°C
TJ = +85°C
0.5
TJ = -40°C
TJ = +25°C
0.8
0.4
0.2
TJ = +25°C
0
-0.5
3.8
4.0
4.2
4.4
IOUT = 100 μA
4.6
4.8
VIN (V)
5.0
5.2
VVSET = 0.4 V
5.4
5.6
2.2
VOUT(nom) = 3.3 V
1.8
1.6
1.6
1.4
1.4
1.2
1.2
TJ = +85°C
TJ = +25°C
IEN (nA)
2.0
1.8
0.8
TJ = -40°C
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
VOUT(nom) = 1.22 V
Figure 32. TPS78001 Enable Pin Current vs Input Voltage
2.0
1.0
2.7
IOUT = 1 mA
Figure 31. TPS780330220 VSET Pin Current vs Input Voltage
IEN (nA)
TJ = +85°C
1.0
0.6
0
1.0
TJ = +85°C
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
TJ = -40°C
TJ = +25°C
0
2.7
3.2
3.7
IOUT = 100 μA
4.2
VIN (V)
4.7
5.2
VVSET = 1.2 V
5.7
3.8
4.0
4.2
4.4
IOUT = 100 μA
VOUT(nom) = 2.2 V
Figure 33. TPS780330220 Enable Pin Current vs Input
Voltage
4.6
4.8
VIN (V)
5.0
5.2
VVSET = 0.4 V
5.4
5.6
VOUT(nom) = 3.3 V
Figure 34. TPS780330220 Enable Pin Current vs Input
Voltage
1.2
1.2
1.1
1.1
1.0
1.0
VEN On
0.9
VEN (V)
VEN (V)
1.2
0.8
0.7
VEN On
0.9
0.8
0.7
VEN Off
VEN Off
0.6
0.6
0.5
0.5
0.4
0.4
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
IOUT = 1 mA
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
IOUT = 1 mA
Figure 35. TPS78001 Enable Pin Hysteresis vs Temperature
Figure 36. TPS780330220 Enable Pin Hysteresis vs
Temperature
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
0.4
1
0.3
0.1mA
0
%DVOUT (V)
%VOUT (V)
0.2
0.1
0
-0.1
5mA
-1
150mA
-0.2
-0.3
-0.4
-2
-40 -25 -10
5
20 35 50 65
Temperature (°C)
IOUT = 1 mA
80
VIN = 3.8 V
95
110 125
-40 -25 -10
VOUT(nom) = 3.3 V
1
0.1mA
0
5mA
-1
150mA
-2
-3
-40 -25 -10
5
20 35 50 65
Temperature (°C)
VVSET = 0.4 V
80
VIN = 3.8 V
95
80
VIN = 2.7 V
95
110 125
VOUT(nom) = 2.2 V
Figure 38. TPS780330220 %ΔVOUT vs Temperature
Output Spectral Noise Density (mV/ÖHz)
%DVOUT (V)
2
20 35 50 65
Temperature (°C)
VVSET = 1.2 V
Figure 37. TPS78001 %ΔVOUT vs Temperature
3
5
100
10
150mA
109mVRMS
1
0.1
50mA
109mVRMS
0.01
1mA
108mVRMS
0.001
10
110 125
100
1k
Frequency (Hz)
CIN = 1 μF
VIN = 2.7 V
VOUT(nom) = 3.3 V
Figure 39. TPS780330220 %ΔVOUT vs Temperature
COUT = 2.2 μF
10k
100k
VVSET = 1.2 V
Figure 40. TPS780330220 Output Spectral Noise Density vs
Frequency
80
VIN
PSRR (dB)
60
50
40
50mA
Enable
VOUT
Load Current
30
0V
20
VIN = 0.0V to 5.0V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Current (50mA/div)
Voltage (1V/div)
1mA
70
150mA
10
0
10
100
VIN = 2.7 V
1k
10k
100k
Frequency (Hz)
VOUT = 1.2 V
1M
COUT = 2.2 μF
Figure 41. TPS78001 Ripple Rejection vs Frequency
12
Time (20ms/div)
10M
Figure 42. TPS780330220 Input Voltage Ramp vs Output
Voltage
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
VSET
Load Current
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
VIN
Load Current
0A
0V
0V
VIN = 0.0V to 5.5V
VOUT = 2.2V
IOUT = 100mA
COUT = 10mF
VOUT
Time (20ms/div)
Time (1ms/div)
Figure 43. TPS780330220 Output Voltage vs Enable (Slow
Ramp)
Figure 44. TPS780330220 Input Voltage vs Delay to Output
VIN
VIN
1V/div
1V/div
VOUT
VIN = 4.0V to 4.5V
VOUT = 2.2V
IOUT = 150mA
Slew Rate = 1V/ms
VOUT
VIN = 4.0V to 4.5V
VOUT = 3.3V
IOUT = 150mA
Slew Rate = 1V/ms
Time (200ms/div)
Time (200ms/div)
Figure 45. TPS780330220 Line Transient Response
Figure 46. TPS780330220 Line Transient Response
VIN
Enable
VOUT
Load
Current
VIN = 5.5V
VOUT = 3.3V
IOUT = 17mA to 60mA
COUT = 10mF
Current
(20mA/div)
Load
Current
VOUT
VIN
Current
(10mA/div)
VIN = 5.5V
VOUT = 3.3V
IOUT = 5mA to 15mA
COUT = 10mF
Enable
Voltage
(100mV/div)
Voltage
(100mV/div)
Current (50mA/div)
VOUT
Voltage (1V/div)
Enable
Current (50mA/div)
Voltage (1V/div)
VIN
0A
0A
Time (5ms/div)
Time (2ms/div)
Figure 47. TPS780330220 Load Transient Response
Figure 48. TPS780330220 Load Transient Response
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT =
100 μA, VEN = VVSET = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
VIN = 5.50V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
0V
Voltage (1V/div)
Load Current
VIN
Enable
VOUT
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Load
Current
0V
Time (1ms/div)
Current (50mA/div)
VOUT
VIN
Current (50mA/div)
Voltage (1V/div)
Enable
Time (1ms/div)
Figure 49. TPS780330220 Enable Pin vs Output Voltage
Response and Output Current
Figure 50. TPS780330220 Enable Pin vs Output Voltage
Delay
VOUT
VOUT
1V/div
VSET
VSET
1V/div
VIN = 5.0V
Enable = VIN
IOUT = 150mA
VOUT Transitioning from 2.2V to 3.3V
VIN = 5.0V
IOUT = 150mA
VOUT Transitioning from 3.3V to 2.2V
Time (500ms/div)
Time (500ms/div)
Figure 51. TPS780330220 VSET Pin Toggle
Figure 52. TPS780330220 VSET Pin Toggle
Current (50mA/div)
Voltage (1V/div)
VIN
VOUT
VSET
100mA
VIN = 5.5V
VOUT = 3.3V
50mA
IOUT = 150mA
to 100mA 0A
COUT = 10mF
Load Current
Time (50ms/div)
Figure 53. TPS780330220 VSET Pin Toggle (Slow Ramp)
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7 Detailed Description
7.1 Overview
The TPS780 family of low-dropout regulators (LDOs) is designed specifically for battery-powered applications
where ultralow quiescent current is a critical parameter. The absence of pulldown circuitry at the output of the
LDO provides the flexibility to use the regulator output capacitor as a temporary backup power supply for a short
period of time (for example, during battery replacement). The TPS780 family is compatible with the TI MSP430
and other similar products. The enable pin (EN) is compatible with standard CMOS logic. This LDO family is
stable with any output capacitor greater than 1.0 µF.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
EPROM
EN
Bandgap
MUX
Thermal
Shutdown
Active
PullDown
(1)
VSET/FB
10kW
LOGIC
GND
(1)
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions.
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS780 is internally current-limited to protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do
not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS780 family has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting to 5% of rated output current may be appropriate.
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Feature Description (continued)
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage CMOS levels. When
shutdown capability is not required, connect EN to the IN pin, as shown in Figure 54.
VIN
IN
VOUT
OUT
1 mF
1 mF
TPS780xx
EN
GND
Figure 54. Circuit Showing EN Tied High When Shutdown Capability is not Required
7.3.3 Active VOUT Pulldown
In the TPS780 series, the active pulldown discharges VOUT when the device is off. However, the input voltage
must be greater than 2.2 V for the active pulldown to work.
7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
TJ
Normal
VIN > VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Dropout
VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Disabled
—
VEN < VEN(LO)
—
TJ > TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
• The enable voltage has previously exceeded the enable rising threshold voltage (VEN > VEN(HI)) and not yet
decreased below the enable falling threshold.
• The output current is less than the current limit (IOUT < ICL).
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage (VEN < VEN(LO)) or has not yet exceeded
the enable rising threshold.
• The device junction temperature is greater than the thermal shutdown temperature (TJ > TSD).
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7.5 Programming
7.5.1 Programming the TPS78001 Adjustable LDO Regulator
The output voltage of the TPS78001 adjustable regulator is programmed using an external resistor divider as
shown in Figure 55. The output voltage operating range is 1.2 V to 5.1 V, and is calculated using Equation 1:
R
VOUT = VFB ´ 1 + 1
R2
(
)
where
•
VFB = 1.216 V typical (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 1.2-μA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided because leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VOUT. Table 2 lists several
common output voltages and resistor values. The recommended design procedure is to choose R2 = 1 MΩ to set
the divider current at 1.2 μA, and then calculate R1 using Equation 2:
V
R1 = OUT - 1 ´ R2
VFB
(2)
(
)
VIN
IN
VOUT
OUT
1mF
1mF
R1
TPS78001
FB
EN
R2
GND
VOUT = VFB ´ (1 +
R1
)
R2
Figure 55. TPS78001 Adjustable LDO Regulator Programming
Table 2. Output Voltage Programming Guide
OUTPUT VOLTAGE
R1
R2
1.8 V
0.499 MΩ
1 MΩ
2.8 V
1.33 MΩ
1 MΩ
5.0 V
3.16 MΩ
1 MΩ
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS780 family of LDOs is factory-programmable to have a fixed output. Note that during start-up or steadystate conditions, do not allow the EN pin voltage to exceed VIN + 0.3 V.
8.2 Typical Application
4.2V to 5.5V
VIN
2.2V to 3.3V
IN
VOUT
OUT
1mF
1mF
TPS780
On
Off
EN
VSET High = VOUT(LOW)
VSET Low = VOUT(HIGH)
VSET
GND
Figure 56. Typical Application Circuit
8.2.1 Design Requirements
Table 3. Design Paramters
PARAMETER
DESIGN REQUIREMENT
Input Voltage
5V
Output Voltage High
3.6 V
Output Voltage Low
2V
Maximum Output Current
100 mA
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND pin current, and power the load. Select input and output capacitors based on application needs.
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if
the device is not located near the power source. If source impedance is not sufficiently low, a 0.1-μF input
capacitor may be necessary to ensure stability.
The TPS780 family is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at
the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1.0 Ω. With tolerance and dc bias effects, the minimum
capacitance to ensure stability is 1 μF.
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8.2.2.2 Dropout Voltage
The TPS780 family uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance
is the RDS(on) of the PMOS pass element. VDO approximately scales with output current because the PMOS
device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are
degraded as (VIN – VOUT) approaches dropout. This effect is shown in Typical Characteristics. Refer to
application report SLVA207, Understanding LDO Dropout, available from www.ti.com.
8.2.2.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases duration of the transient response. For more information, see Figure 48.
8.2.2.4 Minimum Load
The TPS780 family is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at
very light output loads. The TPS780 employs an innovative, low-current circuit under very light or no-load
conditions, resulting in improved output voltage regulation performance down to zero output current. See for the
load transient response.
100
80
1mA
70
10
60
150mA
109mVRMS
1
PSRR (dB)
Output Spectral Noise Density (mV/ÖHz)
8.2.3 Application Curves
0.1
50mA
109mVRMS
0.01
10
100
1k
Frequency (Hz)
40
50mA
30
20
150mA
10
1mA
108mVRMS
0.001
50
0
10k
100k
10
CIN = 1 μF, COUT = 2.2 μF, VVSET = 1.2 V, VIN = 2.7 V
Figure 57. TPS780330220 Output Spectral Noise Density
vs Frequency
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 2.7 V, VOUT = 1.2 V, COUT = 2.2 μF
Figure 58. TPS78001 Ripple Rejection vs Frequency
8.3 Do's and Don'ts
Place at least one 1-μF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND of the
regulator.
Do not exceed the absolute maximum ratings.
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9 Power Supply Recommendations
For best performance, connect a low-output impedance power supply directly to the IN pin of the TPS780.
Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin
during start-up or load transient events. If inductive impedances are unavoidable, use an input capacitor.
9.1 Powering the MSP430 Microcontroller
Several versions of the TPS780 are ideal for powering the MSP430 microcontroller. Table 4 shows potential
applications of some voltage versions.
Table 4. Typical MSP430 Applications
DEVICE
VOUT(HI)
(TYP)
VOUT(LO)
(TYP)
TPS780360200
3.6 V
2.0 V
VOUT, MIN > 1.800 V required by many
MSP430s. Allows lowest power
consumption operation.
TPS780360220
3.6 V
2.2 V
VOUT, MIN > 2.200 V required by some
MSP430s FLASH operation.
TPS780360300
3.6 V
3.0 V
VOUT, MIN > 2.700 V required by some
MSP430s FLASH operation.
TPS780360220
3.6 V
2.2 V
VOUT, MIN < 3.600 V required by some
MSP430s. Allows highest speed operation.
APPLICATION
The TPS780 family offers many output voltage versions to allow designers to optimize the supply voltage for the
processing speed required of the MSP430. This flexible architecture minimizes the supply current consumed by
the particular MSP430 application. The MSP430 total system power can be reduced by substituting the 500-nA
IQ TPS780 series LDO in place of an existing ultralow IQ LDO (typical best case = 1 μA). Additionally, DVS allows
for increasing the clock speed in active mode (MSP430 VCC = 3.6 V). The 3.6-V VCC reduces the MSP430 time in
active mode. In low-power mode, MSP430 system power can be further reduced by lowering the MSP430 VCC to
2.2 V in sleep mode.
Key features of the TPS780 series are an ultralow quiescent current (500 nA), DVS, and miniaturized packaging.
The TPS780 family are available in SON-6 and TSOT-23 packages. Figure 59 shows a typical MSP430 circuit
powered by an LDO without DVS. Figure 60 is an MSP430 circuit using a TPS780 LDO that incorporates an
integrated DVS, thus simplifying the circuit design. In a circuit without DVS, as Figure 59 illustrates, VCC is
always at 3.0 V. When the MSP430 goes into sleep mode, VCC remains at 3.0 V; if DVS is applied, VCC could be
reduced in sleep mode. In Figure 60, the TPS780 LDO with integrated DVS maintains 3.6-V VCC until a logic high
signal from the MSP430 forces VOUT to level shift VOUT from 3.6 V down to 2.2 V, thus reducing power in sleep
mode.
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3.0V
VIN
VCC
VOUT
1mF
1 mF
LDO
MSP430
I/O
VSS
GND
VCC = 3.0V
5mA
Active
Mode
1.6mA IQ
LPM3/Sleep Mode
Figure 59. Typical LDO Without DVS
2.2V to 3.6V
VIN
VOUT
1mF
VCC
1 mF
TPS780
MSP430
VSET
I/O
GND
VSS
VCC = 3.6V
VCC = 2.2V
5mA
Active
Mode
Current
700nA IQ
LPM3/Sleep Mode
Figure 60. TPS780 With Integrated DVS
The other benefit of DVS is that it allows a higher VCC voltage on the MSP430, increasing the clock speed and
reducing the active mode dwell time.
The total system power savings is outlined in Table 5, Table 6, and Table 7. In Table 5, the MSP430 power
savings are calculated for various MSP430 devices using a TPS780 series with integrated DVS versus a
standard ultralow IQ LDO without DVS. In Table 6, the TPS780 series quiescent power is calculated for a VIN of
4.2 V, with the same VIN used for the ultralow IQ LDO. Quiescent power dissipation in an LDO is the VIN voltage
times the ground current, because zero load is applied. After the dissipation power is calculated for the individual
LDOs in Table 6, simple subtraction outputs the LDO power savings using the TPS780 series. Table 7 calculates
the total system power savings using a TPS780 series LDO in place of an ultralow IQ 1.2-μA LDO in an
MSP430F1121 application. There are many different versions of the MSP430. Actual power savings vary
depending on the selected device.
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Table 5. DDV MSP430 Power Savings With the TPS780 Series on Selected MSP430 Devices
DEVICE
LPM3 AT VCC = 3 V, IQ
(μA)
LPM3 AT
VCC = 3.0 V × IQ
(μW)
LPM3 AT
VCC = 2.2 V, IQ
(μA)
LPM3 AT
VCC = 2.2 V × IQ
(μW)
μW SAVINGS
USING ONLY DVS
MSP430F1121
1.6
4.8
0.7
1.5
3.3
MSP430F149
1.6
4.8
0.9
2.0
2.8
MSP430F2131
0.9
2.7
0.7
1.5
1.2
MSP430F249
1.0
3.0
0.9
2.0
1.0
MSP430F413
0.9
2.7
0.7
1.5
1.2
MSP430F449
1.6
4.8
1.1
2.4
2.4
Table 6. Typical Ultralow IQ LDO Quiescent Power Dissipation vs the TPS780 Series
MSP430 SYSTEM
POWER SAVINGS
USING THE TPS780
SERIES
TYPICAL ULTRALOW IQ
LDO AT 25°C AMBIENT
TYPICAL ULTRALOW IQ
LDO AT 25°C AMBIENT
POWER DISSIPATION
TPS780 SERIES
TYPICAL IQ AT 25°C
AMBIENT
TPS780 SERIES AT 25°C
AMBIENT, POWER
DISSIPATION
IQ
(μA)
IQ × VIN = 4.2 V
(μW)
TPS780 IQ
(μA)
IQ × VIN = 4.2 V
(μW)
Quiescent Power
Dissipation Savings
(μW)
1.20
5.04
0.42
1.76
3.28
Table 7. Total System Power Dissipation
Typical 1.2 μA LDO, no DVS
TPS780 Series with DVS
(1)
LDO DISSIPATION
MSP430 DISSIPATION
TOTAL SYSTEM POWER IN
SLEEP MODE 3
5.04 μW
4.8 μW (1)
9.84 μW
1.76 μW
(1)
3.26 μW
1.5 μW
Value taken from Table 5 and relative to the MSP430F1121.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), design the printed circuit
board (PCB) with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND
pin of the device. In addition, the output capacitor must be as close as possible to the ground pin of the device to
provide a common reference for regulation purposes. High ESR capacitors may degrade PSRR.
10.1.2 Package Mounting
Solder pad footprint recommendations for the TPS780 series are available from the Texas Instruments web site
at www.ti.com through the TPS780 series product folders.
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10.2 Layout Example
VIN
VOUT
1
CIN
5
COUT
2
3
4
GND PLANE
Represents via used for
application-specific connections
Figure 61. TPS780xx DDC Package Layout Example
10.3 Thermal Considerations
Thermal protection disables the device output when the junction temperature rises to approximately 160°C,
allowing the device to cool. After the junction temperature cools to approximately 140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off again. This cycling limits the dissipation of the regulator, protecting it from damage
as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 105°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.
The internal protection circuitry of the TPS780 family is designed to protect against overload conditions.
However, this circuitry is not intended to replace proper heatsinking. Continuously running the TPS780 series
into thermal shutdown degrades device reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in Thermal Information.
Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on
input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the
voltage drop across the output pass element (VIN to VOUT), as shown in Equation 3:
PD = (VIN - VOUT) ´ IOUT
(3)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS780.
The TPS780XXEVM-301 evaluation module (and related user's guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS780 series is available through the product folders under
Tools & Software.
11.1.2 Device Nomenclature
Table 8. Device Nomenclature (1)
PRODUCT
TPS780vvvxxx yyy z
(1)
(2)
(3)
(4)
(2)
VOUT
vvv is the nominal output voltage for VOUT(HI) and corresponds to VSET pin low.
xxx is the nominal output voltage for VOUT(LO) and corresponds to VSET pin high.
yyy is the package designator.
z is the tape and reel quantity (R = 3000, T = 250).
Adjustable version (3) (4)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Additional output voltage combinations are available on a quick-turn basis using innovative, factory EPROM programming. Minimum
order quantities apply; contact your sales representative for details and availability.
To order the adjustable version, use TPS78001YYYZ.
The device is either fixed voltage, dual-level VOUT, or adjustable voltage only. Device design does not permit a fixed and adjustable
output simultaneously.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Application note: Understanding LDO Dropout, SLVA207.
• TPS780XXEVM-301 User's Guide, SLVU235.
11.3 Trademarks
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
(1)
TPS78001DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CEA
Samples
TPS78001DDCRG4
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CEA
Samples
TPS78001DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CEA
Samples
TPS78001DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEA
Samples
TPS78001DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CEA
Samples
TPS780180300DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RAX
Samples
TPS780180300DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RAX
Samples
TPS780230300DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
NXP
Samples
TPS780230300DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
NXP
Samples
TPS780270200DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVN
Samples
TPS780270200DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVN
Samples
TPS780300250DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
OAI
Samples
TPS780300250DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
OAI
Samples
TPS780330200DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13A
Samples
TPS780330200DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13A
Samples
TPS780330220DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CEC
Samples
TPS780330220DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CEC
Samples
TPS780330220DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CEC
Samples
TPS780330220DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CEC
Samples
The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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