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TPS782
SBVS115D – AUGUST 2008 – REVISED JANUARY 2015
TPS782 500-nA IQ,150-mA, Ultra-Low Quiescent Current
Low-Dropout Linear Regulator
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS782 family of low-dropout regulators (LDOs)
offers the benefits of ultra-low power and miniaturized
packaging.
1
Low IQ: 500 nA
150-mA, Low-Dropout Regulator
Input Voltage Range: 2.2 V to 5.5 V
Low-Dropout at 25°C, 130 mV at 150 mA
Low-Dropout at 85°C, 175 mV at 150 mA
3% Accuracy Over Load, Line, and Temperature
Stable with a 1.0-μF Ceramic Capacitor
Thermal Shutdown and Overcurrent Protection
CMOS Logic Level-Compatible Enable Pin
Available in DDC (TSOT23-5) or DRV (2-mm x 2mm SON-6) Packages
This LDO is designed specifically for battery-powered
applications where ultra-low quiescent current is a
critical parameter. The TPS782, with ultra-low IQ (500
nA), is ideal for microprocessors, microcontrollers,
and other battery-powered applications.
The ultra-low power and miniaturized packaging allow
designers to customize power consumption for
specific applications.
The TPS782 family is designed to be compatible with
the TI MSP430 and other similar products. The
enable pin (EN) is compatible with standard CMOS
logic. This device allows for minimal board space
because of miniaturized packaging and a potentially
small output capacitor. The TPS782 series also
features thermal shutdown and current limit to protect
the device during fault conditions. All packages have
an operating temperature range of TJ = –40°C to
125°C.
2 Applications
•
•
•
•
TI MSP430 Attach Applications
Wireless Handsets and Smart Phones
MP3 Players
Battery-Operated Handheld Products
For high-performance applications that require a duallevel voltage option, consider the TPS780 series, with
an IQ of 500 nA and dynamic voltage scaling.
Device Information(1)
PART NUMBER
TPS782
PACKAGE
BODY SIZE (NOM)
SOT (5)
2.90 mm x 1.60 mm
SON (6)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VIN
IN
VOUT
OUT
1mF
1mF
TPS782xx
On
Off
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS782
SBVS115D – AUGUST 2008 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
8.3 Do's and Don’ts....................................................... 13
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 14
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Protection................................................
Power Dissipation .................................................
14
14
14
14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2014) to Revision D
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Changed document format to latest data sheet standards; moved existing sections ............................................................ 1
•
Changed factory programming feature bullet ........................................................................................................................ 1
•
Added input voltage range feature bullet ............................................................................................................................... 1
•
Changed Applications list ...................................................................................................................................................... 1
•
Changed Description section text (all paragraphs) ................................................................................................................ 1
•
Added simplified schematic to front page .............................................................................................................................. 1
•
Deleted footnotes from pin configuration drawings ............................................................................................................... 3
•
Changed pin descriptions throughout Pin Functions table .................................................................................................... 3
•
Changed operating junction temperature range maximum value in Absolute Maximum Ratings table................................. 4
•
Deleted Dissipation Ratings table; see Thermal Information table......................................................................................... 4
•
Changed symbol and parameter names for clarity in Electrical Characteristics table .......................................................... 5
Changes from Revision B (May 2010) to Revision C
•
Page
Changed IQ value in Description section from 1 µA to 500 nA .............................................................................................. 1
Changes from Revision A (September 2008) to Revision B
Page
•
Changed first bullet of Features list........................................................................................................................................ 1
•
Updated title of data sheet...................................................................................................................................................... 1
•
Changed ground pin current, IOUT = 0mA typical specification from 1.0 μA to 0.42 μA ......................................................... 5
•
Added Figure 6 ...................................................................................................................................................................... 6
2
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SBVS115D – AUGUST 2008 – REVISED JANUARY 2015
5 Pin Configuration and Functions
DDC PACKAGE
TSOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
OUT
4
GND
DRV PACKAGE
2-mm x 2-mm SON-6
(TOP VIEW)
OUT
1
N/C
2
GND
3
Thermal
Pad
6
IN
5
GND
4
EN
Pin Functions
PIN
I/O
DESCRIPTION
5
O
Regulated output voltage pin. A small (1-μF) ceramic capacitor is needed from this pin to
ground to assure stability. See the Input and Output Capacitor Requirements in the
Application and Implementation section for more details.
2
—
—
No internal connection.
EN
4
3
I
GND
3, 5
2, 4
—
IN
6
1
I
Thermal
pad
Thermal
pad
—
—
NAME
DRV
DDC
OUT
1
NC
Enable pin. Drive this pin over 1.2 V to turn on the regulator. Drive this pin below 0.4 V to
put the regulator into shutdown mode, reducing operating current to 18 nA typical.
Ground pin. Tie all ground pins to ground for proper operation.
Input pin. For stable operation, place a small, 0.1-µF capacitor from this pin to ground;
typical input capacitor = 1.0 µF. Tie back both input and output capacitor grounds to the
IC ground, with no significant impedance between them.
Connect the thermal pad to ground.
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SBVS115D – AUGUST 2008 – REVISED JANUARY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage
Current
(1)
MIN
MAX
UNIT
Input voltage range
–0.3
6
V
Enable
–0.3
VIN + 0.3
V
Output voltage range
–0.3
VIN + 0.3
V
Maximum output current
Internally limited
Output short-circuit duration
A
Indefinite
Total continuous power dissipation, PDISS
See Thermal Information
Operating junction temperature, TJ
–40
160
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
2.2
VOUT
Output voltage
VEN
Enable voltage
IOUT
Output current
TJ
Junction temperature
NOM
MAX
UNIT
5.5
V
1.8
4.2
V
0
VIN
V
0
150
mA
–40
125
°C
6.4 Thermal Information
TPS782
THERMAL METRIC (1)
DRV
DDC
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
65.9
193.0
RθJC(top)
Junction-to-case (top) thermal resistance
87.3
40.1
RθJB
Junction-to-board thermal resistance
35.4
34.3
ψJT
Junction-to-top characterization parameter
1.7
0.9
ψJB
Junction-to-board characterization parameter
35.8
34.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.1
—
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater;
IOUT = 100 μA, VEN = VIN, COUT = 1.0 μF, fixed VOUT test conditions, unless otherwise noted. Typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
VIN
Input voltage range
2.2
VOUT
DC output accuracy
ΔVOUT(ΔVIN)
Line regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V,
IOUT = 5 mA
±1%
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 150 mA
±2%
VDO
Dropout voltage (1)
VIN = 95% VOUT(nom), IOUT = 150 mA
ILIM
Output current limit
VOUT = 0.90 × VOUT(nom)
Nominal
TJ = 25°C
Over VIN, IOUT, VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V,
temperature
0 mA ≤ IOUT ≤ 150 mA
MAX
–2%
±1%
+2%
–3%
±2%
3%
150
IOUT = 0 mA
UNIT
5.5
V
130
250
mV
230
400
mA
0.42
1.3
μA
IGND
Ground pin current
IEN
EN pin current
VEN = 5.5V
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4 V, 2.2 V ≤ VIN < 5.5 V,
TJ = –40°C to 100°C
18
f = 10 Hz
40
dB
Power-supply rejection ratio
VIN = 4.3 V,
VOUT = 3.3 V,
IOUT = 150 mA
f = 100 Hz
20
dB
f = 1 kHz
15
dB
108
μVRMS
500
μs
500 (4)
μs
160
°C
PSRR
IOUT = 150 mA
Vn
Output noise voltage
BW = 100 Hz to 100 kHz, VIN = 3.2 V,
VOUT = 2.7 V, IOUT = 1 mA
tSTR
Startup time (2)
COUT = 1.0 μF, VOUT = 10% VOUT(nom) to
VOUT = 90% VOUT(nom)
(3)
tSHDN
Shutdown time
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
μA
8
IOUT = 150 mA, COUT = 1.0 μF,
VOUT = 2.8 V,
VOUT = 90% VOUT(nom) to
VOUT = 10% VOUT(nom)
Shutdown, temperature increasing
Reset, temperature decreasing
40
nA
130
nA
140
–40
°C
125
°C
VDO is not measured for devices with VOUT(nom) ≤ 2.3 V because minimum VIN = 2.2 V.
Time from VEN = 1.2 V to VOUT = 90% (VOUT(nom)).
Time from VEN = 0.4 V to VOUT = 10% (VOUT(nom)).
See Shutdown in the Feature Description section for more details.
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6.6 Typical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT
= 100 μA, VEN = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
3
1.0
0.8
TJ = -40°C
0.6
0.4
1
0.2
VOUT (%)
VOUT (%)
2
TJ = +25°C
0
-0.2
TJ = +85°C
-0.4
TJ = -40°C
0
-1
-0.6
-2
TJ = +85°C
-0.8
-3
-1.0
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
3.8
5.6
Figure 1. Line Regulation, IOUT = 5 mA, TPS78227
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
Figure 2. Line Regulation, IOUT = 150 mA, TPS78227
3
250
TJ = +125°C
VDO (VIN - VOUT) (mV)
2
TJ = -40°C
1
VOUT (%)
TJ = +25°C
0
-1
TJ = +25°C
TJ = +85°C
200
TJ = +85°C
150
100
50
-2
TJ = -40°C
TJ = +25°C
0
-3
0
25
50
75
IOUT (mA)
100
125
150
Figure 3. Load Regulation, VIN = 3.8 V, TPS78227
0
25
50
75
IOUT (mA)
100
125
150
Figure 4. Dropout Voltage vs Output Current, VIN = 0.95 ×
VOUT(nom), TPS78227
250
900
TJ = +85°C
600
150
100mA
100
TJ = +25°C
500
400
300
50mA
TJ = -40°C
200
50
100
10mA
0
0
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95
110 125
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
VIN (V)
Figure 5. Dropout Voltage vs Junction Temperature, VIN =
0.95 × VOUT(nom), TPS78227
6
TJ = +125°C
700
150mA
IGND (nA)
VDO (VIN - VOUT) (mV)
800
200
Figure 6. Ground Pin Current vs Input Voltage, IOUT = 0 mA,
TPS78233
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT
= 100 μA, VEN = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
3
6
5
2
TJ = +125°C
TJ = +85°C
1
VOUT (%)
IGND (mA)
4
3
2
0
-1
TJ = +25°C
TJ = -40°C
1
-2
0
TJ = +85°C
TJ = +25°C
-3
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
3.8
5.6
Figure 7. Ground Pin Current vs Input Voltage, IOUT = 50
mA, TPS78227
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
Figure 8. Ground Pin Current vs Input Voltage, IOUT = 150
mA, TPS78227
300
2.0
290
1.8
280
1.6
270
1.4
TJ = -40°C
260
250
IEN (nA)
Current Limit (mA)
TJ = -40°C
TJ = +25°C
240
TJ = +85°C
230
220
TJ = +25°C
1.0
TJ = +85°C
0.8
0.6
0.4
TJ = +125°C
210
TJ = -40°C
1.2
0.2
200
0
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
Figure 9. Current Limit vs Input Voltage, VOUT = 95%
VOUT(nom), TPS78227
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
Figure 10. Enable Pin Current vs Input Voltage, IOUT = 100
μA, TPS78227
1.2
1
1.1
0.1mA
0.9
VEN On
%DVOUT (V)
VEN (V)
1.0
0.8
0.7
0
5mA
-1
VEN Off
150mA
0.6
0.5
0.4
-2
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95
110 125
Figure 11. Enable Pin Hysteresis vs Junction Temperature,
IOUT = 1 mA, TPS78227
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95
110 125
Figure 12. %ΔVOUT vs Junction Temperature, VIN = 3.3 V,
TPS78227
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Typical Characteristics (continued)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT
= 100 μA, VEN = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
Output Spectral Noise Density (mV/ÖHz)
3
2
%DVOUT (V)
1
0.1mA
0
5mA
-1
150mA
-2
-3
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95
100
10
1
0.1
50mA
109mVRMS
0.01
1mA
108mVRMS
0.001
110 125
Figure 13. %ΔVOUT vs Junction Temperature, VIN = 3.7 V,
TPS78227
150mA
109mVRMS
10
100
VIN
PSRR (dB)
50
40
50mA
Enable
VOUT
VIN = 0.0V to 5.0V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Load Current
30
0V
20
100k
Current (50mA/div)
Voltage (1V/div)
1mA
60
10k
Figure 14. Output Spectral Noise Density vs Frequency, CIN
= 1 μF, COUT = 2.2 μF, VIN = 3.2 V, TPS78227
80
70
1k
Frequency (Hz)
150mA
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Time (20ms/div)
10M
Figure 16. Input Voltage Ramp vs Output Voltage,
TPS78233
Figure 15. Ripple Rejection vs Frequency, VIN = 4.2 V, VOUT
= 2.7 V, COUT = 2.2 μF, TPS78227
Load Current
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
0V
0A
0V
Time (20ms/div)
VIN = 0.0V to 5.5V
VOUT = 2.2V
IOUT = 100mA
COUT = 10mF
VOUT
Time (1ms/div)
Figure 17. Output Voltage vs Enable (Slow Ramp),
TPS78233
8
VIN
Load Current
Current (50mA/div)
VOUT
Voltage (1V/div)
Enable
Current (50mA/div)
Voltage (1V/div)
VIN
Figure 18. Input Voltage vs Delay to Output, TPS78222
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Typical Characteristics (continued)
Enable
Enable
Voltage (1V/div)
VIN
VOUT
Load
Current
Current
(10mA/div)
VIN = 5.5V
VOUT = 3.3V
IOUT = 0mA to 10mA
COUT = 10mF
VOUT
VIN
Load Current
VIN = 5.50V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
0V
0A
Time (5ms/div)
Current (50mA/div)
Voltage
(100mV/div)
Over the operating temperature range of TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT
= 100 μA, VEN = VIN, COUT = 1 μF, and CIN = 1 μF, unless otherwise noted.
Time (1ms/div)
VIN
Figure 20. Enable Pin vs Output Voltage Response and
Output Current, TPS78233
Enable
VOUT
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Load
Current
0V
Current (50mA/div)
Voltage (1V/div)
Figure 19. Load Transient Response, TPS78233
Time (1ms/div)
Figure 21. Enable Pin vs Output Voltage Delay, TPS78233
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7 Detailed Description
7.1 Overview
The TPS782 family of low-dropout regulators (LDOs) is designed specifically for battery-powered applications
where ultralow quiescent current is a critical parameter. The TPS782 family is compatible with the TI MSP430
and other similar products. The enable pin (EN) is compatible with standard CMOS logic. This LDO family is
stable with any output capacitor greater than 1.0 µF.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
EPROM
EN
Mux
Thermal
Shutdown
Bandgap
Active
PullDown
10kW
Logic
GND
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS782 is internally current-limited to protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the
device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TPS782 series has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting to 5% of rated output current may be appropriate.
7.3.2 Active VOUT Pulldown
In the TPS782 series, the active pulldown discharges VOUT when the device is off. However, the input voltage
must be greater than 2.2 V for the active pulldown to work.
10
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Feature Description (continued)
7.3.3 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage CMOS levels. When
shutdown capability is not required, EN should be connected to the IN pin, as shown in Figure 22. The TPS782
series, with internal active output pulldown circuitry, discharges the output to within 5% VOUT with a time (t)
shown in Equation 1:
t=3
10kW ´ RL
´ COUT
10kW + RL
(1)
Where:
RL= output load resistance
COUT = output capacitance
4.2V to 5.5V
VIN
2.7V
IN
VOUT
OUT
1 mF
1mF
TPS78227
EN
GND
Figure 22. Circuit Showing EN Tied High When Shutdown Capability Is Not Required
7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
TJ
Normal
VIN > VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ILIM
TJ < TSD
Dropout
VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ILIM
TJ < TSD
Disabled
—
VEN < VEN(LO)
—
TJ > TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
• The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
• The output current is less than the current limit (IOUT < ILIM).
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
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7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature (TJ > TSD).
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS782 family of LDOs is factory-programmable to have a fixed output. Note that during startup or steadystate conditions, it is important that the EN pin voltage never exceed VIN + 0.3V.
8.2 Typical Application
VIN
IN
VOUT
OUT
1mF
1mF
TPS782xx
On
Off
EN
GND
Figure 23. Typical Application Circuit
8.2.1 Design Requirements
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND pin current, and power the load. Select input and output capacitors based on application needs.
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if
the device is not located near the power source. If source impedance is not sufficiently low, a 0.1-μF input
capacitor may be necessary to ensure stability.
The TPS782 series is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at
the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1.0 Ω. With tolerance and dc bias effects, the minimum
capacitance to ensure stability is 1 μF.
12
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Typical Application (continued)
8.2.2.2 Dropout Voltage
The TPS782 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. Refer to application
report SLVA207, Understanding LDO Dropout, available for download from www.ti.com.
8.2.2.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases duration of the transient response. For more information, see Figure 19.
8.2.2.4 Minimum Load
The TPS782 series is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at
very light output loads. The TPS782 employs an innovative, low-current circuit under very light or no-load
conditions, resulting in improved output voltage regulation performance down to zero output current. See
Figure 19 for the load transient response.
100
80
1mA
70
10
60
150mA
109mVRMS
1
PSRR (dB)
Output Spectral Noise Density (mV/ÖHz)
8.2.3 Application Curves
0.1
50mA
109mVRMS
0.01
10
100
1k
Frequency (Hz)
40
50mA
30
20
150mA
10
1mA
108mVRMS
0.001
50
0
10k
100k
Figure 24. Output Spectral Noise Density vs Frequency,
CIN = 1 μF, COUT = 2.2 μF, VIN = 3.2 V, TPS78227
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 25. Ripple Rejection vs Frequency, VIN = 4.2 V,
VOUT = 2.7 V, COUT = 2.2 μF, TPS78227
8.3 Do's and Don’ts
Do place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND of
the regulator.
Do not exceed the absolute maximum ratings.
9 Power Supply Recommendations
For best performance, connect a low-output impedance power supply directly to the IN pin of the TPS782 series.
Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin
during startup or load transient events. If inductive impedances are unavoidable, use an input capacitor.
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10 Layout
10.1 Layout Guidelines
To improve ac performance (such as PSRR, output noise, and transient response), it is recommended that the
printed circuit board (PCB) be designed with separate ground planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should
connect directly to the GND pin of the device. High ESR capacitors may degrade PSRR.
10.2 Layout Example
VIN
VOUT
1
CIN
5
COUT
2
3
4
GND PLANE
Represents via used for
application-specific connections
Figure 26. Layout Example for DDC Package
10.3 Thermal Protection
Thermal protection disables the device output when the junction temperature rises to approximately 160°C,
allowing the device to cool. Once the junction temperature cools to approximately 140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off again. This cycling limits the dissipation of the regulator, protecting it from damage
as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TPS782 series has been designed to protect against overload conditions.
However, it is not intended to replace proper heatsinking. Continuously running the TPS782 series into thermal
shutdown degrades device reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power
dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the
output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2:
PD = (VIN - VOUT) ´ IOUT
(2)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS782.
The TPS782xxEVM evaluation modules (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS782 family is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 2. Device Nomenclature (1)
PRODUCT
TPS782xxyyyz
(1)
VOUT
XX is the nominal output voltage
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Application report. Understanding LDO Dropout, SLVA207
• Product information. Low-power MCUs, MSP430
• Reference design.Water Meter Implementation with FRAM Microcontroller, TIDU517
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS78218DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJY
TPS78218DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJY
TPS78218DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
SAF
TPS78218DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
SAF
TPS78222DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RAR
TPS78222DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RAR
TPS78223DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
NXM
TPS78223DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
NXM
TPS78225DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVD
TPS78225DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVD
TPS78225DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVD
TPS78225DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVD
TPS78227DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVE
TPS78227DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVE
TPS78227DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CVE
TPS78227DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVE
TPS78228DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVF
TPS78228DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVF
TPS78228DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVF
TPS78228DRVRG4
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVF
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS78228DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CVF
TPS78230DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCK
TPS78230DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCK
TPS78230DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ODE
TPS78230DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ODE
TPS78233DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OAH
TPS78233DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OAH
TPS78236DDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SCE
TPS78236DDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SCE
TPS78236DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SCE
TPS78236DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SCE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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