TPS92074DDCR

TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 Non-Isolated, Buck PFC LED Driver with Digital Reference Control Check for Samples: TPS92074 FEATURES DESCRIPTION • • • • • • • • • • • • The TPS92074 is a hybrid power factor controller (PFC) optimized for driving LED lighting solutions that do not require phase dimming compatibility. The device monitors the converter rectified AC waveform using an internal, low-power, digital controller. The controller and DAC generate a synchronized triangular reference to regulate the output current. By allowing for some variation in the LED current over a line cycle and maintaining a regulated overall average current, high power factor solutions can be achieved. 1 Controlled Reference Derived PFC Digital 50/60 Hz Synchronization Constant LED current operation Single Winding Magnetic Configurations Low Typical Operating Current Fast Start-up Overvoltage Protection Feedback Short-Circuit Protection Wide Temperature Operation Range Low BOM Cost and Small PCB Footprint Patent Pending Digital Architecture 8-Pin SOIC and 6-Pin TSOT Available APPLICATIONS • • • Non Phase Dimmable LED Lamps Bulb Replacement Area Lighting Using a constant off-time control, the solution achieves low component count, high efficiency and inherently provides variation in the switching frequency. This variation creates an emulated spread spectrum effect easing the converters EMI signature and allowing a smaller input filter. The TPS92074 also includes standard features: current limit, overvoltage protection, thermal shutdown, and VCC undervoltage lockout, all in packages utilizing only 6 pins. SIMPLIFIED APPLICATION DIAGRAM EMI Filter LED + TPS92074 VSEN COFF GND VCC ISNS GATE LED - VIN AC 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE MIN Input voltage range Bias and ISNS MAX VCC –0.3 22 VSEN, COFF –0.3 6.0 IQ bias current (non-switching) Gate 2.5 mA –0.3 2.5 V GATE - continuous –0.3 18 V –2.5 20.5 V GATE - 100 ns Internally Limited Electrostatic discharge Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Operating junction temperature, TJ (3) Storage temperature range, Tstg –65 Lead temperature, soldering, 10s (2) (3) V ISNS (2) to Ground Continuous power dissipation (1) UNIT 2 kV 750 V 160 °C 150 °C 260 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ISNS can sustain –2 V for 100 ns without damage. Maximum junction temperature is internally limited. THERMAL INFORMATION TPS92074 SOIC (D) TSOT (DDC) 8 PINS 6 PINS THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance (2) 112.3 165.5 θJCtop Junction-to-case (top) thermal resistance (3) 58.4 28.8 θJB Junction-to-board thermal resistance (4) 52.5 24.6 12.5 0.3 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 51.9 23.8 θJCbot Junction-to-case (bottom) thermal resistance (7) NA NA (1) (2) (3) (4) (5) (6) (7) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 RECOMMENDED OPERATING CONDITIONS (1) Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C. MIN Supply input voltage range VCC MAX 11 Operating junction temperature (1) TYP –40 UNIT 18 V 125 °C Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics table. ELECTRICAL CHARACTERISTICS Unless otherwise specified –40°C ≤ TJ = TA ≤ 125°C, VCC = 14 V, CVCC = 10 µF CGATE = 2.2 nF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE INPUT (VCC) IQ VVCC quiescent current Not switching 1.3 2.5 mA IQ_SD VVCC low power mode current VCC < VCC(UVLO) 120 250 µA VVCC Input range VCC ≤ VCC(OVP) 18 V VVCC(OVP) Overvoltage protection threshold VCC > VCC(OVP) 20.0 V VVCC(UVLO) VVCC UVLO threshold 10.5 V VVCC(HYS) VVCC UVLO hysteresis 18.0 VCC rising VCC falling 9.8 5.75 6.40 V 3.3 V LINE SYNCHRONIZATION VSENTH-Hi VSEN line detect rising threshold 0.9 1.0 1.1 V VSENTH-Low VSEN line detect falling threshold 0.465 0.500 0.540 V 1.14 OFF-TIME CONTROL VCOFF OFF capacitor threshold 1.20 1.285 V RCOFF OFF capacitor pull-down resistance 33 60 Ω tOFF(max) Maximum off-time 280 μs GATE DRIVER OUTPUT (GATE) RGATE(H) Gate sourcing resistance 3 8 Ω RGATE(L) Gate sinking resistance 3 8 Ω 500 555 mV CURRENT SENSE VISNS Average ISNS limit threshold VCL Current limit 1.2 V Leading edge blanking 240 ns Current limit reset delay 280 µs ISNS limit to GATE delay 33 ns OFF capacitor limit to GATE delay 33 ns tISNS tCOFF_DLY DAC: 63/127 445 THERMAL SHUTDOWN TSD Thermal limit threshold 160 °C THYS Thermal limit hysteresis 20 °C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 3 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM VCC VVCC Regulator VSEN Filter Internal Regulator VVCC OVP VVCC UVLO Logic Standby Thermal Shutdown Standby 0 -V to 1-V (Analog) PWM + ISNS ILIM + 200-ns Delay 1.2 V COFF GATE Control Logic + 1.2 V 200-PS Off-timer GND TPS92074 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 SOIC (D) PACKAGE 8 PINS (TOP VIEW) GND 1 8 VSEN COFF 2 7 NC VCC 3 6 NC GATE 4 5 ISNS TSOT (DDC) PACKAGE 6 PINS (TOP VIEW) VSEN 1 6 COFF GND 2 5 VCC ISNS 3 4 GATE PIN DESCRIPTIONS PIN NUMBERS NAME SIOC (D) TSOT (DDC) I/O DESCRIPTION COFF 2 6 I Used to set the converter constant off-time. A current and capacitor connected from the output to this pin sets the constant off-time of the switching controller. GATE 4 4 O Power MOSFET driver pin. This output provides the gate drive for the power switching MOSFET. GND 1 2 — Circuit ground connection ISNS 5 3 I VCC 3 5 — VSEN 8 1 I LED current sense pin. Connect a resistor from main switching MOSFET source to GND to set the maximum switching cycle LED current. Connect ISNS to the switching FET source. Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. VCC undervoltage lockout has been implemented with a wide range: 10V rising, 6V falling to ensure operation with start-up methods that allow elimination of the linear pass device. This includes using a coupled inductor with resistive start-up. The line voltage and frequency are detected through this pin and fed to the digital decoder. Sensing thresholds are 1V rising and 0.5V falling – nominal. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 5 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS 1.1630 1400 1.1625 1200 VCC Input Current (µA) COFF Voltage Threshold (V) Unless otherwise stated, –40°C ≤ TA = TJ ≤ 125°C, VVCC = 14 V, CVCC = 10 µF CGATE = 2.2 nF 1.1620 1.1615 1.1610 1.1605 1.1600 −40 −25 −10 800 600 400 200 5 20 35 50 65 Temperature (°C) 80 95 0 110 125 0 2 4 6 8 10 12 14 VCC Input Voltage (V) 16 18 20 G000 Figure 2. VCC Input Current vs Vcc Input Voltage 6.48 9.82 6.46 UVLO Threshold (V) 9.84 9.80 9.78 9.76 9.74 6.44 6.42 6.40 6.38 9.72 9.70 −40 −25 −10 VCC Rising VCC Falling G000 Figure 1. COFF Threshold Voltage vs Temperature UVLO Threshold (V) 1000 5 20 35 50 65 Temperature (°C) 80 95 110 125 6.36 −40 −25 −10 5 G000 Figure 3. Input Voltage (UVLO Rising) vs Junction Temperature 20 35 50 65 Temperature (°C) 80 95 110 125 G000 Figure 4. Input Voltage (UVLO Falling) vs Junction Temperature 50 45 Number of Devices 40 35 30 25 20 15 10 5 0. 47 0 0 .5 20 0 ISNS Mid-Scale Voltage Range (V) Figure 5. ISNS 0.5V Threshold Distribution 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 APPLICATION INFORMATION The TPS92074 is an AC-DC power factor correction (PFC) controller for LED lighting applications. A hysteretic, peak current, constant off-time approach implements the conversion. Rectified AC A A Vcc C3 C3 TPS92074 VSEN COFF GND VCC ISNS GATE D2 C8 D2 B Buck B Buck-Boost Q2 R7 Figure 6. Simplified TPS92074 Schematic The TPS92074 controls the inductor current by controlling two features: (A) The peak inductor current, and (B) The cycle off-time. The following items summarize the basics of the switch operation in this hysteretic controller. • The main switch Q2 turns on and current ramps in the inductor. • The Q2 current flows through the sense resistor R7. The R7 voltage is compared to a reference voltage at ISNS. The Q2 on-time ends when the voltage on R7 is equal to a controlled reference voltage and the inductor current has reached its set peak current level for that switching cycle. • Q2 is turned off and a constant off-time timer begins. Voltage begins ramping on C8. • The next cycle begins when the voltage on C8 reaches 1.2 V. This ends the constant off-time and discharges C8. • Capacitor C3 eliminates most of the ripple current seen in the LEDs. iL (A) Peak Inductor Current 'iL-PP (B) tOFF tON (constant) Ts 0 Time UDG-12176 Figure 7. Current Regulation Method The TPS92074 incorporates a patent-pending control methodology to generate the reference for the conversion stage. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 7 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com Initial Start-Up The TPS92074 is designed to achieve instant turn-on using an external linear regulator circuit. The start-up sequence is internally controlled by a VCC under-voltage lockout (UVLO) circuit. Sufficient headroom has been incorporated to support the use of an auxiliary winding with start-up linear, resistive or coupled capacitor start-up methods. VCC Bias Supply The TPS92074 can be configured to use a linear regulator with or without the use of an auxiliary winding. Using a linear regulator to provide VCC incurs more losses than an auxiliary winding, but has several advantages: • allows the use of inexpensive off-the-shelf inductors as the main magnetic • can reduce the size of the required VCC capacitor to as low as 0.1uF Another consideration when selecting a bias method involves the OVP configuration. Because the feature is enabled via the VCC pin, an auxiliary winding provides the simplest implementation of output over-voltage protection. A typical start-up sequence begins with VVCC input voltage below the UVLO threshold and the device operating in low-power, shut-down mode. The VVCC input voltage increases to the UVLO threshold of 9.8V typical. At this point all of the device features are enabled. The device loads the initial start-up value as the output reference and switching begins. The device operates until the VVCC level falls below the VCC(UVLO) falling threshold. (6.4V typical) When VVCC is below this threshold, the device enters low-power shut-down mode. Voltage Sense Operation The VSEN (voltage sense) pin is the only input to the digital controller. The time between the rising edge and the falling edge of the signal determines converter functions. The pin incorporates internal analog and digital filtering so that any transition that remains beyond the threshold for more than approximately 150 µs will cause the device to record a change-of-state. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 Controller Basic Operation The controller continuously monitors the line cycle period. Control algorithms use a normalized line period of 256 samples from VSEN fall to VSEN fall and a normalized converter reference control of 127 levels over a range of 0V to 1V . The two main controller states are: • Start-Up • Normal Operation After the initial start-up period where the reference is a DC level, the reference is changed to a triangular ramp to achieve a high power factor. The ramp generates gradually over several cycles ensuring the change is undetectable. The controller maintains the ramp between the rising and falling VSEN signals. Table 1. Control States and Controlled Reference Values MODE LINE DUTY CYCLE CONTROLLED REFERENCE VALUE (value / 127 ) X 1 V = reference Any 50 Start-up Normal Operation Typical Average 55 Typical Ramp Range 22 to 127 Any 42 No VSEN Initial Start-up Line Synchronization When the device reaches the turn-on UVLO threshold, the output current reference resets to 0.393 V (50/127) and switching begins. The controller samples the line for approximately 80 ms (t1 to t2 , Figure 8) to determine the line frequency and establish the present state of operation. After determining the line frequency, the controller uses the information to calibrate the internal oscillator. The controller supports line frequencies from 45 Hz to 65 Hz. After determining frequency and duty cycle, the controller enters normal operation. VREC VVSEN Controlled Reference VISNS(peak) VGATE xxxxxxxxxxx Time t0 t1 t2 UDG-12168 Figure 8. Line Synchronization Triangular Ramp Creation After the start-up period, the controller creates a triangular ramp that is synchronized to the line and is centered between rising and falling edges of the VSEN signal as shown in Figure 9. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 9 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com Rectified AC VSEN Controlled Reference Time Figure 9. Controlled Reference Output At start-up the ramp is created over 127 line cycles (see Figure 10) or approximately 1 second (t2 to t3 ≈ 1 second). Because the output level before and after the change is very similar and the change very gradual, it is impossible for the user to perceive a change in output level. The ramp converts from a DC level to a ramp using a method that further ensures transparency to the user. VREC ... VVSEN ... VISNS(peak) ... t2 Time t3 Figure 10. Transition Stages of the Controlled Reference during Start-Up Loss of Voltage Sense If a circuit malfunction or failure occurs causing the VSEN singal to become too narrow or to be lost completely, the controller simply sets the reference to a default value 0.33 V (42/127) and waits for the VSEN signal to return. Not Using Voltage Sense A simplified version of the TPS92074 circuit can be implemented by grounding the VSEN signal if minimum component count and size are essential design criteria. In this configuration, the triangular ramp reference is not implemented. The output is controlled with a default, static reference of 0.394 V (50/127). If used in conjunction with an on-time clamp and the appropriate LED stack voltage, power factors (> 0.9) can still be achieved, but THD is higher without the ramp waveform. Thermal Shutdown The TPS92074 includes thermal shutdown protection. If the die temperature reaches approximately 160°C the device stops switching (GATE pin low). When the die temperature cools to approximately 140°C, the device resumes normal operation. If thermal foldback is desired at levels below the device thermal shut down limit, application circuit design features implement this protection. The most simple of these design features is the addition of a thermistor in the off-time circuitry. Thermal Foldback To implement thermal foldback, adjust the resistance of an existing circuit resistor with the use of an NTC (negative temperature coefficient) thermistor. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 For example, a resistor combination creating a dominant effect when the thermistor reaches the desired temperature and resistance can be incorporated by paralleling a thermistor and another resistor like R10 with the suggested On-Time clamp (see Figure 12. ). This circuit option creates a shorter on-time as the temperature increases, reducing the output current. The use of a thermistor (NTC or PTC) in these types of circuit implementations is simple and saves costly added circuitry and additional device pins. Overvoltage Protection (OVP) The implementation of overvoltage protection is simple and built-in if using a two-coil magnetic (coupled inductor) to derive VCC. If the LED string is opened the auxiliary VCC rises and reaches the VCC(OVP) trip point. This action disables and grounds the gate pin, preventing the converter from switching. The converter remains disabled until VCC drops 0.5 V after a 1 second time-out. If an inductor is used, implement other discrete circuits to disable the converter. Output Bulk Capacitor The required output bulk capacitor, CBULK, stores energy during the input voltage zero crossing interval and limits twice the line frequency ripple component flowing through the LEDs. Equation 1 describes the calculation of the of output capacitor value. PIN CBULK ³ 4p ´ fL ´ RLED ´ VLED ´ ILED(ripple ) where • • • RLED is the dynamic resistance of LED string ILED(ripple) is the peak to peak LED ripple current and fL is line frequency (1) Compute RLED as the difference in LED forward voltage divided by the difference in LED current for a given LED using the manufacturer’s VF vs. IF curve. For an initial estimate, a typical value of 0.25 Ω per LED can be used. More detail can be found in the Application Report Design Challenges of Switching LED Drivers (AN-1656). In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve the desired operating lifetime. It should also be a consideration to provide a minimum load at the output of the driver to discharge the capacitor after the power is switched off or during LED open circuit failures. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 11 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com Design Guidelines This TPS92074 application design requires the selection of components for the power conversion stage and line sensing. Output inductor, sense resistor and switching frequency are the key aspects of the power stage design. Another important consideration is the inclusion of an on-time clamp. The combination of the line voltage going to zero at each cycle and the hysteretic control method can lead to large increases in current draw at the start and end of each cycle. The components required for the on-time clamp are very inexpensive and they return results that make their inclusion a common choice for LED driver designers. This simplified design procedure assumes the use of an on-time clamp in the design. UDG-12183 iL(ave) Peak Inductor Current follows this Controlled Reference. Ipk(t) = VISNS(t)/RSENSE RSENSE adjusts the average, peak inductor current The Inductance (L) defines 'iL(P-P) ûiL-PP = (VLED * toff ) L Rectified AC Inductor Current Ripple The average output current = the average peak ± ½ the peak to peak inductor ripple iL(ave)= iLave(pk) ± ûiL(P-P) 2 iLave(pk) = VISNS(ave) RSENSE Time tON Time tOFF Figure 11. TPS92074 Output Current Control The device uses the controller reference during every switching cycle. This controller reference sets the peak current through the main switch and sense resistor. The average value of this reference and the inductor ripple current can be used to calculate the average output current. Also consider the length of time the converter provides power to the LEDs based on the LED stack voltage. A conversion factor (CF) that accounts for a lower level of power conversion at the ends of each cycle is used to provide a more accurate sense resistor value. The lower level of power conversion in these areas also helps to increase the power factor. For the RSENSE calculation use VISNS (ave) = 0.433 V (55/127). The CF calculation involves computing the normalized time length of the voltage sense pulse using a formula shown in Equation 3. See the simplified design expressions in Equation 2 through Equation 6. For a more comprehensive approach refer to the TPS92074 Design Spreadsheet. To calculate RSENSE, use Equation 2. æ ö ç V ÷ ISNS ave ( ) ÷ RSENSE = ç ´ CF ç DiL(P-P ) ÷ ç ILED + ÷ 2 è ø (2) To calculate the conversion factor, use Equation 3. æ æ VLED ç sin-1 ç ç 2´V ç RMS è CF = 1 - ç 90 ç ç è ö ö ÷ ÷ ÷ 3÷ ø´ ÷ 2÷ ÷ ø (3) To calculate inductance ripple, use Equation 4. ´t æV ö DiL(P-P ) = ç LED OFF ÷ L è ø (4) To calculate the constant off-time, use Equation 5 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 æ æ æ 1.2 ööö tOFF = ç ln ç - ç - 1÷ ÷ ÷ ´ (-CTOFF ´ RCOFF ) ÷ ç ç è VVCC ø ø ÷ø è è (5) To calculate the average switching frequency, use Equation 6. æ ö 1 fSW = ç ÷ ç tOFF + (tOFF ´ CF ) ÷ è ø (6) General Approach to Buck and Buck-Boost PFC Design To maintain a high power factor and low THD, create an input current waveform equivalent to what would be seen in a purely resistive load. A resistive load (like an incandescent light bulb) can draw power until the line zero cross. A buck converter driving an LED load can provide power only while the input line is greater than the LED stack voltage. This situation creates a limitation in the selection of LED stack voltage. Currently in non-LED load, buck PFC applications, a commonly accepted output voltage that maintains acceptable THD and PFC levels is one that maintains a 50% conduction angle each line cycle. See the TI Application Report Power Factor Correction Using the Buck Topology(SLUP264) In practical terms this equates to 90 VDC for a 90 VAC minimum input. For LED driver solutions this rule can be followed if the goal is simply a power factor ≥0.9. If the goal is also THD less than 20% then stricter requirements must be followed. In general, designs with an LED stack voltage beyond 45 V have difficulty achieving < 20% THD. For these solutions, a buck-boost topology should be used so that the circuit has the capability to draw current from the line below the LED stack voltage. On-Time Clamp The use of an on-time clamp ( see Figure 12) provides soft-start and soft-stop functionality to the conversion during each line cycle. The clamp also allows an opportunity to control the energy in these conversion areas to optimize THD. For example, reducing the energy conversion in these areas helps to create an input current that is more sinusoidal in shape. Without it, the current can rise quickly at the start and end of each cycle as the converter goes in and out of drop-out. Solutions having a power factor ≥0.9 are still achievable, but the design must use the on-time clamp to obtain very low THD. TPS92074 ISNS R11 GATE R10 D5a D5b ISNS ISNS C10 R8 Figure 12. On-time Clamp Circuitry The circuit uses the gate drive output to generate a ramp. The ramp increases at a rate to reach the current sense trip point at the desired maximum conduction time. The gate signal, resistor R10 and capacitor C10 create the ramp. Diode D5b resets the ramp for each switching cycle. Resistor R11 provides an impedance so this signal can override ISNS. In the regions at the start and end of a line cycle the current sense reference is controlled to 0.173 V (22/127). To select an R-C to reach this point in the desired time use Equation 7. A good starting estimate for the maximum on-time clamp is approximately one-half of tOFF . For example, choosing 33 nF as the value of capacitor C10, and assuming VGATE ≈ VCC, R10 (Rton(max)) is calculated in Equation 7. tOFF R ton(max ) = é æ æ 0.173 ö öù - 1÷ ÷ ú ´ -Cton(max ) 2 ´ êln ç - ç ç V ÷ ø ø ûú ëê è è GATE (7) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 13 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com Voltage Sense Circuitry and Minimum VSEN Signal Length If the design topology is a buck converter, select the divider so the falling 0.5-V VSEN threshold is reached when the rectified AC voltage is at the LED stack voltage. For example, if the LED stack is 20 V and the top resistor is 400 kΩ, the bottom resistor should be 10.25 kΩ to provide a falling VSEN signal at 0.5 V when the rectified AC reaches 20 V. A 20-V VSEN falling signal corresponds to a 40-V VSEN rising threshold because of the 2:1 hysteresis. These thresholds provide a VSEN signal length of approximately 7.4 ms. This length is adequate to activate the ramp mode. Regardless of the VSEN connection method used, the divider must ensure an adequate voltage sense time (tVSEN > 5.9 ms) to activate the creation of the triangular reference. For example, if a straight resistor divider ( as shown in Figure 13) is implemented and the design LED stack is more than 42 V, the VSEN conduction time may not be adequate to ensure use of the ramp reference by the controller. LED(-) LED(+) LED(+) VSEN VSEN VSEN Figure 13. Voltage Sense for Low Voltage Buck Applications Figure 14. Voltage Sense for Buck Applications up to 65V Figure 15. Voltage Sense for Buck-Boost Applications For LED stack voltages between 3 V and 65 V, use an alternate method that senses from LED(–). Because LED(–) reaches ground each line cycle, the absolute VSEN comparison limits of 0.5 V and 1 V can be used, providing extra conduction time for the VSEN signal as shown in Figure 14. When using an LED stack, with an approximate voltage of more than 65-V, use an alternate VSEN methods such as a bridge tap. For buck-boost applications, implement the circuit shown in Figure 15. A capacitor on the VSEN pin may be required, depending on operating conditions. EMI Filtering: AC versus DC side of the rectifier bridge The TPS92074 requires a minimal amount of EMI filtering to pass conducted and radiated emissions levels to comply with agency requirements. Applications have been tested with the filter on the AC or DC side of the diode bridge and have obtained passing results. The use of an R-C snubber to damp filter resonances is strongly recommended. The EMI filter design involves optimizing several factors and design considerations, including: • the use of ‘X’ versus non-X rated filter capacitors • the use of ceramic versus film capacitors • component rating requirements when on the AC or DC side of the diode bridge • snubber time constant and position in the design schematic • filter design choices and audible noise 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 Application Circuits + TPS92074 VSEN COFF GND VCC ISNS GATE Figure 16. TPS92074 Buck Topology with AC Side Filter + TPS92074 VSEN COFF GND VCC ISNS GATE ISNS ISNS Figure 17. TPS92074 Buck-Boost Topology with DC Side Filter Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 15 TPS92074 SLUSBO7 – AUGUST 2013 www.ti.com + TPS92074 VSEN COFF GND VCC ISNS GATE ISNS ISNS UDG-12184 Figure 18. TPS92074 Buck-Boost Topology with Resistive Start-up and AUX Supply + TPS92074 VSEN COFF GND VCC ISNS GATE Rt 0-3V Analog DIM Signal Figure 19. TPS92074 Buck Topology with Thermal Foldback and Analog Dimming (0 to 100%) 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92074 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS92074D ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92074 TPS92074DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DR ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92074 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of