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TPS7A26
SBVS290B – DECEMBER 2018 – REVISED OCTOBER 2019
TPS7A26 500-mA, 18-V, Ultra-Low IQ, Low-Dropout Linear Voltage Regulator
With Power-Good
1 Features
3 Description
•
•
•
The TPS7A26 low-dropout (LDO) linear voltage
regulator supports a 2.4-V to 18-V input voltage
range with very-low quiescent current (IQ). These
features help modern appliances meet increasingly
stringent energy requirements and help extend
battery life in portable-power solutions.
1
•
•
•
•
•
•
•
•
Ultra-low IQ: 2.0 µA
Input voltage: 2.4 V to 18 V
Output voltage options available:
– Fixed: 1.25 V to 5.5 V
– Adjustable: 1.24 V to 17.4 V
1% accuracy over temperature
Low dropout: 590 mV (max) at 500 mA
Open-drain, power-good output
Active overshoot pulldown protection
Thermal shutdown and overcurrent protection
Operating junction temperature: –40°C to +125°C
Stable with 1-µF output capacitors
Package: 6-pin WSON
The TPS7A26 is available in both fixed and
adjustable versions. For more flexibility or higher
output voltages, the adjustable version uses feedback
resistors to set the output voltage from 1.24 V to
17.4 V. Both versions have 1% output regulation
accuracy that provides precision regulation for
microcontroller (MCU) references.
With the open-drain, power-good (PG) output the
device can provide a reset to an MCU or be wireORed and level-shifted with other open-drain PGs to
provide a system-wide PG or reset.
2 Applications
•
•
•
•
•
•
•
The TPS7A26 LDO operates more efficiently than
standard linear regulators because the maximum
dropout voltage is less than 590 mV at 500 mA of
current. This maximum dropout voltage allows for
87.7% efficiency from a 5.7-V input voltage (VIN) to
5.0-V output voltage (VOUT).
Home and building automation
Multicell power banks
Smart grid and metering
Portable power tools
Motor drives
White goods
Portable appliances
For lower power applications, consider the TPS7A25.
Device Information(1)
PART NUMBER
TPS7A26
PACKAGE
WSON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Typical Application Circuit
VPG
PG
VIN
VOUT
OUT
IN
TPS7A26
CIN
RPG
R1
COUT
EN
FB
GND
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A26
SBVS290B – DECEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision A (March 2019) to Revision B
Page
•
Added fixed-voltage version to document ............................................................................................................................. 1
•
Changed adjustable version output voltage from 0.24 V to 17.45 V to 1.24 V to 17.4 V....................................................... 1
•
Deleted fixed-voltage version description from Description section ...................................................................................... 1
•
Added reference to TPS7A25 in Description section ............................................................................................................. 1
•
Added Active to Overshoot Pulldown Circuitry title ............................................................................................................. 15
Changes from Original (December 2019) to Revision A
•
2
Page
Changed status from Advance Information to Production Data ............................................................................................ 1
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SBVS290B – DECEMBER 2018 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
TPS7A26: DRV Package (Adjustable)
6-Pin WSON
Top View
OUT
1
FB
2
PG
3
6
IN
5
4
TPS7A26: DRV Package (Fixed)
6-Pin WSON
Top View
OUT
1
GND
NC
2
EN
PG
3
Thermal
6
IN
5
GND
4
EN
Thermal
Pad
Pad
Not to scale
Not to scale
Pin Functions
PIN
DRV
(Adjustable)
DRV
(Fixed)
I/O
DESCRIPTION
EN
4
4
Input
Enable pin. Drive EN greater than VEN(HI) to enable the regulator. Drive EN
less than VEN(LOW) to put the regulator into low-current shutdown. Do not float
this pin. If not used, connect EN to IN.
FB
2
—
Input
Feedback pin. Input to the control-loop error amplifier. This pin is used to set
the output voltage of the device with the use of external resistors. For
adjustable-voltage version devices only.
GND
5
5
—
IN
6
6
Input
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger capacitor from IN to ground as listed in the
Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
NC
—
2
—
No internal connection. For fixed-voltage version devices only. Ths pin can
be floated but the device has better thermal performance with this pin tied to
GND.
Output
Output pin. A capacitor is required from OUT to ground for stability. For best
transient response, use the nominal recommended value or larger capacitor
from OUT to ground. Follow the recommended capacitor value as listed in
the Recommended Operating Conditions table. Place the output capacitor as
close to the OUT and GND pins of the device as possible.
Power-good pin; open-collector output. Pullup this pin externally to the OUT
pin or another voltage rail. The PG pin goes high when VOUT > VIT(PG,RISING),
as discussed in the Electrical Characteristics table. The PG pin is driven low
when VOUT < VIT(PG,FALLING), as discussed in the Electrical Characteristics
table. Ths pin can be floated but the device has better thermal performance
with this pin tied to GND.
NAME
OUT
PG
Thermal pad
1
1
3
3
Output
Pad
Pad
—
Ground pin.
Exposed pad of the package. Connect this pad to ground or leave floating.
Connect the thermal pad to a large-area ground plane for best thermal
performance.
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SBVS290B – DECEMBER 2018 – REVISED OCTOBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
(2)
MIN
MAX
VIN
–0.3
20
VOUT (3)
–0.3
VIN + 0.3
VFB
–0.3
5.5
VEN
–0.3
20
–0.3
20
VPG
Current
Maximum output
Temperature
(1)
(2)
(3)
Internally limited
UNIT
V
A
Operating junction, TJ
–50
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages with respect to GND.
VIN + 0.3 V or 20 V (whichever is smaller).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VIN
Input voltage
VOUT
NOM
MAX
UNIT
2.4
18
V
Output voltage (adjustable version)
1.24
18-VDO
V
VOUT
Output voltage (fixed version)
1.25
5.5
V
IOUT
Output current
0
500
mA
VEN
Enable voltage
0
18
V
VPG (1)
Power-good voltage
0
18
CIN (2)
Input capacitor
COUT (2)
Output capacitor
TJ
Operating junction temperature
(1)
(2)
1
1
2.2
–40
V
μF
100
μF
125
°C
Select pullup resistor to limit PG pin sink current when PG output is driven low. See Power Good section for details.
All capacitor values are assumed to derate to 50% of the nominal capacitor value.
6.4 Thermal Information
TPS7A26
THERMAL METRIC
(1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
73.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
90.6
°C/W
RθJB
Junction-to-board thermal resistance
38.3
°C/W
ΨJT
Junction-to-top characterization parameter
3.7
°C/W
ΨJB
Junction-to-board characterization parameter
38.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
14.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS290B – DECEMBER 2018 – REVISED OCTOBER 2019
6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.8 V or VIN = 2.4 V (whichever is greater), FB tied to OUT, IOUT = 1 mA,
VEN = 2 V, and CIN = 1 μF, COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
MIN
TYP
MAX
UNIT
VIN rising
1.95
2.15
2.35
V
UVLO threshold falling
VIN falling
1.85
2.09
VFB
Feedback voltage
Adjustable version only
VOUT
Output voltage accuracy
Adjustable version, VOUT = VFB
VOUT
Output voltage
accuracyaccuracy for fixed
output options
Fixed output versions
ΔVOUT(ΔVIN)
Line regulation (1)
ΔVOUT(ΔIOUT)
Load regulation
VUVLO(RISING)
UVLO threshold rising
VUVLO(HYS)
UVLO hysteresis
VUVLO(FALLING)
VDO
Dropout voltage (2)
ICL
Output current limit
TEST CONDITIONS
70
mV
2.25
V
1.24
1.228
1.24
V
1.252
V
–1
1
%
(VOUT(nom) + 0.8 V or 2.4 V) ≤ VIN ≤ 18 V
–0.1
0.1
%
1 mA ≤ IOUT ≤ 500 mA
–0.5
0.5
%
IOUT = 100 mA
92
145
IOUT = 250 mA
173
280
355
590
717
970
IOUT = 0 mA
2
4.5
IOUT = 1 mA
15
IOUT = 500 mA
VOUT = 0.9 × VOUT(nom)
525
mV
mA
IGND
Ground pin current
ISHUTDOWN
Shutdown current
IFB
FB pin current
IEN
EN pin current
VEN = 18 V
VEN(HI)
Enable pin high-level input
voltage
Device enabled
VEN(LOW)
Enable pin low-level input
voltage
Device disabled
VIT(PG,RISING)
PG pin threshold rising
RPULLUP = 10 kΩ, VOUT rising,
VIN ≥ VUVLO(RISING)
93
VHYS(PG)
PG pin hysteresis
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
3
%VOUT
VIT(PG,FALLING)
PG pin threshold falling
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
90
%VOUT
VOL(PG)
PG pin low level output
voltage
VOUT < VIT(PG,FALLING), IPG-SINK = 500 µA
ILKG(PG)
PG pin leakage current
VOUT > VIT(PG,RISING), VPG = 18 V
VEN ≤ 0.4 V, VIN = 2.4 V, Iout = 0 mA
f = 10 Hz
PSRR
Power-supply rejection ratio f = 100 Hz
f = 1 kHz
325
µA
600
nA
10
nA
10
nA
0.9
84
V
5
0.4
V
96.5
%VOUT
0.4
V
300
nA
75
62
dB
52
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VOUT = 1.2 V
300
μVRMS
TSD(shutdown)
Thermal shutdown
temperature
Shutdown, temperature increasing
165
°C
TSD(reset)
Thermal shutdown reset
temperature
Reset, temperature decreasing
145
°C
(1)
(2)
Vout(nom) + 0.8 V or 2.4 V (whichever is greater).
VDO is measured with VIN = 0.97 × VOUT(nom) for fixed output voltage versions. VDO is not measured for fixed output voltage versions
when VOUT ≤ 2.5 V. For the adjustable output device, VDO is measured with VFB = 0.97 × VFB(nom).
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.6
1
Tj
-50qC
-40qC
0qC
25qC
0.6
0.4
85qC
125qC
150qC
Change in Output Voltage (%)
Output Voltage Accuracy (%)
0.8
0.2
0
-0.2
-0.4
-0.6
Tj
-50qC
-40qC
0qC
25qC
0.4
0.2
85qC
125qC
150qC
0
-0.2
-0.4
-0.8
-1
-0.6
2
4
6
8
10
12
Input Voltage (V)
14
16
18
0
0.05
0.1
0.15
D002
IOUT = 1 mA
0.4
0.45
0.5
D008
VOUT = 1.24 V
Figure 1. Line Regulation vs VIN
Figure 2. Load Regulation vs IOUT
250
400
Tj
-50qC
-40qC
0qC
25qC
85qC
125qC
150qC
Tj
-50qC
-40qC
0qC
25qC
350
Dropout Voltage (mV)
200
Dropout Voltage (mV)
0.2 0.25 0.3 0.35
Output Current (A)
150
100
300
85qC
125qC
150qC
250
200
150
50
100
0
50
2
4
6
8
10
12
Input Voltage (V)
14
16
18
2
4
6
D017
IOUT = 100 mA
Figure 3. Dropout Voltage vs VIN
16
18
D016
Figure 4. Dropout Voltage vs VIN
600
Tj
-50qC
-40qC
0qC
25qC
85qC
125qC
150qC
Tj
-50qC
-40qC
0qC
25qC
500
Dropout Voltage (mV)
700
Dropout Voltage (mV)
14
IOUT = 250 mA
800
600
500
400
300
400
85qC
125qC
150qC
300
200
100
200
100
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
0
D015
IOUT = 500 mA
0.1
0.2
0.3
Output Current (A)
0.4
0.5
D013
VIN = 2.4 V
Figure 5. Dropout Voltage vs VIN
6
8
10
12
Input Voltage (V)
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Figure 6. Dropout Voltage vs IOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
600
1
Tj
-50qC
-40qC
85qC
125qC
Tj
150qC
-50qC
-40qC
0qC
25qC
85qC
125qC
150qC
0.9
400
Current Limit (A)
Droput Voltage (mV)
500
0qC
25qC
300
200
0.8
0.7
100
0
0
0.1
0.2
0.3
Output Current (A)
0.4
0.6
0.5
2
4
6
8
10
12
Input Voltage (V)
14
16
18
D012
VIN = 18 V
Figure 7. Dropout Voltage vs IOUT
Figure 8. Current Limit vs VIN
30
10
Ground Current (PA)
25
20
85qC
125qC
150qC
Tj
-50qC
-40qC
0qC
25qC
8
Quiescent Current (PA)
Tj
-50qC
-40qC
0qC
25qC
15
10
85qC
125qC
150qC
6
4
2
5
0
0
2
4
6
8
10
12
Input Voltage (V)
14
16
2
18
4
6
14
16
18
D005
VOUT = 1.24 V, IOUT = 0 A
VOUT = 1.24 V, IOUT = 1 mA
Figure 10. IQ vs VIN
Figure 9. IGND vs VIN
240
50
Tj
-50qC
-40qC
0qC
25qC
85qC
125qC
150qC
40
35
30
25
Tj
220
-50qC
-40qC
200
Ground Current (PA)
45
Quiescent Current (PA)
8
10
12
Input Voltage (V)
20
15
0qC
25qC
85qC
125qC
150qC
180
160
140
120
100
80
60
10
40
5
20
0
0
0
0.5
1
1.5
2
2.5
Input Voltage (V)
3
3.5
4
0
0.05
D006
VOUT = 1.24 V, IOUT = 0 A
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
0.4
0.45
0.5
VOUT = 1.24 V
Figure 12. IGND vs IOUT
Figure 11. IQ vs VIN
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.8
3
Tj
-50qC
-40qC
0qC
25qC
2
VEN(LOW)
VEN(HIGH)
85qC
125qC
150qC
Enable Threshold (V)
Shutdown Current (PA)
2.5
1.5
1
0.5
0.7
0.6
0.5
0
-0.5
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
0.4
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
VOUT = 1.24 V, 2.4 V ≤ V IN ≤ 18 V
VOUT = 1.24 V
Figure 13. Shutdown Current vs VIN
Figure 14. VEN vs Temperature
100
2.3
VUVLO- (VIN Falling)
VUVLO+ (VIN Rising)
VIT(PG,FALLING)
VIT(PG,RISING)
98
96
PG Threshold (%Vout)
Input Voltage (V)
2.2
2.1
2
94
92
90
88
86
84
82
1.9
-50
-25
0
25
50
75
Temperature (qC)
100
125
80
-50
150
-25
0
VOUT = 1.24 V, IOUT = 1 mA
Figure 15. UVLO Thresholds vs Temperature
125
150
Figure 16. PG Thresholds vs Temperature
100
Power Supply Rejection Ratio (dB)
150
PG Leakage (nA)
100
VOUT = 1.24 V
200
100
50
ILKG(PG)
0
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
90
80
70
60
50
40
30
20
10
0
10
VOUT = 1.24 V
IOUT
10 mA
100 mA
200 mA
300 mA
500 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 1.24 V, CIN = 0 μF, COUT = 1 μF
Figure 17. PG Leakage Current vs Temperature
8
25
50
75
Temperature (qC)
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Figure 18. PSRR vs Frequency and IOUT
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Typical Characteristics (continued)
100
100
90
90
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
80
70
60
50
40
30
20
10
0
10
IOUT
10 mA
100 mA
200 mA
300 mA
500 mA
100
1k
10k
100k
Frequency (Hz)
1M
80
70
60
50
40
30
20
10
0
10
10M
VOUT = 3.3 V, VIN = 4.3 V,
CIN = 0 μF, COUT = 1 μF, CFF = 10 nF
Figure 19. PSRR vs Frequency and IOUT
COUT
1 uF
10 uF
47 uF
80
70
60
50
40
30
20
10
100
1k
10k
100k
Frequency (Hz)
1M
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
10k
100k
Frequency (Hz)
1M
10M
Figure 20. PSRR vs Frequency and VIN
80
70
60
50
40
30
20
10
0
10
10M
CFF
1 nF
10 nF
100 nF
90
VOUT = 3.3 V, VIN = 4.3 V, IOUT = 0.5 A,
CIN = 0 μF, CFF = 10 nF
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 3.3 V, VIN = 4.3 V, IOUT = 0.5 A,
CIN = 0 μF, COUT = 1 μF
Figure 21. PSRR vs Frequency and COUT
Figure 22. PSRR vs Frequency and CFF
20
100
VOUT
1.24 V
3.3 V
5V
90
80
70
60
50
40
30
20
10
10
Output Voltage Noise (PV —Hz)
Power Supply Rejection Ratio (dB)
1k
100
90
0
10
100
VOUT = 3.3 V, IOUT = 0.5 A,
CIN = 0 μF, COUT = 1 μF, CFF = 10 nF
100
0
10
VIN
3.8 V
4.0 V
4.3 V
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = VOUT + 1 V or 2.4 V (whichever is greater), IOUT = 0.5 A,
CIN = 0 μF, COUT = 1 μF, CFF = 10 nF
Figure 23. PSRR vs Frequency and VOUT
0.005
10
VOUT
1.24 V, RMS Noise = 292.7 PV RMS
3.3 V, RMS Noise = 297.7 PV RMS
5 V, RMS Noise = 341.9 PV RMS
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = VOUT + 1 V or 2.4 V (whichever is greater),
IOUT = 0.5 A, CIN = 1 μF, COUT = 1 μF, CFF = 10 nF,
VRMS BW = 10 Hz to 100 kHz
Figure 24. Output Noise (Vn) vs Frequency and VOUT
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Typical Characteristics (continued)
10
10
5
5
Output Voltage Noise (PV —Hz)
Output Voltage Noise (PV —Hz)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
2
1
0.5
0.2
0.1
IOUT
0.01A, RMS Noise = 280.2 PV RMS
0.1A, RMS Noise = 283.2 PV RMS
0.2 A, RMS Noise = 285.2 PV RMS
0.3 A RMS Noise = 281.8 PV RMS
0.5 A RMS Noise = 292.7 PV RMS
0.05
0.02
0.01
0.005
10
100
1k
10k
100k
Frequency (Hz)
2
1
0.5
0.2
0.1
0.05
0.01
1M
0.005
10
10M
VOUT = 1.24 V, CIN = 1 μF, COUT = 1 μF, CFF = 10 nF,
VRMS BW = 10 Hz to 100 kHz
100
1M
10M
Figure 26. Output Noise (Vn) vs Frequency and COUT
1.8
100
5
1.6
0
2
1.4
-100
Output Current (A)
200
10
1
0.5
0.2
0.1
0.05
0.02
CFF
0 nF, RMS Noise = 411.0 PV RMS
10 nF, RMS Noise = 290.4 PV RMS
100 nF, RMS Noise = 244.7 PV RMS
100
1k
10k
100k
Frequency (Hz)
1.2
-200
1
-300
0.8
-400
0.6
-500
0.4
-600
0.2
-700
0
-800
IOUT
VOUT
-0.2
1M
-0.4
-100
10M
VOUT = 3.3 V, VIN = 4.3 V, IOUT = 0.5 A, CIN = 1 μF, COUT = 1 μF,
VRMS BW = 10 Hz to 100 kHz
0
100
200
300
Time (µsec)
400
500
-900
-1000
600
IOUT = 0.001 A to 0.5 A, slew rate = 0.5 A/μs,
VOUT = 3.3 V, VIN = 4.3 V, CIN = 1 μF, COUT = 1 μF
Figure 27. Output Noise (Vn) vs Frequency and CFF
Figure 28. Load Transient
1.8
10
11
1.6
IOUT 600
VOUT
450
0
10
1.4
300
1.2
150
0
0.8
-150
0.6
-300
0.4
-450
0.2
-600
0
-750
-0.2
-900
-0.4
-100
0
100
200
300
Time (µsec)
400
500
-1050
600
IOUT = 0.5 A to 0.001 A, slew rate = 0.5 A/μs,
VOUT = 3.3 V, VIN = 4.3 V, CIN = 1 μF, COUT = 1 μF
AC-Coupled Output Voltage (mV)
20
12
-10
9
-20
8
-30
7
-40
6
-50
5
-60
Input Voltage (V)
750
AC-Coupled Output Voltage (mV)
2
1
AC-Coupled Output Voltage (mV)
2
0.01
Output Current (A)
10k
100k
Frequency (Hz)
20
0.005
10
4
VOUT
VIN
-70
-80
-400
-200
3
0
200
400
Time (µsec)
600
800
2
1000
VIN = 5.3 V to 4.3 V, slew rate = 0.5 V/μs, VOUT = 3.3 V,
IOUT = 0.5 A, CIN = 1 μF, COUT = 1 μF
Figure 30. Line Transient
Figure 29. Load Transient
10
1k
VOUT = 1.24 V, IOUT = 0.5 A, CIN = 1 μF, CFF = 10 nF,
VRMS BW = 10 Hz to 100 kHz
Figure 25. Output Noise (Vn) vs Frequency and IOUT
Output Voltage Noise (PV —Hz)
COUT
1 PF, RMS Noise = 292.7 PVRMS
10 PF, RMS Noise = 325.0 PVRMS
100 PF, RMS Noise = 275.2 PVRMS
0.02
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Typical Characteristics (continued)
20
12
8
10
11
7
0
10
9
-20
8
-30
7
-40
6
-50
5
-60
4
-70
VOUT
VIN
-80
-450 -300 -150
3
0
150 300 450
Time (µsec)
600
2
900 1050
750
VIN
VEN
VOUT
6
5
Voltage (V)
-10
Input Voltage (V)
AC-Coupled Output Voltage (mV)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
4
3
2
1
0
-1
-100
VIN = 4.3 V to 5.3 V, slew rate = 0.5 V/μs, VOUT = 3.3 V,
IOUT = 0.5 A, CIN = 1 μF, COUT = 1 μF
0
100
200
300 400 500
Time (Psec)
600
700
800
900
VEN= 0 V to 2 V, VOUT = 3.3 V, IOUT = 0.5 A,
CIN = 1 μF, COUT = 1 μF
Figure 32. Start-Up With Enable
Figure 31. Line Transient
10
VIN
VOUT
9
8
7
Voltage (V)
6
5
4
3
2
1
0
-1
-2
-200
0
200
400
600
Time (Psec)
800
1000
1200
VIN = 0 V to 5 V, VEN = VIN, VOUT = 3.3 V, IOUT = 0.5 A,
CIN = 1 μF, COUT = 1 μF
Figure 33. Start-Up With Enable Pin Tied to Input
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7 Detailed Description
7.1 Overview
The TPS7A26 is an 18-V, low quiescent current, low-dropout (LDO) linear regulator. The low IQ performance
makes the TPS7A26 an excellent choice for battery-powered or line-power applications that are expected to
meet increasingly stringent standby-power standards.
The 1% accuracy over temperature and power-good indication make this device an excellent choice for meeting
a wide range of microcontroller power requirements.
For increased reliability, the TPS7A26 also incorporates overcurrent, overshoot pulldown, and thermal shutdown
protection. The operating junction temperature is –40°C to +125°C, and adds margin for applications concerned
with higher working ambient temperatures.
The TPS7A26 is available in a thermally enhanced WSON package.
7.2 Functional Block Diagram
TPS7A2601
(Adjustable Version)
OUT
IN
Current
Limit
Thermal
Shutdown
±
FB
+
UVLO
PG
EN
Band-Gap
Reference
GND
+
Logic
PG
Reference
±
Figure 34. Adjustable Version
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Functional Block Diagram (continued)
TPS7A26
(Fixed Version)
OUT
IN
Current
Limit
Thermal
Shutdown
±
R1
+
UVLO
PG
R2
EN
Band-Gap
Reference
GND
+
Logic
PG
Reference
±
Figure 35. Fixed Version
7.3 Feature Description
7.3.1 Output Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
7.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.
The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output
voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the
nominal output regulation, then the output voltage falls as well.
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Feature Description (continued)
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON) =
IRATED
(1)
7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme limits
the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 36 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 36. Current Limit
7.3.4 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.5 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
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Feature Description (continued)
When the thermal limit is triggered with load currents near the value of the current limit, the output may oscillate
prior to the output switching off.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.6 Power Good
The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an
external pullup resistor. The maximum pullup voltage is listed as VPG in the Recommended Operating Conditions
table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than VUVLO(RISING), as listed
in the Electrical Characteristics table. When the VOUT exceeds VIT(PG,RISING), the PG output is high impedance and
the PG pin voltage pulls up to the connected regulated supply. When the regulated output falls below
VIT(PG,FALLING), the open-drain output turns on and pulls the PG output low after a short deglitch time. If output
voltage monitoring is not needed, the PG pin can be left floating or connected to ground.
By connecting a pullup resistor to an external supply, any downstream device can receive power-good (PG) as a
logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid
logic signal for the receiving device.
The recommended maximum PG pin sink current (IPG-SINK) and the leakage current into the PG pin (ILKG(PG)) are
listed in the Electrical Characteristics table.
The PG pullup voltage (VPG_PULLUP), the desired minimum power-good output voltage (VPG(MIN)), and ILKG(PG) limit
the maximum PG pin pullup resistor value (RPG_PULLUP). VPG_PULLUP, the PG pin low-level output voltage (VOL(PG)),
and IPG-SINK limit the minimum RPG_PULLUP. Maximum and minimum values for RPG_PULLUP can be calculated from
the following equations:
RPG_PULLUP(MAX) = (VPG_PULLUP – VPG(MIN)) / ILKG(PG)_MAX
RPG_PULLUP(MIN) = (VPG_PULLUP – VOL(PG)) / IPG-SINK
(2)
(3)
For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from Equation 2,
RPG_PULLUP(MAX) is 11 MΩ. From Equation 3, RPG_PULLUP(MIN) is 5.8 kΩ.
7.3.7 Active Overshoot Pulldown Circuitry
This device has pulldown circuitry connected to VOUT. This circuitry is a 100-μA current sink, in series with a 5.5kΩ resistor, controlled by VEN. When VEN is below VEN(LOW), the pulldown circuitry is disabled and the LDO output
is in high-impedance mode.
If the output voltage is more than 60 mV above nominal voltage when VEN ≥ VEN(LOW), the pulldown circuitry turns
on and the output is pulled down until the output voltage is within 60 mV from the nominal voltage. This feature
helps reduce overshoot during the transient response.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off and internal circuits are shutdown.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(4)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(5)
8.1.2 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are
recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0Grated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5Vrated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast load transient or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
The effective output capacitance value is recommended to not exceed 50 µF.
8.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
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Application Information (continued)
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
Figure 37 shows one approach for protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 37. Example Circuit for Reverse Current Protection Using a Schottky Diode
Figure 38 shows another, more commonly used, approach in high input voltage applications.
IN
CIN
OUT
Device
COUT
GND
Figure 38. Reverse Current Prevention Using A Diode Before the LDO
8.1.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF
can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and
Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit
board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no
other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. Equation 6 calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(6)
NOTE
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use the
minimum input voltage required for correct output regulation.
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Application Information (continued)
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to Equation 7, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA).
TJ = TA + (RθJA × PD)
(7)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ). As described in , use the junction-to-top characterization parameter
(ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. As
described in , use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm
from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(8)
where
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(9)
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
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Application Information (continued)
8.1.8 Special Consideration for Line Transient
During a line transient, the response of this LDO to a very large or fast input voltage change can cause a brief
shutdown lasting up to a few hundred microseconds from the voltage transition. This shutdown can be avoided
by reducing the voltage step size, increasing the transition time, or a combination of both. Figure 39 provides a
boundary to follow to avoid this behavior. If necessary, reduce slew rate and the voltage step size to stay below
the curve.
2
1.8
Slew Rate (V/Psec)
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
VIN Delta
0
0
1
2
3
4
5 6 7 8 9 10 11 12 13 14 15
Input Voltage Step Size (V)
Figure 39. Recommended Input Voltage Step and Slew Rate in a Line transient
8.2 Typical Application
VPG
PG
VIN
TPS7A26
CIN
RPG
VOUT
OUT
IN
R1
COUT
EN
FB
GND
R2
Figure 40. Generating a 5-V Rail From a Multicell Power Bank
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 40.
Table 2. Design Parameters
PARAMETER
20
DESIGN VALUES
VIN
7.2 V
VOUT
5 V ±1%
I(IN) (no load)
< 5 µA
IOUT (max)
330 mA
TA
70°C (max)
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8.2.2 Detailed Design Procedure
Select a 5-V output, fixed or adjustable device to generate the 5-V rail. The fixed-version LDO has internal
feedback divider resistors, and thus has lower quiescent current. The adjustable-version LDO requires external
feedback divider resistors, and is described in the Selecting Feedback Divider Resistors section.
8.2.2.1 Transient Response
As with any regulator, increasing the output capacitor value reduces over- and undershoot magnitude, but
increases transient response duration.
8.2.2.2 Selecting Feedback Divider Resistors
For this design example, VOUT is set to 5 V. The following equations set the output voltage:
VOUT = VFB × (1 + R1 / R2)
R1 + R2 ≤ VOUT / (IFB × 100)
(10)
(11)
For improved output accuracy, use Equation 11 and IFB(TYP) = 10 nA as listed in the Electrical Characteristics
table to calculate the upper limit for series feedback resistance, R1 + R2 ≤ 5 MΩ.
The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 1.24 V as
listed in the Electrical Characteristics table). Use Equation 10 to determine the ratio of R1 / R2 = 3.03. Use this
ratio and solve Equation 11 for R2. Now calculate the upper limit for R2 ≤ 1.24 MΩ. Select a standard value
resistor of R2 = 1.18 MΩ.
Reference Equation 10 and solve for R1:
R1 = (VOUT / VFB – 1) × R2
(12)
From Equation 12, R1 = 3.64 MΩ can be determined. Select a standard resistor value for R1 = 3.6 MΩ. From
Equation 10, select VOUT = 5.023 V.
8.2.2.3 Thermal Dissipation
Junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 13 to calculate the power dissipation. Multiply PD by RθJA and add the
ambient temperature (TA), as Equation 14 shows, to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(13)
(14)
Equation 15 calculates the maximum ambient temperature. Equation 16 calculates the maximum ambient
temperature for typical design applications.
TA(MAX) = TJ(MAX) – (RθJA × PD)
TA(MAX) = 125°C – [73.3°C/W × (7.2 V – 5 V) × 0.33 A] = 71.8°C
(15)
(16)
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8.2.3 Application Curve
2
1.6
Output Current (A)
1.4
400
1.2
200
1
0
0.8
-200
0.6
-400
0.4
-600
0.2
-800
0
-1000
-0.2
-1200
-0.4
-1000
0
1000
2000
Time (µsec)
3000
AC-Coupled Output Voltage (mV)
1000
IOUT 800
VOUT
600
1.8
-1400
4000
IOUT = 1 mA to 0.33 A, slew rate = 0.5 A/μs,
VOUT = 5 V, VIN = 7.2 V, CIN = 1 μF, COUT = 1 μF, CFF = 0 μF
Figure 41. TPS7A26 Load Transient 1 mA to 330 mA)
22
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9 Power Supply Recommendations
The device is designed to operate with an input supply range of 2.4 V to 18 V. If the input supply is noisy,
additional input capacitors with low ESR can help improve output noise performance.
10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close to the device pins as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device and under the DRV thermal pad to distribute heat
10.2 Layout Examples
GND PLANE
COUT
VIN
VOUT
R1
FB
RPG
PG
1
6
CIN
2
5
GND
3
4
EN
R2
GND PLANE
Represents via used for application-specific connections
Figure 42. Adjustable Version Layout Example
VOUT
VIN
COUT
RPG
GND
PG
1
6
CIN
2
5
GND
3
4
EN
GND
PLANE
Represents via used for application-specific connections
Figure 43. Fixed Version Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1)
(1)
PRODUCT
VOUT
TPS7A26xx(x)yyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are
used in the ordering number; for output voltages with a resolution of 50 mV, three digits are used
(for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output version.
yyy is the package designator.
z is the package quantity. R is for large quantity reel, T is for small quantity reel.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
Texas Instruments, TPS7A25 300-mA, 18-V, Ultra-Low-IQ, Low-Dropout Linear Voltage Regulator With
Power-Good data sheet
Texas Instruments, Know Your Limits application report
Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A2601DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7A26
TPS7A2601DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7A26
TPS7A26125DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1X9P
TPS7A2618DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1X8P
TPS7A2625DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1X7P
TPS7A2633DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1WRP
TPS7A2650DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1WPP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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