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TPS7A3401
SBVS163A – JUNE 2011 – REVISED MAY 2015
TPS7A3401 –20-V, –200-mA, Low-Noise Negative Voltage Regulator
1 Features
3 Description
•
•
The TPS7A3401 device is a negative, high-voltage
(–20-V), low-noise linear regulator capable of
sourcing a maximum load of 200 mA.
1
•
•
•
•
•
•
•
•
•
Input Voltage Range: –3 V to –20 V
Noise:
– 80 μVRMS (10 Hz to 100 kHz)
Power-Supply Ripple Rejection:
– 50 dB (1 kHz)
– ≥ 27 dB (10 Hz to 1 MHz)
Adjustable Output:
Approximately –1.18 V to –18 V
Maximum Output Current: 200 mA
Dropout Voltage: 500 mV at 100 mA
Stable With Ceramic Capacitors ≥ 2.2 μF
CMOS Logic-Level-Compatible Enable Pin
Built-In, Fixed, Current Limit, and Thermal
Shutdown Protection
Available in High Thermal Performance MSOP-8
PowerPAD™ Package
Operating Temperature Range: –40°C to 125°C
These linear regulators include a CMOS logic-levelcompatible enable pin. Other features available
include built-in current limit and thermal shutdown
protection to safeguard the device and system during
fault conditions.
The TPS7A3401 is designed using bipolar
technology, and is ideal for instrumentation
applications where clean voltage rails are critical for
improving system performance. This design makes it
a cost-effective choice to power operational
amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and other analog
circuitry.
In addition, the TPS7A3401 linear regulator is
suitable for cost-effective, post DC-DC converter
regulation. By filtering out the output voltage ripple
inherent to DC-DC switching conversion, increased
system performance is provided in instrumentation
applications.
2 Applications
•
•
Cost-Effective Supply Rails for Op Amps, DACs,
ADCs, and Other High-Precision Analog Circuitry
Cost-Effective Post DC-DC Converter Regulation
and Ripple Filtering
Device Information(1)
PART NUMBER
TPS7A3401
PACKAGE
HVSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Post DC-DC Converter Regulation
+18V
IN
OUT
+15V
TPS7A49
-18V
EN
GND
IN
OUT
-15V
TPS7A34
EN
GND
EVM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A3401
SBVS163A – JUNE 2011 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 13
8.3 Do's and Don'ts ....................................................... 15
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
16
16
17
17
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (June 2011) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed Pin Configuration and Functions section; updated table format ............................................................................ 3
•
Changed Thermal Information table; updated values ........................................................................................................... 5
•
Changed parametric symbol for current limit from ILIM to ICL ................................................................................................. 5
2
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5 Pin Configuration and Functions
DGN Package
8-Pin HVSSOP
Top View
OUT
FB
GND
GND
1
2
3
4
8
7
6
5
IN
GND
GND
EN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
OUT
1
O
Regulator output. A capacitor ≥ 2.2 µF must be tied from this pin to ground to ensure stability.
FB
2
I
This pin is the feedback pin that sets the output voltage of the device.
3, 4, 6, 7
—
EN
5
I
This pin turns the regulator ON or OFF. If VEN ≥ VEN(+HI) or VEN ≤ VEN(–HI), the regulator is
enabled. If VEN(+LO) ≥ VEN ≥ VEN(–LO), the regulator is disabled. The EN pin can be connected to
IN, if not used. |VEN| ≤ |VIN|.
IN
8
I
Input supply. A capacitor ≥ 2.2 µF must be tied from this pin to ground to ensure stability.
PowerPAD
—
—
GND
Ground
Must either be left floating or tied to GND. Solder to printed-circuit-board (PCB) plane to enhance
thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
–22
0.3
OUT pin to GND pin
–22
0.3
OUT pin to IN pin
–0.3
22
FB pin to GND pin
–2
0.3
FB pin to IN pin
–0.3
22
EN pin to IN pin
–0.3
22
EN pin to GND pin
–22
22
NR/SS pin to IN pin
–0.3
22
–2
0.3
IN pin to GND pin
Voltage
NR/SS pin to GND pin
Current
Temperature
(1)
Peak output
Internally limited
Operating virtual junction, TJ
–40
125
Storage, Tstg
–65
150
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
UNIT
±1500
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VIN
Input supply voltage
VEN
Enable supply voltage
VOUT
Output voltage
IOUT
Output current
TJ
Operating junction temperature
CIN
Input capacitor
2.2
10
µF
COUT
Output capacitor
2.2
10
µF
CFF
Feed-forward capacitor
0
10
R2
Lower feedback resistor
4
–20
–3
V
0
VIN
V
VREF
–18
V
0
200
mA
–40
125
nF
237
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°C
kΩ
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6.4 Thermal Information
TPS7A3401
THERMAL METRIC (1)
DGN (HVSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
3.7
°C/W
ψJB
Junction-to-board characterization parameter
37.1
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
13.5
°C/W
(1)
63.4
°C/W
53
°C/W
37.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 µF, COUT = 2.2 µF,
and the FB pin tied to OUT, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–3
V
–1.184
–1.166
V
VIN
Input voltage
VREF
Internal reference
TJ = 25°C, VFB = VREF
Output voltage (2)
|VIN| ≥ |VOUT(nom)| + 1 V
–18
VREF
Nominal accuracy
TJ = 25°C, |VIN| = |VOUT(nom)| + 0.5 V
–1.5
1.5
%VOUT
Overall accuracy
|VOUT(nom)| + 1 V ≤ |VIN| ≤ 20 V
1 mA ≤ IOUT ≤ 200 mA
–2.5
2.5
%VOUT
DVOUT(DVIN)
VOUT(NOM)
Line regulation
TJ = 25°C, |VOUT(nom)| + 1 V ≤ |VIN| ≤ 20 V
0.14
%VOUT
DVOUT(DIOUT)
VOUT(NOM)
Load regulation
TJ = 25°C, 1 mA ≤ IOUT ≤ 200 mA
0.04
%VOUT
VIN = 95% VOUT(nom), IOUT = 100 mA
216
VIN = 95% VOUT(nom), IOUT = 200 mA
500
800
mV
330
500
mA
55
100
μA
VOUT
|VDO|
Dropout voltage
ICL
Current limit
IGND
Ground current
|ISHDN|
Shutdown supply current
IFB
Feedback current (3)
|IEN|
Enable current
–20
UNIT
VOUT = 90% VOUT(nom)
–1.202
200
IOUT = 0 mA
IOUT = 100 mA
V
mV
μA
950
VEN = 0.4 V
1
VEN = –0.4 V
5
μA
μA
1
5
14
100
nA
VEN = |VIN| = |VOUT(nom)| + 1 V
0.48
1
μA
VIN = VEN = –20 V
0.51
1
μA
VIN = –20 V, VEN = 15 V
0.50
1
μA
2
15
V
1.8
15
TJ = –40°C to 125°C
VEN(+HI)
Positive enable high-level voltage
VEN(+LO)
Positive enable low-level voltage
0
0.4
V
VEN(–HI)
Negative enable high-level voltage
VIN
–2
V
VEN(–LO)
Negative enable low-level voltage
–0.4
0
V
Vn
Output noise voltage
VIN = –3 V, VOUT(nom) = VREF, COUT = 10 μF,
BW = 10 Hz to 100 kHz
80
μVRMS
PSRR
Power-supply rejection ratio
VIN = –6.2 V, VOUT(nom) = –5 V,
COUT = 10 μF, f = 1 kHz
50
dB
TSD
Thermal shutdown temperature
(1)
(2)
(3)
TJ = –40°C to 85°C
Shutdown, temperature increasing
170
Reset, temperature decreasing
150
°C
At operating conditions, VIN ≤ 0 V, VOUT(nom) ≤ VREF ≤ 0 V. At regulation, VIN ≤ VOUT(nom) – |VDO|. IOUT > 0 flows from OUT to IN.
To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required.
IFB > 0 flows into the device.
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Electrical Characteristics (continued)
At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 µF,
COUT = 2.2 µF, and the FB pin tied to OUT, unless otherwise noted.(1)
PARAMETER
TJ
6
TEST CONDITIONS
Operating junction temperature
MIN
–40
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TYP
MAX
UNIT
125
°C
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6.6 Typical Characteristics
At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF,
COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted.
-1.165
100
90
80
70
IFB (nA)
VFB (V)
-1.17
-1.175
+125°C
+105°C
+85°C
+25°C
-40°C
-1.18
60
50
40
30
20
10
-1.185
0
-25
-20
-15
-10
0
-5
-40 -25 -10
5
20 35 50 65
Temperature (°C)
VIN (V)
Figure 1. Feedback Voltage vs Input Voltage
95
110 125
Figure 2. Feedback Current vs Temperature
2500
1200
0 mA
10 mA
50 mA
100 mA
200 mA
2000
TJ = +25°C
1000
800
1500
IGND (mA)
IGND (mA)
80
1000
600
+125°C
+105°C
+85°C
+25°C
-40°C
400
500
200
IOUT = 100 mA
0
0
-25
-20
-15
-10
0
-5
-25
-20
-15
VIN (V)
-10
0
-5
VIN (V)
Figure 3. Ground Current vs Input Voltage
Figure 4. Ground Current vs Input Voltage
2500
1000
+125°C
+25°C
-40°C
800
2000
600
IEN (nA)
IGND (mA)
400
1500
1000
+125°C
+105°C
+85°C
+25°C
-40°C
500
0
200
0
-200
-400
-600
-800
-1000
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 5. Ground Current vs Output Current
-35
-25
-15
5
-5
VEN (V)
15
25
35
Figure 6. Enable Current vs Enable Voltage
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Typical Characteristics (continued)
At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF,
COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted.
100
3.5
90
+125°C
+105°C
+85°C
+25°C
-40°C
3
80
2.5
ISHDN (mA)
IQ (mA)
70
60
50
40
+125°C
+105°C
+85°C
+25°C
-40°C
30
20
10
IOUT = 0 mA
2
1.5
1
0.5
VEN = -0.4 V
0
0
-25
-20
-15
-10
0
-5
-25
-20
-15
Figure 7. Quiescent Current vs Input Voltage
0
-5
Figure 8. Shutdown Current vs Input Voltage
450
500
400
450
350
400
10 mA
50 mA
100 mA
200 mA
350
VDO (mV)
300
VDO (mV)
-10
VIN (V)
VIN (V)
250
200
+125°C
+105°C
+85°C
+25°C
-40°C
150
100
50
300
250
200
150
100
50
0
0
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
-40 -25 -10
Figure 9. Dropout Voltage vs Output Current
450
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 10. Dropout Voltage vs Temperature
500
VOUT = 90% VOUT(NOM)
400
5
450
350
400
ILIM (mA)
ILIM (mA)
300
250
200
+125°C
+105°C
+85°C
+25°C
-40°C
150
100
50
300
250
0
200
-10
-9
-8
-7
-6
VIN (V)
-5
-4
Figure 11. Current Limit vs Input Voltage
8
350
-3
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF,
COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted.
1
2
ON
1.5
0.6
1
VOUT(NOM) (%)
0.4
0.5
VEN (V)
+125°C
+105°C
+85°C
+25°C
-40°C
0.8
0
OFF
-0.5
0.2
0
-0.2
-0.4
-1
-0.6
-1.5
-0.8
ON
-1
-2
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
-25
110 125
-20
Figure 13. Enable Threshold Voltage vs Temperature
80
0.8
VOUT(NOM) (%)
PSRR (dB)
0.4
60
50
10
+125°C
+105°C
+85°C
+25°C
-40°C
0.6
70
20
VOUT = -5 V
VIN = -6.2 V
IOUT = 200 mA
COUT = 10 mF
CBYP = 0 mF
10
100
0
-5
Figure 14. Line Regulation
1
30
-10
VIN (V)
90
40
-15
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
1k
100k
10k
Frequency (Hz)
1M
0
10M
20
Output Spectral Noise Density (mV/ÖHz)
Figure 15. Power-Supply Rejection Ratio
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 16. Load Regulation
10
VOUT = -1.2 V
VIN = -3 V
IOUT = 200 mA
COUT = 10 mF
1
0.1
0.01
10
100
1k
Frequency (Hz)
10k
100k
Figure 17. Output Spectral Noise Density
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7 Detailed Description
7.1 Overview
The TPS7A3401 device is a wide VIN, low-noise, 150-mA linear regulator (LDO). This device features an enable
pin, programmable soft-start, current limiting, and thermal protection circuitry that allow the device to be used in a
wide variety of applications. As a bipolar-based device, the TPS7A3401 device is ideal for high-accuracy, highprecision applications at higher voltages.
7.2 Functional Block Diagram
GND
EN
Enable
FB
Bandgap
Antisaturation
OUT
Error
Amp
Pass
Device
Thermal
Shutdown
Current
Limit
IN
7.3 Feature Description
7.3.1 Internal Current Limit
The fixed internal current limit of the TPS7A3401 device helps protect the regulator during fault conditions. The
maximum amount of current the device can source is the current limit (330 mA, typical), and it is largely
independent of output voltage. For reliable operation, do not operate the device in current limit for extended
periods of time.
7.3.2 Enable Pin Operation
The TPS7A3401 device provides a dual polarity enable pin (EN) that turns on the regulator when |VEN| > 2 V,
whether the voltage is positive or negative, as shown in Figure 18.
This functionality allows for different system power management topologies:
• Connecting the EN pin directly to a negative voltage, such as VIN, or
• Connecting the EN pin directly to a positive voltage, such as the output of digital logic circuitry.
10
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Feature Description (continued)
VOUT
VEN
VIN
Time (20 ms/div)
Figure 18. Enable Pin Positive and Negative Threshold
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as the |VIN(min)|.
• The input voltage magnitude is greater than the nominal output voltage magnitude added to the dropout
voltage.
• |VEN| > |VEN(HI)|
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage magnitude is lower than the nominal output voltage magnitude plus the specified dropout
voltage magnitude, but all other conditions are met for normal operation, the device operates in dropout mode. In
this mode of operation, the output voltage magnitude is the same as the input voltage magnitude minus the
dropout voltage magnitude. The transient performance of the device is significantly degraded because the pass
device (as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• |VEN| < |VEN(HI)|
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
|VIN| > { |VOUT(nom)| + |VDO|, |VIN(min)| }
|VEN| > |V(HI)|
I OUT < ICL
T J < 125°C
Dropout mode
|VIN(min)| < |VIN| < |VOUT(nom)| + |VDO|
|VEN| > |V(HI)|
—
TJ < 125°C
Disabled mode
(any true condition disables the device)
—
|VEN| < |V(HI)|
—
TJ > 170°C
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A3401 device belongs to a family of new generation linear regulators that use an innovative bipolar
process to achieve ultralow-noise. As a bipolar-based device, the TPS7A3401 device is ideal for high-accuracy,
high-performance analog applications at higher voltages.
8.1.1 Adjustable Operation
The TPS7A3401 device has an output voltage range from –1.174 V to –18 V. The nominal output voltage of the
device is set by two external resistors, as shown in Figure 19.
VOUT
VIN
OUT
IN
CIN
10 mF
CBYP
10 nF
EN
TPS7A3401
R1
FB
R2
COUT
10 mF
GND
Figure 19. Adjustable Operation for Maximum AC Performance
R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1. To ensure
stability under no load conditions, this resistive network must provide a current equal to or greater than 5 μA.
|V
|
VOUT
R1 = R2
- 1 , where FB(nom) > 5mA
R2
VFB(nom)
(1)
If greater voltage accuracy is required, consider the output voltage offset contributions because of the feedback
pin current and use 0.1% tolerance resistors.
8.1.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases duration of the transient response.
8.1.3 Post DC-DC Converter Filtering
Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by
one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements.
DC-DC converters are the preferred solution to step up or down a voltage rail when current consumption is not
negligible. They offer high-efficiency with minimum heat generation, but they have one primary disadvantage:
they introduce a high-frequency component, and the associated harmonics, on top of the DC output signal.
This high-frequency component, if not filtered properly, degrades analog circuitry performance, reducing overall
system accuracy and precision.
The TPS7A3401 device offers a wide-bandwidth, very high power-supply rejection ratio. This specification makes
it ideal for post DC-DC converter filtering, as shown in Figure 20. TI highly recommends using the maximum
performance schematic shown in Figure 19. Also, verify that the fundamental frequency (and its first harmonic, if
possible) is within the bandwidth of the regulator PSRR, shown in Figure 15.
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Application Information (continued)
IN
+18V
OUT
+15V
TPS7A49
-18V
EN
GND
IN
OUT
-15V
TPS7A34
EN
GND
EVM
Figure 20. Post DC-DC Converter Regulation to High-Performance Analog Circuitry
8.1.4 Power for Precision Analog
One of the primary applications of the TPS7A3401 device is to provide ultralow-noise voltage rails to highperformance analog circuitry to maximize system accuracy and precision.
The TPS7A3401 negative high-voltage linear regulator provides ultralow noise positive and negative voltage rails
to high-performance analog circuitry, such as operational amplifiers, ADCs, DACs, and audio amplifiers.
Because of the ultralow noise levels at high voltages, analog circuitry with high-voltage input supplies can be
used. This characteristic allows for high-performance analog solutions to optimize the voltage range, maximizing
system accuracy.
8.2 Typical Application
VIN
OUT
IN
CIN
10 mF
EN
TPS7A3401
CBYP
10 nF
VOUT
R1
FB
R2
Where:
COUT
10 mF
GND
VOUT
³ 5 mA, and
R1 + R2
R1 = R2
VOUT
-1
VREF
Figure 21. Maximize PSRR Performance and Minimize RMS Noise
8.2.1 Design Requirements
The design goals are VIN = –3 V, VOUT = –1.2 V, and IOUT = 150 mA, maximum. The input supply comes from a
supply on the same printed-circuit-board (PCB). The design circuit is shown in Figure 19.
The design space consists of CIN, COUT, CFF, R1, and R2, at TA(max) = 75°C.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
The first step when designing with a linear regulator is to examine the maximum load current along with the input
and output voltage requirements to determine if the device thermal and dropout voltage requirements can be
met. At 150 mA, the input dropout voltage of the TPS7A3401 family is a maximum of 800 mV over temperature;
therefore, the dropout headroom of 1.8 V is sufficient for operation over both input and output voltage accuracy.
Dropout headroom is calculated as VIN – VOUT – VDO(max), and should be greater than 0 for reliable operation.
VDO(max) is the maximum dropout allowed, given worst-case load conditions.
The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element
from the input to the output, multiplied by the maximum load current. In this example, the maximum voltage drop
across in the pass element is |3 V – 1.2 V|, giving us a VDO = 1.8 V. The power dissipated in the pass element is
calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum
power dissipated in the linear regulator is 0.273 W, and is calculated using Equation 2.
PD = (VDO) (IMAX) + (VIN) (IQ)
(2)
Once the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be
calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by
the junction-to-ambient thermal resistance. This calculation gives the worst-case junction temperature; good
thermal design can significantly reduce this number. For thermal resistance information, refer to Thermal
Information. For this example, using the DGN package, the maximum junction temperature rise is calculated to
be 17.3°C. The maximum junction temperature rise is calculated by adding junction temperature rise to the
maximum ambient temperature, which is 75°C for this example. For this example, the designer calculates the
maximum junction temperature is 92.3°C. Keep in mind the maximum junction temperate must be less than
125°C for reliable device operation. Additional ground planes, added thermal vias, and air flow all help to lower
the maximum junction temperature.
Use the following equations to pick the rest of the components:
To ensure stability under no-load conditions, the current through the resistor network must be greater than 5 µA,
as shown in Equation 3.
VFB
> 5mA ® R2 < 242.4 kW
R2
(3)
To set R2 = 100 kΩ for a standard 1% value resistor, we calculate R1 as shown in Equation 4.
VOUT
1.2 V
R1 = R2
- 1 = 100 kW
- 1 = 2.04 kW
1.176 V
VREF(nom)
(4)
Use a standard, 1%, 2.05-kΩ resistor for R1.
For CIN, assume that the –3-V supply has some inductance, and is placed several inches away from the PCB.
For this case, we select a 2.2-µF ceramic input capacitor to ensure that the input impedance is negligible to the
LDO control loop while keep the physical size and cost of the capacitor low; this component is a common-value
capacitor.
For better PSRR for this design, use a 10-µF input and output capacitor. To reduce the peaks from transients but
slow down the recovery time, increase the output capacitor size or add additional output capacitors.
8.2.2.1 Capacitor Recommendations
Low-ESR capacitors should be used for the input, output, noise reduction, and feed-forward capacitors. Ceramic
capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics.
Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R capacitors are the
most cost-effective and are available in higher values.
High-ESR capacitors may degrade PSRR.
8.2.2.1.1 Input and Output Capacitor Requirements
The TPS7A3401 negative, high-voltage linear regulator achieves stability with a minimum input and output
capacitance of 2.2 μF; however, TI highly recommends using a 10-μF capacitor to maximize AC performance.
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Typical Application (continued)
8.2.2.1.2 Feed-Forward Capacitor Requirements
Although feed-forward capacitors (CFF) are not needed to achieve stability, TI highly recommends using 10-nF
capacitors to minimize noise and maximize AC performance.
For more information on CFF, refer to Application Report, Pros and Cons of Using a Feedforward Capacitor with a
Low-Dropout Regulator (SBVA042). This application report explains the advantages of using CFF (also known as
CBYP), and the problems that can occur while using this capacitor.
8.2.3 Application Curves
1
1
+125°C
+105°C
+85°C
+25°C
-40°C
0.6
VOUT(NOM) (%)
0.4
0.2
+125°C
+105°C
+85°C
+25°C
-40°C
0.8
0.6
0.4
VOUT(NOM) (%)
0.8
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
-25
-20
-15
-10
-5
0
0
VIN (V)
Figure 22. Line Regulation
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 23. Load Regulation
8.3 Do's and Don'ts
Place at least one, low-ESR, 2.2-μF capacitor as close as possible to both the IN and OUT terminals of the
regulator to the GND pin.
Provide adequate thermal paths away from the device.
Do not place the input or output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not float the Enable (EN) pin.
9 Power Supply Recommendations
The input supply for the LDO should be within its recommended operating conditions, that is, from –3 V to –20 V.
The input voltage should provide adequate headroom in order for the device to have a regulated output. If the
input supply is noisy, additional input capacitors with low-ESR can help improve the output noise performance.
The input and output supplies should also be bypassed with at least a 2.2-μF capacitor located near the input
and output pins. There should be no other components located between these capacitors and the pins.
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10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with
a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.
The GND pin should be tied directly to the PowerPAD under the IC. The PowerPAD should be connected to any
internal PCB ground planes using multiple vias directly under the IC.
Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize
performance and ensure stability. Every capacitor (CIN, COUT, CFF) must be placed as close as possible to the
device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because these circuits may impact system performance
negatively, and even cause instability.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC performance (such as PSRR, output noise, and transient response), TI recommends designing
the board with separate ground planes for VIN and VOUT, with each ground plane star connected only at the GND
pin of the device.
10.2 Layout Example
Input GND Plane
VOUT
CIN
Sense Line
OUT
1
FB
2
GND
3
GND
4
8
IN
7
GND
6
GND
5
EN
R1
COUT
R2
Thermal
Pad
VIN
Output GND Plane
NOTE: CIN and COUT are size 1208 capacitors, while R1 and R2 are size 0402.
Figure 24. PCB Layout Example (DGN Package)
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10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to a maximum of 125°C. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TPS7A3401 device has been designed to protect against overload
conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A3401 device into
thermal shutdown degrades device reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data or JEDEC low- and high-K boards are given in Thermal Information.
Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated
through-holes to heat dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element, as shown in Equation 5.
PD = (VIN - VOUT) IOUT
(5)
Power dissipation that results from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.
Figure 25 shows the maximum ambient temperature versus the power dissipation of the TPS7A3401 device.
Figure 25 presumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board.
Actual board thermal impedances vary widely. If the application requires high power dissipation, having a
thorough understanding of the board temperature and thermal impedances is helpful to ensure the TPS7A3401
device does not operate above a junction temperature of 125°C.
Maximum Ambient Temperature (°C)
125
115
105
95
85
75
65
55
0
0.05
0.10
0.15
0.20
0.25
0.30
Power Dissipation (W)
Figure 25. Maximum Ambient Temperature (°C) vs Power Dissipation
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Power Dissipation (continued)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in Thermal
Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and
the package than RθJA. The junction temperature can be estimated with Equation 6.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 5,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(6)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A3401. The TPS7A3401EVM-042 evaluation module (and related user's guide) can be requested at the
Texas Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A3401 is available through the product folder under the
Tools & Software tab.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042.
• Using New Thermal Metrics, SBVA025.
• TPS7A3401EVM-042 Evaluation Module User's Guide, SLVU428.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A3401DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PPKQ
TPS7A3401DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PPKQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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