TPS7A43
SBVS393B – DECEMBER 2020 – REVISED NOVEMBER 2022
TPS7A43 50-mA, 85-V, Ultra-Low IQ, Low-Dropout Linear Voltage Regulator With
Power-Good, Precision Enable, and Selectable Mid-Output Rail
1 Features
3 Description
•
•
The TPS7A43 low-dropout (LDO) linear voltage
regulator introduces a combination of a 4-V to 85-V
input voltage range with very-low quiescent current.
•
•
•
•
•
•
•
•
•
Input voltage: 4 V to 85 V
Wide output (OUT) voltage range:
– Adjustable: 1.24 V to 14.5 V
– Fixed: 1.25 V to 5.0 V
Selectable intermediate output (MID_OUT):
– 10 V, 12 V, 15 V
Maximum output current:
– 50 mA (shared between OUT and MID_OUT)
1% accuracy over temperature
Ultra-low IQ: 5.5 μA
Precision enable
Power-good (PG) output (open drain)
Thermal shutdown and overcurrent protection
Operating junction temperature: –40°C to +125°C
Package: HVSSOP-10 (RθJA = 53.7°C/W)
2 Applications
•
•
•
•
•
•
•
Cordless power tools
DC motors and fans
Programmable logic controllers (PLCs)
Field transmitter and process sensors
Smoke and heat detectors
EV charging infrastructure
Battery packs
This device can support a wide range of input
voltages (for example, a 15-s battery and 24-V to
48-V line power) and withstand line transient voltages
up to 85 V. These features help modern applications
meet increasingly stringent energy requirements, and
help extend battery life in portable-power solutions.
The TPS7A43 output (OUT) is available in both
fixed and adjustable output versions, which can
regulate from 1.24 V to 14.5 V at 1% accuracy. The
device also provides a second intermediate output
(MID_OUT) that can be set to 10 V, 12 V, and 15 V
using the MVSEL pins and can be used to bias gate
drivers in place of a discrete regulator.
The TPS7A43 features a precision enable input that
helps enable or disable the LDO at a fixed and
accurate threshold voltage using a resistor divider
from the input.
The power-good (PG) output is used to monitor the
voltage at the feedback pin to indicate the status of
the output voltage. The EN input and PG output can
be used for sequencing multiple power sources in the
system.
Package Information(1)
PART NUMBER
TPS7A43
(1)
VIN
CIN
IN
PACKAGE
BODY SIZE (NOM)
DGQ (HVSSOP, 10)
3.00 mm × 3.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
VOUT
OUT
COUT
VEN
GND
TPS7A43
VMVSEL1
GND
NC
EN
GND
VMID_OUT
MVSEL1
MID_OUT
MVSEL2
PG
CMID_OUT
VMVSEL2
GND
GND
Typical Application Circuit
Line Transient With VMID_OUT = 12 V, VOUT = 3.3 V,
IOUT = 50 mA
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A43
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SBVS393B – DECEMBER 2020 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 8
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagrams....................................... 15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 23
8.3 Power Supply Recommendations.............................25
8.4 Layout....................................................................... 25
9 Device and Documentation Support............................27
9.1 Device Support......................................................... 27
9.2 Documentation Support............................................ 27
9.3 Receiving Notification of Documentation Updates....27
9.4 Support Resources................................................... 27
9.5 Trademarks............................................................... 27
9.6 Electrostatic Discharge Caution................................27
9.7 Glossary....................................................................28
10 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2022) to Revision B (November 2022)
Page
• Changed document title......................................................................................................................................1
Changes from Revision * (December 2020) to Revision A (September 2022)
Page
• Changed document status from Advance Information to Production Data ........................................................1
2
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5 Pin Configuration and Functions
OUT
1
10
IN
FB
2
9
NC
PG
3
MVSEL1
GND
Thermal pad
OUT
1
10
IN
NC
2
9
NC
8
MID_OUT
PG
3
4
7
MVSEL2
MVSEL1
5
6
EN
GND
Not to scale
Thermal pad
8
MID_OUT
4
7
MVSEL2
5
6
EN
Not to scale
Figure 5-1. DGQ Package (Adjustable),
10-Pin HVSSOP (Top View)
Figure 5-2. DGQ Package (Fixed), 10-Pin HVSSOP
(Top View)
Table 5-1. Pin Functions
PIN
NAME
DGQ
(Adjustable)
DGQ
(Fixed)
TYPE
DESCRIPTION
EN
6
6
Input
Precision enable pin. Driving this pin higher than VEN(HI) enables the device.
Driving this pin lower than VEN(LOW) disables the device. This pin can be left
floating to enable the device because the device features an internal pullup
current source. If this pin is tied to the IN pin then the input voltage must not
exceed 18 V; see the Recommended Operating Conditions table.
FB
2
—
Input
Feedback pin. Input to the control-loop error amplifier for the (OUT) output.
This pin is used to set the output voltage of the device with the use of
external resistors. For adjustable-voltage version devices only. This pin must
not be left floating.
GND
5
5
—
IN
10
10
Input
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger ceramic capacitor from IN to ground; see
the Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
Output
MID output pin. A capacitor is required from MID_OUT to ground for stability.
For best transient response, use the nominal recommended value or larger
capacitor from MID_OUT to ground. Follow the recommended capacitor
value as listed in the Recommended Operating Conditions table. Place the
MID output capacitor as close to the MID_OUT and GND pins of the device
as possible.
MID_OUT
8
8
Ground pin.
MVSEL1
4
4
Input
MID_OUT voltage-select pin. The MVSEL1 pin and MVSEL2 pin are used
to set the MID_OUT voltage; see the MID_OUT Voltage Setting section for
details on how to set the MID_OUT voltage using these pins. Do not float this
pin, instead tie this pin to GND if not used to set VMID_OUT.
MVSEL2
7
7
Input
MID_OUT voltage-select pin. The MVSEL2 pin and MVSEL1 pin are used
to set the MID_OUT voltage; see the MID_OUT Voltage Setting section for
details on how to set the MID_OUT voltage using these pins. Do not float this
pin, instead tie this pin to GND if not used to set VMID_OUT.
NC
9
9
—
No internal connection. This pin must be left floating to observe high voltage
clearance between the IN and MID_OUT pins.
NC
—
2
—
No internal connection. This pin can be left floating or tied to the GND plane
to improve thermal performance.
Output
Output pin. A capacitor is required from OUT to ground for stability. For best
transient response, use the nominal recommended value or larger capacitor
from OUT to ground. Follow the recommended capacitor value as listed in
the Recommended Operating Conditions table. Place the output capacitor as
close to the OUT and GND pins of the device as possible.
OUT
1
1
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Table 5-1. Pin Functions (continued)
PIN
DGQ
(Adjustable)
NAME
PG
Thermal pad
DGQ
(Fixed)
TYPE
DESCRIPTION
3
3
Output
Power-good pin. An open-drain output indicates when the output voltage
reaches VIT(PG, RISING); see the Electrical Characteristics table. If not used,
this pin can be left floating or tied to the GND plane to improve thermal
performance.
Pad
Pad
—
Exposed pad of the package. Connect this pad to ground or leave floating.
Connect the thermal pad to a large-area GND plane for improved thermal
performance.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Voltage(2)
Current
Temperature
(1)
(2)
(3)
(4)
(5)
MIN
MAX
VIN
–0.3
90(3)
VOUT (adjustable version)
–0.3
VMID + 0.3(4)
VOUT (fixed version)
–0.3
5.5
VMID_OUT
–0.3
VIN + 0.3(5)
VFB
–0.3
5.5
VEN
–0.3
20
VMVSEL1
–0.3
20
VMVSEL2
–0.3
20
VPG
–0.3
20
Maximum output
Internally limited
Maximum MID output
Internally limited
UNIT
V
A
Operating junction, TJ
–50
150
Storage, Tstg
–65
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device
lifetime.
All voltages with respect to GND.
Absolute maximum voltage, withstand 90 V for 200 ms.
VMID_OUT + 0.3 V or 20 V (whichever is smaller).
VIN + 0.3 V or 20 V (whichever is smaller).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
VIN
Input voltage
VMID_OUT
MID output voltage
VOUT
NOM
MAX
UNIT
4
85
V
10
15
V
Output voltage (adjustable version)
1.24
VMID_OUT –
VDO(OUT)
V
VOUT
Output voltage (fixed version)
1.25
5.5
IOUT
Output current
0
50 – IMID_OUT
mA
IMID_OUT
MID rail output current
0
50
mA
VMVSEL1
MID voltage select input voltage 1
0
18
V
VMVSEL2
MID voltage select input voltage 2
0
18
V
VEN
Enable voltage
0
18
V
VPG (1)
Power-good voltage
0
18
CIN (2)
Input capacitor
COUT (2)
Output capacitor
CMID_OUT (2) (3)
MID output capacitor
TJ
Operating junction temperature
(1)
(2)
(3)
0.1
1
V
V
μF
2.2
100
3 × COUT
μF
μF
–40
125
°C
Select pullup resistor to limit PG pin sink current when PG output is driven low. See the Power Good section for details.
All capacitor values are assumed to derate to 50% of the nominal capacitor value.
Maintain a 3:1 ratio between CMID_OUT vs COUT for stability.
6.4 Thermal Information
TPS7A43
THERMAL METRIC(1)
HVSSOP (DGQ)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
53.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
76.6
°C/W
RθJB
Junction-to-board thermal resistance
26.8
°C/W
ΨJT
Junction-to-top characterization parameter
3.6
°C/W
ΨJB
Junction-to-board characterization parameter
26.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 1.5V or 4V, whichever is greater, FB tied to OUT (adjustable version
only), IOUT = 1 mA, IMID_OUT = 0mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF, CMID_OUT = 4.7 μF, and COUT =
1 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
ΔVOUT
ΔVOUT
Output voltage
accuracy
VFB
Feedback voltage
ΔVOUT(ΔVIN)
Line regulation(1)
ΔVOUT(ΔIOUT)
Load regulation
ΔVMID_OUT
MIN
TYP
MAX
UNIT
Adjustable version, VOUT = VFB
1.23
1.24
1.25
V
Fixed output version, TJ = 25℃
–0.5
0.5
–0.75
0.75
Fixed output version
MID output voltage
accuracy
Adjustable version only
1.24
V
(VOUT(nom) + 1 V or 4 V) ≤ VIN ≤ 85 V
–0.05
0.05
VMID_OUT(nom) + 1.5 V ≤ VIN ≤ 85 V
–0.05
0.05
1 mA ≤ IOUT ≤ 50 mA,
IMID_OUT = 0 mA
–0.15
0.10
VIN = VMID_OUT + 1.5 V
%
VMVSEL1 ≤ VMVSEL1(LOW),
VMVSEL2 ≤ VMVSEL2(LOW)
14.4
15
15.6
VMVSEL1 ≤ VMVSEL1(LOW)
or VMVSEL1 ≥
VMVSEL1(HIGH),
VMVSEL2 ≥ VMVSEL2(HIGH)
11.5
12
12.5
VMVSEL1 ≥ VMVSEL1(HIGH),
VMVSEL2 ≤ VMVSEL2(LOW)
9.6
10
10.4
%
%
V
Line regulation of
MID output(1)
(VMID_OUT(nom)) + 1.5 V ≤ VIN ≤ 85 V,
IMID_OUT = 1 mA, IOUT = 0 mA
–0.1
0.1
%
Load regulation of
MID output
1 mA ≤ IMID_OUT ≤ 50 mA
VIN = VMID_OUT + 1.5 V
IOUT = 0 mA
–0.2
0.1
%
VDO(OUT)
Dropout voltage of
VIN to VOUT (2)
IOUT = 50 mA
800
mV
VDO(OUT)
Dropout voltage of
I
= 50 mA
VMID_OUT to VOUT (2) OUT
200
mV
VDO(MID_OUT)
Dropout voltage of
VIN to VMID_OUT (3)
IMID_OUT = 50 mA
600
mV
ICL(OUT)
Output current limit
VOUT = 0.9 × VOUT(nom)
100
125
145
mA
ICL(MID_OUT)
MID output current
limit
VOUT = 0.9 × VMID_OUT(nom),
VIN = VMID_OUT + 1.5 V
118
145
165
mA
5.5
7
ΔVMID_OUT(ΔVIN)
ΔVMID_OUT(Δ
IOUT)
IGND
6
TEST CONDITIONS
Ground pin current
IOUT = IMID_OUT = 0 mA,
VIN = VMID_OUT + 1.5 V
TJ = 25°C
TJ = –40°C to +125°C
9
IOUT = 50 mA,
VIN = VMID_OUT + 1.5 V
µA
185
ISHUTDOWN
Shutdown current
VEN ≤ VEN(LOW) ,
VIN = VMID_OUT(nom) + 1.5
V
IOUT = IMID_OUT = 0 mA
TJ = –40°C to +85°C
TJ = –40°C to +85°C
710
ISHUTDOWN
Shutdown current
VEN ≤ VEN(LOW) ,
VIN =85 V
IOUT = IMID_OUT = 0 mA
IFB
FB pin current
10
nA
IMVSEL1
MVSEL1 pin current VMVSEL1 = 18 V
10
nA
IMVSEL2
MVSEL2 pin current VMVSEL2 = 18 V
10
nA
IEN
EN pin current
10
nA
VMVSEL1(HIGH)
MVSEL1 pin highlevel input voltage
VMVSEL1(LOW)
MVSEL1 pin lowlevel input voltage
TJ = –40°C to +125°C
710
TJ = –40°C to +125°C
1600
nA
2100
nA
1900
2500
VEN = 18 V
0.9
V
0.3
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V
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 1.5V or 4V, whichever is greater, FB tied to OUT (adjustable version
only), IOUT = 1 mA, IMID_OUT = 0mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF, CMID_OUT = 4.7 μF, and COUT =
1 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
VMVSEL2(HIGH)
MVSEL2 pin highlevel input voltage
VMVSEL2(LOW)
MVSEL2 pin lowlevel input voltage
VEN(HI)
Enable rising
threshold
Device enabled
1.15
VEN(LOW)
Enable falling
threshold
Device disabled
1.11
VEN(HYST)
Enable pin
hysteresis
VIT(PG,RISING)
PG pin threshold
rising
RPULLUP = 10 kΩ, VOUT rising,
VIN ≥ VUVLO(RISING)
VHYS(PG)
PG pin hysteresis
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
VIT(PG,FALLING)
PG pin threshold
falling
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
VOL(PG)
PG pin low level
output voltage
VOUT < VIT(PG,FALLING), IPG-SINK = 500 µA
ILKG(PG)
PG pin leakage
current
VOUT > VIT(PG,RISING), VPG = 18 V
PSRR(OUT)
Power-supply
rejection ratio of
OUT rail
PSRR(MID_OUT)
Power-supply
rejection ratio of
MID_OUT rail
TYP
MAX
0.9
V
0.3
V
1.24
1.35
V
1.19
1.28
V
50
IOUT = 20 mA
IMID_OUT = 20 mA
88
93
mV
96.5
%VOUT
3
84
UNIT
90
5
f = 10 Hz
76
f = 100 Hz
67
f = 1 kHz
82
f = 100 kHz
73
f = 10 Hz
61
f = 100 Hz
64
f = 1 kHz
55
f = 100 kHz
47
94.5
0.4
V
130
nA
dB
Vn
Output noise
voltage
BW = 10 Hz to 100 kHz, VOUT = 1.24 V
124
μVRMS
TSD(shutdown)
Thermal shutdown
temperature
Shutdown, temperature increasing
170
°C
(1)
(2)
(3)
Line regulation from Input of the LDO to the final output of the LDO.
VDO is measured with VIN = 0.95 × VOUT(nom) for fixed output voltage versions. VDO is not measured for fixed output voltage versions
when VOUT ≤ 3.1 V. For the adjustable output device, VDO is measured with VFB = 0.95 × VFB(nom).
VDO(MID_OUT) is measured with VIN = 0.95 × VMID_OUT(nom) for Mid output voltages.
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
0.5
0.5
TJ
0qC
25qC
55qC
40qC
0.3
85qC
125qC
0.2
0.1
0
-0.1
-0.2
-0.3
TJ
0.4
150qC
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
0.4
-0.4
55qC
40qC
0.3
85qC
125qC
150qC
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current (A)
0.1
0
10
VOUT = 1.24 V (adjustable)
20
30
40
50
Input Voltage (V)
60
70
80 85
VOUT = 1.24 V (adjustable)
Figure 6-1. VOUT Accuracy vs IOUT
Figure 6-2. VOUT Accuracy vs VIN
1
2
TJ
TJ
0.8
55qC
40qC
0.6
0qC
25qC
85qC
125qC
150qC
55qC
40qC
1.75
0qC
25qC
85qC
125qC
150qC
1.5
Output Voltage (V)
MID_OUT Voltage Accyracy (%)
0qC
25qC
0.4
0.2
0
-0.2
-0.4
1.25
1
0.75
0.5
-0.6
0.25
-0.8
-1
13
0
23
33
43
53
Input Voltage (V)
63
73
0
83
0.02
0.04
0.06
0.08
0.1
Output Current (A)
0.12
0.14
0.16
VOUT = 1.24 V (adjustable)
VMID_OUT = 12 V
Figure 6-4. VOUT vs ICL(OUT)
Figure 6-3. VMID_OUT Accuracy vs VIN
18
1000
TJ
55qC
40qC
14
0qC
25qC
85qC
125qC
700
150qC
500
Ground Current (PA)
MID_OUT Voltage (V)
16
12
10
8
6
300
200
100
TJ
70
55qC
40qC
50
4
2
30
0
20
0
0.02
0.04
0.06
0.08
0.1
MID_OUT Current (A)
0.12
0.14
0.16
0
8
85qC
125qC
150qC
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current (A)
0.1
VIN = 11 V, VOUT = 1.24 V (adjustable)
VMID_OUT = 12 V
Figure 6-5. VMID_OUT vs IMID_OUT
0qC
25qC
Figure 6-6. IGND vs IOUT (MID_OUT in Dropout)
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
45
300
TJ
270
55qC
40qC
85qC
125qC
40
150qC
210
180
150
120
90
85qC
125qC
30
25
20
15
10
60
30
5
0
0
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current (A)
0.1
0
10
20
30
40
50
Input Voltage (V)
VIN = 16.5 V, VMID_OUT = 15 V, VMVSEL1 = VMVSEL2 = 0 V,
VOUT = 1.24 V (adjustable)
60
70
80 85
IOUT = 0 mA
Figure 6-7. IGND vs IOUT
Figure 6-8. IGND vs VIN
1.25
0.35
TJ
TJ
0qC
25qC
85qC
125qC
0.75
0.5
0.25
0qC
25qC
55qC
40qC
0.3
Output Voltage Dropout (V)
55qC
40qC
1
Shutdown Current (PA)
TJ
0qC
25qC
55qC
40qC
35
Ground Current (PA)
Ground Current (PA)
240
0qC
25qC
85qC
125qC
150qC
0.25
0.2
0.15
0.1
0.05
0
0
10
20
30
40
50
Input Voltage (V)
60
70
0
80 85
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current (A)
VOUT = 1.24 V (adjustable)
VEN = 1 V
Figure 6-10. VDO(OUT) vs IOUT
Figure 6-9. ISHUTDOWN vs VIN
1.6
18
55qC
40qC
0qC
25qC
85qC
125qC
120
VOUT
16
150qC
VMID_OUT
14
1.2
Output Voltage (V)
MID_OUT Dropout Voltage (V)
TJ
1.4
1
0.8
0.6
0.4
0.2
0.03
0.04 0.05 0.06 0.07
MID_Output Current (A)
0.08
0.09
0.1
VMID_OUT = 15 V, VMVSEL1 = VMVSEL2 = 0 V, IOUT = 0 mA
100
80
60
10
40
8
20
6
0
4
-20
2
-40
0
-60
0
0.02
VIN
VIN scale o
m Rest of
channels scale
12
VPG
-2
0
0.01
0.1
400
800
1,200
Time (Ps)
1,600
Input Voltage (V)
0
-80
2,000
CIN = 0 μF, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 10 mA
Figure 6-12. Fast Start-Up
Figure 6-11. VDO(MID_OUT) vs IMID_OUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
18
120
Output Voltage (V)
14
VMID_OUT
VPG
VIN
100
80
VIN scale o
m Rest of
12 channels scale
60
10
40
8
20
6
0
4
-20
2
-40
0
-60
-2
0
400
800
1,200
Time (Ps)
Input Voltage (V)
VOUT
16
-80
2,000
1,600
CIN = 0 μF, VIN ramp rate = 45 V/ms,VOUT = 3.3 V,
IOUT = 10 mA
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-13. Slow Start-Up
Figure 6-14. Line Transient
-5
160
-10
80
VIN scale o
AC-Coupled VMID_OUT (mV)
240
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
100
240
50
200
0
160
-50
120
-100
80
VIN scale o
0
0
2
0.1
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
Figure 6-16. Line Transient
Figure 6-15. Line Transient
5
320
VOUT
0.2
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 10 mA
m VOUT scale
40
-200
0
0.4
VIN
280
-150
-15
0.2
VMID_OUT
150
0
0
320
m VOUT scale
VIN
200
320
m VOUT scale
VIN
VMID_OUT
VIN
240
-5
160
-10
80
VIN scale o
0
0.1
0.2
0.3
0.4 0.5 0.6
Time (ms)
0.7
0.8
0.9
1
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-17. Line Transient
10
280
100
240
50
200
0
160
-50
120
-100
80
VIN scale o
-150
-15
0
AC-Coupled VMID_OUT (mV)
0
Input Voltage (V)
AC-Coupled VOUT (mV)
150
Input Voltage (V)
VOUT
Input Voltage (V)
AC-Coupled VOUT (mV)
200
320
m VOUT scale
Input Voltage (V)
5
40
-200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
VIN = 4 V to 85 V, VIN ramp rate = 1 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-18. Line Transient (VMID_OUT in Dropout)
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
200
240
-5
160
-10
80
VIN scale o
0.3
0.4 0.5 0.6
Time (ms)
0.7
0.8
0.9
150
280
100
240
50
200
0
160
-50
320
0
0.1
160
80
AC-Coupled Voltage (mV)
240
-10
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
VIN scale o
IOUT
450
400
200
350
150
300
100
250
50
200
0
150
-50
100
-100
50
-150
0
0
0
0
0.1
0.2
0.3
0.4 0.5 0.6
Time (ms)
0.7
0.8
0.9
1
250
-200
-15
0.9
500
VOUT
VMID_OUT
300
-5
0.2
350
VIN
0
40
Figure 6-20. Line Transient (VMID_OUT in Dropout)
Input Voltage (V)
AC-Coupled VOUT (mV)
VIN scale o
VIN = 4 V to 85 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-19. Line Transient (VMID_OUT in Dropout)
VOUT
80
0
VIN = 4 V to 85 V, VIN ramp rate = 1 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
m VOUT scale
120
-100
1
5
VIN
-200
0
0.2
VMID_OUT
-150
-15
0.1
AC-Coupled VMID_OUT (mV)
0
0
320
m VOUT scale
VIN
Input Voltage (V)
AC-Coupled VOUT (mV)
VOUT
Input Voltage (V)
320
m VOUT scale
500
1000
1500
1
2000 2500
Time (Ps)
3000
3500
Output Current (mA)
5
-50
4000
VIN = 65 V, VOUT = 3.3 V, IOUT = 0 mA to 50 mA to 0 mA,
IOUT slew rate = 1 A/μs
VIN = 4 V to 85 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-22. Load Transient
350
350
300
150
300
100
VOUT
VMID_OUT
IOUT
250
50
200
0
150
-50
100
500
VOUT
VMID_OUT
IOUT
450
250
400
200
350
150
300
100
250
50
200
0
150
-50
100
-100
50
-100
50
-150
0
-150
0
-200
-50
100
-200
0
10
20
30
40
50
60
Time (Ps)
70
80
90
VIN = 65 V, VOUT = 3.3 V, IOUT = 0 mA to 50 mA to 0 mA,
IOUT slew rate = 1 A/μs
0
500
1000
1500
2000 2500
Time (Ps)
3000
3500
Output Current (mA)
400
200
AC-Coupled Voltage (mV)
250
Output Current (mA)
AC-Coupled Voltage (mV)
Figure 6-21. Line Transient (VMID_OUT in Dropout)
-50
4000
VIN = 65 V, VOUT = 3.3 V, IOUT = 1 mA to 50 mA to 1 mA,
IOUT slew rate = 1 A/μs
Figure 6-23. Load Transient (Rising Edge)
Figure 6-24. Load Transient
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6.6 Typical Characteristics (continued)
150
300
100
0
250
VOUT
200
VMID_OUT
IOUT
150
50
-50
100
-100
50
-150
0
-200
0
10
20
30
40
50
60
Time (Ps)
70
80
90
100
50
200
0
150
-50
100
-100
50
-150
0
0
VIN = 65 V, VOUT = 3.3 V, IOUT = 1 mA to 50 mA to 1 mA,
IOUT slew rate = 1 A/μs
100
-15
50
-20
0
-25
0
1000
2000
3000
4000 5000
Time (Ps)
6000
7000
-5
150
-10
100
-15
50
-20
0
3000
4000 5000
Time (Ps)
6000
7000
-50
8000
VIN = 65 V, VOUT = 3.3 V, IMID_OUT = 1 mA to 50 mA to 1 mA,
IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
Figure 6-29. Load Transient (MID_OUT)
12
Spectral Noise Density (PV/—Hz)
200
MID_OUT Current (mA)
AC-Coupled Output Voltage (mV)
0
2000
IMID_OUT
200
0
150
-50
100
-100
50
-150
0
1000
2000
3000
4000 5000
Time (Ps)
6000
7000
-50
8000
Figure 6-28. Load Transient (MID_OUT)
250
1000
-50
8000
VIN = 65 V, VMID_OUT = 12 V, IMID_OUT = 1 mA to 50 mA to
1 mA, IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
Figure 6-27. Load Transient (MID_OUT)
5
0
7000
50
0
VIN = 65 V, VOUT = 3.3 V, IMID_OUT = 0 mA to 50 mA to 0 mA,
IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
-25
6000
-200
-50
8000
VOUT
IMID_OUT
4000 5000
Time (Ps)
250
VMID_OUT
AC-Coupled MID_OUT Voltage (mV)
-10
MID_OUT Current (mA)
AC-Coupled Output Voltage (mV)
150
3000
100
200
VOUT
IMID_OUT
2000
Figure 6-26. Load Transient (MID_OUT)
250
-5
1000
VIN = 65 V, VMID_OUT = 12 V, IMID_OUT = 0 mA to 50 mA to
0 mA, IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
Figure 6-25. Load Transient (Rising Edge)
0
IMID_OUT
-200
-50
100
5
250
VMID_OUT
MID_OUT Current (mA)
350
MID_OUT Current (mA)
400
200
AC-Coupled MID_OUT Voltage (mV)
250
Output Current (mA)
AC-Coupled Voltage (mV)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
200
100
50
IOUT = 0.1 mA, Vn = 235 PVRMS
IOUT = 1.0 mA, Vn = 320 PVRMS
IOUT = 20 mA, Vn = 385 PVRMS
IOUT = 50 mA, Vn = 398 PVRMS
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 13 V, VOUT = 3.3 V, VRMS bandwidth = 10 Hz to 100 kHz
Figure 6-30. Spectral Noise Density vs Frequency and IOUT
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6.6 Typical Characteristics (continued)
Spectral Noise Density (PV/—Hz)
100
50
Power Supoply Rejection Ratio PSRR (dB)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
COUT = 1.0 PF, Vn = 385 PVRMS
COUT = 100 PF, Vn = 317 PVRMS
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 13 V, VOUT = 3.3 V, IOUT = 20 mA,
VRMS bandwidth = 10 Hz to 100 kHz
120
100
80
60
40
20
0
10
VIN - VMID_OUT = 1 V
VIN - VMID_OUT = 3 V
VIN - VMID_OUT = 6 V
80
60
40
20
100
1k
10k
100k
Frequency (Hz)
1M
100
80
60
40
20
Power Supply Rejection Ratio PSRR (dB)
Power Supply Rejection Ration PSRR(dB)
60
40
20
10k
100k
Frequency (Hz)
1M
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 6-34. OUT PSRR vs Frequency and COUT
IMID_OUT = 1 mA
IMID_OUT = 20 mA
IMID_OUT = 50 mA
1k
10M
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IOUT = 20 mA
Figure 6-33. OUT PSRR vs Frequency and VIN
100
1M
COUT = 1 PF
COUT = 100 PF
0
10
10M
100
0
10
10k
100k
Frequency (Hz)
120
CIN = 0 μF,VOUT = 3.3 V, IOUT = 20 mA
80
1k
Figure 6-32. OUT PSRR vs Frequency and IOUT
Power Supply Rejection Ratio PSRR (dB)
Power Supply Rejection Ratio PSRR (dB)
120
0
10
100
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V
Figure 6-31. Spectral Noise Density vs Frequency and COUT
100
IOUT = 1 mA
IOUT = 20 mA
IOUT = 50 mA
10M
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IOUT = 0 mA
100
80
VIN - VMID_OUT = 1 V
VIN - VMID_OUT = 3 V
VIN - VMID_OUT = 6 V
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
CIN = 0 μF, VOUT = 3.3 V, IMID_OUT = 20 mA, IOUT = 0 mA
Figure 6-35. MID_OUT PSRR vs Frequency and IMID_OUT
Figure 6-36. MID_OUT PSRR vs Frequency and VIN
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6.6 Typical Characteristics (continued)
Power Supply Rejection Ratio PSRR (dB)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
120
CMID_OUT = 3.3 PF
CMID_OUT = 300 PF
100
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IMID_OUT = 20 mA,
IOUT = 0 mA
Figure 6-37. MID_OUT PSRR vs Frequency and CMID_OUT
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7 Detailed Description
7.1 Overview
The TPS7A43 is an 85-V, low quiescent current, low-dropout (LDO) linear regulator. The very low IQ
performance makes the device an excellent choice for battery-powered or line-power applications that are
expected to meet increasingly stringent standby-power standards.
The high accuracy over temperature and power-good indication make this device designed for meeting a broad
range of microcontroller power requirements. The device features a selectable MID_OUT voltage pin to provide
a secondary voltage to serve as a bias rail for gate drivers.
For increased robustness, the TPS7A43 also incorporates precision enable, output current limit, active
discharge, and thermal shutdown protection. The operating junction temperature for this device is from –40°C to
+125°C.
7.2 Functional Block Diagrams
OUT
IN
Band gap
1.24-V
band gap
±
Current
limit
±
Current
limit
+
+
MVSEL1
FB
Internal
controller
MVSEL2
PG
Thermal
shutdown
±
0.9 x 1.24-V Band Gap
+
+
EN
±
GND
MID_OUT
Band gap
GND
Figure 7-1. Adjustable Version
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OUT
IN
Band gap
1.24-V
band gap
±
Current
limit
±
Current
limit
+
+
MVSEL1
NC
550 NŸ
Internal
controller
GND
MVSEL2
PG
Thermal
Shutdown
±
0.9 x 1.24-V Band Gap
+
+
EN
±
GND
MID_OUT
Band Gap
GND
Figure 7-2. Fixed Version
7.3 Feature Description
7.3.1 MID_OUT Voltage Selection
The TPS7A43 features a MID_OUT voltage pin that provides a secondary output voltage supply in addition to
the OUT pin, which is the main output voltage supply. The MID_OUT voltage can be set using the MVSEL1 and
MVSEL2 pins; see the MID_OUT Voltage Setting section for more details.
7.3.2 Precision Enable
The TPS7A43 features a precision enable circuit. The enable pin (EN) is active high; thus, enable the device
by forcing the voltage of the enable pin to exceed the VEN(HI) voltage; see the Electrical Characteristics table.
Turn off the device by forcing the voltage of the enable pin to drop below the VEN(LOW) voltage; see the Electrical
Characteristics table. EN is pulled high by a 50-nA current source; therefore, EN can be left floating to enable the
device. Board-level leakage on the order of tens of nanoamperes can cause the EN pin to be pulled low when
EN is left floating, so care must be taken to minimize leakage if this functionality is used.
If this pin is tied to the IN pin, the input voltage must not exceed 18 V; see the Recommended Operating
Conditions table.
16
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As shown in Figure 7-3, an external resistor divider circuit can be used to enable the device using the input
voltage.
IN
Internal
controller
R1
+
EN
±
R2
Band gap
GND
Figure 7-3. Enable the Device Using the Input Voltage
The VEN(HI) (maximum) and VEN(LOW) (minimum) thresholds along with the application input voltage can be used
to set the R1 to R2 resistor divider ratio. The values of the R2 and R1 resistors can also be optimized to minimize
the leakage current through the divider.
7.3.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
7.3.4 Current Limit
The device has internal current limit circuits for both MID_OUT and OUT rails. These circuits protect the
regulator during high-current load transient faults or shorting events on either rails. Both current limit circuits
are brick-wall schemes with ICL(MID_OUT) being higher than ICL(OUT). In a high-current load transient fault, the
brick-wall scheme limits the output current to the respective current limit (ICL(MID_OUT) or ICL(OUT)), both of which
are listed in the Electrical Characteristics table.
When the device is in either current limit, the output voltages are not regulated. When a current limit event
occurs, the device begins to heat up because of the increase in power dissipation. When the device is in either
current limit, the corresponding pass transistor dissipates power. For instance, when the OUT rail is in current
limit, the power dissipation can be calculated as [(VIN – VOUT) × ICL(OUT)]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the faulty output current condition continues, the device cycles between current limit and thermal shutdown with
approximately a 5-ms time constant. For more information on current limits, see the Know Your Limits application
note.
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Figure 7-4 shows a diagram of the current limit.
VOUT
Brick Wall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 7-4. Current Limit: Brick-Wall Scheme
7.3.5 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
When the thermal limit is triggered with the load current near the value of the current limit, the output can
oscillate prior to the output switching off.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
18
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7.3.6 Power Good
The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an
external pullup resistor. The maximum pullup voltage is listed as VPG in the Recommended Operating Conditions
table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than 4 V. When VOUT
exceeds VIT(PG,RISING), the PG output is high impedance and the PG pin voltage pulls up to the connected
regulated supply. When the regulated output falls below VIT(PG,FALLING), the open-drain output turns on and pulls
the PG output low after a short deglitch time. If output voltage monitoring is not needed, the PG pin can be left
floating or connected to ground.
The recommended maximum PG pin sink current (IPG-SINK) and the leakage current into the PG pin (ILKG(PG)) are
listed in the Electrical Characteristics table.
The PG pullup voltage (VPG_PULLUP), the desired minimum power-good output voltage (VPG(MIN)), and ILKG(PG)
limit the maximum PG pin pullup resistor value (RPG_PULLUP). VPG_PULLUP, the PG pin low-level output voltage
(VOL(PG)), and IPG-SINK limit the minimum RPG_PULLUP. Maximum and minimum values for RPG_PULLUP can be
calculated from the following equations:
RPG_PULLUP(MAX) = (VPG_PULLUP – VPG(MIN)) / ILKG(PG)_MAX
(2)
RPG_PULLUP(MIN) = (VPG_PULLUP – VOL(PG)) / IPG-SINK
(3)
For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from the Electrical
Characteristics table, RPG_PULLUP(MAX) is 25 MΩ. From the Electrical Characteristics table, RPG_PULLUP(MIN) is 6.6
kΩ.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING
MODE
VIN
VEN
Normal operation
VIN > VOUT(nom) + VDO and VIN >
VIN(min)
VEN > VEN(HI)
Dropout operation
on MID_OUT
VIN(min) < VIN < VMID_OUT(nom) +
VDO(MID_OUT)
VEN > VEN(HI)
Dropout operation
on OUT
VIN(min) < VIN < VOUT(nom) + VDO(OUT)
VEN > VEN(HI)
VIN < 4 V
VEN < VEN(LOW)
Disabled
(any true condition
disables the
device)
IMID_OUT
IOUT
TJ
IMID_OUT <
IMID_OUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
IMID_OUT <
IMID_OUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
IMID_OUT <
IMID_OUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Not applicable
Not applicable
TJ > TSD(reset)
7.4.2 Normal Operation
The device regulates to the nominal output voltages when the following conditions are met:
•
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage on either rails
(VMID_OUT(nom) + VDO(MID_OUT) and VOUT(nom) +VDO(OUT))
The current sourced from either MID_OUT and OUT is less than the respective current limit specified in the
Electrical Characteristics table for each rail
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD(shutdown))
The enable voltage has previously exceeded the VEN(HI) (maximum) threshold and has not yet decreased to
less than the VEN(LOW) minimum threshold
VIN has exceeded 4 V if the EN pin is left floating
7.4.3 Dropout Operation
Because the TPS7A43 has two output rails (MID_OUT and OUT), the device can be in either VDO(MID_OUT) or
VDO(OUT), or in both depending on the input voltage level while all other conditions are met for normal operation.
When the input voltage drops to lower than VMID_OUT(nom) + VDO(MID_OUT), the device is in VDO(MID_OUT) dropout.
During this rail dropout, VMID_OUT tracks VIN and the transient performance of VMID_OUT becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. The MID_OUT rail
line or load transients in the VDO(MID_OUT) dropout can result in large VMID_OUT deviations. When the device is still
in VDO(MID_OUT) and when VIN is higher than VOUT(nom) + VDO(OUT), VOUT is in regulation and is not in VDO(OUT)
dropout. When VIN drops below VOUT(nom) + V DO(OUT), V OUT is no longer in regulation and transient performance
becomes significantly degraded.
When the device is in a steady dropout state (when the device is in both VDO(MID_OUT) and VDO(OUT) dropout,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to VMID_OUT(nom) +
VDO(MID_OUT) and greater than VOUT(NOM) + VDO, the output voltage (OUT) can overshoot for a short period of
time while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The outputs of the device can be shutdown by forcing the voltage of the enable pin to less than VEN(LOW)
(minimum); see the Electrical Characteristics table. When disabled, the pass transistor is turned off and internal
circuits are shutdown.
20
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 MID_OUT Voltage Setting
The MID_OUT voltage has three different output voltage levels (10 V, 12 V, and 15 V), as listed in Table 8-1,
depending on the MVSEL1 and MVSEL2 pin voltage settings.
Table 8-1. MID_OUT Voltage Setting
SET VMVSEL1
SET VMVSEL2
MID_OUT
VMVSEL1 ≤ VMVSEL1(LOW)
VMVSEL2 ≤ VMVSEL2(LOW)
15 V
VMVSEL1 ≤ VMVSEL1(LOW)
VMVSEL2 ≥ VMVSEL2(HIGH)
12 V
VMVSEL1 ≥ VMVSEL1(HIGH)
VMVSEL2 ≤ VMVSEL2(LOW)
10 V
VMVSEL1 ≥ VMVSEL1(HIGH)
VMVSEL2 ≥ VMVSEL2(HIGH)
12 V
For adjustable voltage options of the TPS7A43, and to maintain voltage regulation on the MID_OUT and OUT
pins, the input voltage must be kept ≥ MID_OUT + VDO(MID_OUT). Additionally, to maintain regulation on the OUT
pin, the MID_OUT voltage must be set ≥ VOUT(nom) + VDO(OUT).
Set the MVSEL1 and MVSEL2 voltages before enabling the device to set the MID_OUT voltage level; however,
the MID_OUT voltage setting can be changed to a different level after the device had powered up. Do not allow
these pins to float, instead tie them both to GND if not used to set VMID_OUT. When the device is powered while
either of these pins are floating, the MID_OUT voltage is not set properly and might switch levels and cause
damage to the device.
8.1.2 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(4)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100 times the
FB pin current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider
series resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(5)
8.1.3 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
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8.1.4 Input and Output Capacitor Requirements
An input capacitor is not required for stability except when the device maximum current is sourced from the
MID_OUT pin. However, adding an input capacitor is always good analog design practice to counteract reactive
input sources and improve transient response, input ripple, and PSRR. Starting with the nominal input capacitor
value is required if large, fast transient load or line transients are anticipated on the MID_OUT pin or if the device
is located several inches from the input power source.
A minimum of a 3:1 capacitor ratio between CMID_OUT and COUT is required for proper operation of the TPS7A43
LDO and a 4.7-μF capacitor can be connected from the MID_OUT pin to GND.
A minimum 1-μF output capacitor is required for VOUT stability. A maximum 100-μF output capacitor can be used
as long as the 3:1 ratio between CMID_OUT and COUT is maintained.
8.1.5 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(6)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(7)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.6 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). As described in Equation 8 and
Equation 9, these parameters provide two methods for calculating the junction temperature (TJ). Use the
junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT)
to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB
surface temperature 1 mm from the device package (TB) to calculate the junction temperature.
22
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TJ = TT + ψJT × PD
(8)
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(9)
where:
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
8.2 Typical Application
This section discusses the implementation of the TPS7A43 in a cordless power tools application. Figure 8-1
shows a typical circuit diagram for this application.
VIN
CIN
IN
OUT
EN
NC
VOUT
VCC
COUT
R1
GND
R2
TPS7A4333
MID_OUT
MVSEL1
VIN
VMID_OUT
GND
Gate
Driver
GND
CMID_OUT
PG
MVSEL2
MCU
GND
GND
R3
VSS
GND
R4
GND
GND
Figure 8-1. Powering Cordless Power Tools
8.2.1 Design Requirements
Table 8-2 summarizes the design requirements for Figure 8-1.
Table 8-2. Design Parameters
PARAMETER
DESIGN VALUES
VIN
15 V (min), 85 V (transient max)
VOUT
3.3 V ± 2%
VMVSEL1
0V
VMVSEL2
≥ 0.9 V
VMID_OUT
12 V ± 5%
I(IN) (no load)
< 9 μA
IOUT (typical), (max)
20 mA, 50 mA
IMID_OUT (typical), (max)
0 mA, 1 mA
TA
60°C (max)
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8.2.2 Detailed Design Procedure
A fixed 3.3-V output voltage device is used for this application. The MID_OUT voltage is set to 12 V by tying
the VMVSEL1 pin to GND and setting VMVSEL2 to ≥ 0.9 V using the R3 and R4 resistor divider. The value of the
R3 and R4 divider ratio must ensure that VMVSEL2 is set to ≥ 0.9 V when VIN ≥ 15 V. To limit the current burned
through this divider to 5 μA, R3 can be calculated using Equation 10, and the calculated value then can be
rounded to the nearest standard value. When VIN goes all the way up to 85 V during a transient, the VMSEL2
voltage goes up to 3.9 V (which is still lower than the maximum recommended value for this pin, as specified in
the Recommended Operating Conditions table).
R3 = (15 V – 0.9 V) / 5 μA = 2.82 MΩ
(10)
R4 then can be calculated with Equation 11 by using the VMVSEL2 value of the same current value.
R3 = 0.9 V / 5 μA = 180 kΩ
(11)
The enable precision circuit is also used to turn off the device when VIN drops below 15 V. The R1 and R2
resistor divider is used to set VEN to lower than VEN(LOW) of 1.15 V when VIN drops below 15 V. R1 can be
calculated using Equation 12 to limit the burned current through this divider to 5 μA, similar to the above divider.
R1 = (15 V – 1.15 V) / 5 μA = 2.77 MΩ
(12)
Equation 13 can then be used to calculate R2. The calculated R1 and R2 values can then rounded to the
nearest standard values.
R2 = 1.15 V / 5 μA = 230 kΩ
(13)
8.2.3 Application Curves
150
280
100
240
50
200
0
160
-50
120
-100
80
VIN scale o
-150
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VMVSEL1 = 0 V,
VMVSEL2 = 0.9 V, IOUT = 50 mA, IMID_OUT = open
Figure 8-2. TPS7A43 Line Transient: 15 V to 85 V
24
VOUT
VIN
0
240
-5
160
-10
80
VIN scale o
40
-200
0
320
m VOUT scale
VIN
AC-Coupled VOUT (mV)
VMID_OUT
Input Voltage (V)
AC-Coupled VMID_OUT (mV)
5
320
m VOUT scale
Input Voltage (V)
200
-15
0
0
0.1
0.2
0.3
0.4 0.5 0.6
Time (ms)
0.7
0.8
0.9
1
VIN = 15 V to 85 V, VIN ramp rate = 10 V/μs, VMVSEL1 = 0 V,
VMVSEL2 = 0.9 V, IOUT = 50 mA, IMID_OUT = open
Figure 8-3. TPS7A43 Line Transient: 15 V to 85 V
(Zoom on VOUT)
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8.3 Power Supply Recommendations
The device is designed to operate from an input supply voltage range of 4 V to 85 V. To ensure that the
output voltages are well regulated and dynamic performance is optimum, the input supply must be at least
VMID_OUT(nom) + 1.5 V. Connect a low output impedance power supply directly to the input pin of the TPS7A43.
8.4 Layout
8.4.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device pins as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device and under the thermal pad to distribute heat.
Only place tented thermal vias directly beneath the thermal pad of the DGQ package. An untented via
can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a
compromised solder joint on the thermal pad.
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8.4.2 Layout Examples
CIN
COUT
OUT
IN
GND Plane
R1
OUT
1
10
IN
FB
2
9
NC
PG
3
8
MID_OUT
MVSEL2
Thermal Pad
R2
R PG
R2
PG
MVSEL1
4
7
GND
5
6
CMID_
OUT
EN
GND Plane
Routing Via
Thermal Via
Figure 8-4. Adjustable Version Layout Example
CIN
COUT
OUT
IN
GND Plane
R PG
OUT
1
10
IN
NC
2
9
NC
PG
3
8
MID_OUT
MVSEL2
Thermal Pad
MVSEL1
4
7
GND
5
6
CMID_
OUT
EN
GND Plane
Routing Via
Thermal Via
Figure 8-5. Fixed Version Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Modules
An evaluation module (EVM) for a similar P2P device, the TPS7A43, is available to assist in the initial
circuit performance evaluation for the TPS7A43. The TPS7A43EVM-047 Evaluation Module user guide can
be requested at the Texas Instruments website through the product folders or purchased directly from the TI
Store.
9.1.1.2 Spice Models
SPICE models for the TPS7A43 are available through the product folder under Tools & software.
9.1.2 Device Nomenclature
Table 9-1. Device Nomenclature(1)
PRODUCT
TPS7A43 xx(x)yyyz
(1)
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; for output voltages with a resolution of 50 mV, three
digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output
version.
yyy is the package designator.
z is the package quantity. R is for large quantity reel, T is for small quantity reel.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, TPS7A43EVM-047 Evaluation Module user guide
Texas Instruments, LDO Basics: Preventing reverse current blog
Texas Instruments, LDO basics: capacitor vs. capacitance blog
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A4301DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4301
Samples
TPS7A4333DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4333
Samples
TPS7A4350DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4350
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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