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TPS7A87
SBVS281A – MARCH 2016 – REVISED JULY 2016
TPS7A87
Dual, 500-mA, Low-Noise (3.8 μVRMS), LDO Voltage Regulator
1 Features
3 Description
•
•
•
•
•
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The TPS7A87 is a dual, low-noise (3.8 µVRMS), lowdropout (LDO) voltage regulator capable of sourcing
500 mA per channel with only 100 mV of maximum
dropout.
1
•
•
•
•
•
•
•
Two Independent LDO Channels
Low Output Noise: 3.8 µVRMS (10 Hz–100 kHz)
Low Dropout: 100 mVMAX at 0.5 A
Wide Input Voltage Range: 1.4 V to 6.5 V
Wide Output Voltage Range: 0.8 V to 5.2 V
High Power-Supply Ripple Rejection:
– 75 dB at DC
– 40 dB at 100 kHz
– 40 dB at 1 MHz
1.0% Accuracy Over Line, Load, and Temperature
Excellent Load Transient Response
Adjustable Start-Up In-Rush Control
Selectable Soft-Start Charging Current
Independent Open-Drain Power-Good (PGx)
Outputs
Stable with a 10 µF or Larger Ceramic Output
Capacitor
4-mm × 4-mm, 20-Pin WQFN Package
2 Applications
•
•
•
•
•
High-Speed Analog Circuits:
– VCOs, ADCs, DACs, LVDSs
Imaging: CMOS Sensors, Video ASICs
Test and Measurement
Instrumentation and Medical
Professional Audio
The TPS7A87 provides the flexibility of two
independent LDOs and approximately 30% smaller
solution size than two single-channel LDOs. Each
output is adjustable with external resistors from 0.8 V
to 5.2 V. The wide input-voltage range of the
TPS7A87 supports operation as low as 1.4 V and up
to 6.5 V.
With 1% output voltage accuracy (over line, load, and
temperature) and soft-start capabilities to reduce inrush current, the TPS7A87 is ideal for powering
sensitive analog low-voltage devices [such as
voltage-controlled oscillators (VCOs), analog-to-digital
converters (ADCs), digital-to-analog converters
(DACs), complementary metal oxide semiconductor
(CMOS) sensors, and video application-specific
integrated circuits (ASICs)].
The TPS7A87 is designed to power noise-sensitive
components such as those found in instrumentation,
medical, video, professional audio, test and
measurement, and high-speed communication
applications. The very low 3.8-µVRMS output noise
and wideband PSRR (40 dB at 1 MHz) minimizes
phase noise and clock jitter. These features maximize
the performance of clocking devices, ADCs, and
DACs.
Device Information(1)
PART NUMBER
Typical Application Circuit
VIN1
IN1
CIN1
TPS7A87
VOUT1
OUT1
R11
EN1
TPS7A87
FB1
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
COUT1
SS_CTRL1
Powering the Signal Chain
R21
NR/SS1
PACKAGE
WQFN (20)
CNR/SS1
ENABLE
PG1
VIN2
CIN2
VOUT2
OUT2
IN2
R12
EN2
FB2
COUT2
R22
CNR/SS2
GND
IN1
EN1
EN1
Clock
PG1
OUT1
LMK03328
LMX2581
VDD_VCO
TPS7A87
SS_CTRL2
NR/SS2
VIN1
PG2
VIN2
EN2
IN2
EN2
PG2
OUT2
VDD
SCLK
ADC
Copyright © 2016, Texas Instruments Incorporated
ENABLE
ADC3xxx
ADC3xJxx
ADC3xJBxx
ADS4xxBxx
ADS5xxx
ADS52J90
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A87
SBVS281A – MARCH 2016 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 32
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A
•
2
Page
Released to production........................................................................................................................................................... 1
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SBVS281A – MARCH 2016 – REVISED JULY 2016
5 Pin Configuration and Functions
EN1
NR/SS1
SS_CTRL1
PG1
FB1
20
19
18
17
16
RTJ Package
4-mm × 4-mm, 20-Pin WQFN
Top View
IN1
1
15
OUT1
IN1
2
14
OUT1
GND
3
13
GND
Thermal
Pad
9
10
FB2
OUT2
PG2
11
8
5
SS_CTRL2
IN2
7
OUT2
NR/SS2
12
6
4
EN2
IN2
Not to scale
Pin Functions
PIN
NAME
NO.
EN1
20
EN2
6
FB1
16
I/O
DESCRIPTION
I
Enable pin for each channel. These pins turn the regulator on and off. If VENx (1) ≥ VIH(ENx), then the regulator is enabled.
If VENx ≤ VIL(ENx), then the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used.
I
Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FBx to OUTx
(as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor
can disrupt PGx (power good) functionality. See the Feed-Forward Capacitor (CFFx) and Setting the Output Voltage
(Adjustable Operation) sections for more details.
FB2
10
GND
3, 13
—
IN1
1, 2
I
Input supply pin for LDO 1.
A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible.
IN2
4, 5
I
Input supply pin for LDO 2.
A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible.
NR/SS1
19
NR/SS2
7
Ground pin.
These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
—
Noise-reduction and soft-start pin for each channel. Connecting an external capacitor between this pin and ground
reduces reference voltage noise and also enables the soft-start function. Although not required, a 10 nF or larger
capacitor is recommended to be connected from NR/SSx to GND (as close to the pin as possible) to maximize ac
performance. See the Noise-Reduction and Soft-Start Capacitor (CNR/SSx) section for more details.
OUT1
14, 15
O
Regulated output for LDO 1. A 10-μF or larger ceramic capacitor (5 μF or greater of effective capacitance) from OUTx to
ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the
OUT1 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details.
OUT2
11, 12
O
Regulated output for LDO 2. A 10-μF or larger ceramic capacitor (5 μF or greater of effective capacitance) from OUTx to
ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the
OUT2 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details.
O
Open-drain power-good indicator pins for the LDO 1 and LDO 2 output voltages. A 10-kΩ to 100-kΩ external pullup
resistor is required. These pins can be left floating or connected to GND if not used. The use of a feed-forward capacitor
can disrupt power-good functionality. See the Feed-Forward Capacitor (CFFx) section for more details.
I
Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of the
NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot.
PG1
17
PG2
9
SS_CTRL1
18
SS_CTRL2
8
Thermal pad
(1)
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range and all voltages with respect to GND (unless otherwise noted) (1)
Voltage
7.0
INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs)
–0.3
7.5
OUTx
–0.3
VINx + 0.3 (3)
SS_CTRLx
–0.3
VINx + 0.3 (3)
NR/SSx, FBx (2)
–0.3
3.6
UNIT
V
Internally limited
PGx (sink current into device) (2)
Temperature
(2)
(3)
MAX
–0.3
OUTx (2)
Current
(1)
MIN
INx, PGx, ENx (2)
A
5
mA
Operating junction, TJ
–55
150
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
The absolute maximum rating is VINx + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
1.4
6.5
UNIT
V
0.8 – 1%
5.2 + 1%
V
0
500
VINx
Input supply voltage range
VOUTx
Output voltage range
IOUTx
Output current
CINx
Input capacitor, each input
10
µF
COUTx
Output capacitor
10
µF
CNR/SSx
Noise-reduction capacitor
RPGx
Power-good pullup resistance
TJ
Junction temperature range
mA
1
µF
10
100
kΩ
–40
125
°C
6.4 Thermal Information
TPS7A87
THERMAL METRIC (1)
RTJ (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
33
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.8
°C/W
RθJB
Junction-to-board thermal resistance
8.0
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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SBVS281A – MARCH 2016 – REVISED JULY 2016
6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VINx = 1.4 V or VOUTx(TARGET) + 0.2 V (whichever is greater),
VOUTx(TARGET) = 0.8 V, IOUTx = 50 mA, VENx = 1.4 V, COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, SS_CTRLx = GND, PGx pin
pulled up to VINx with 100 kΩ, and for each channel (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
VINx
(1)
TEST CONDITIONS
Input supply voltage range
MIN
TYP
1.4
Reference voltage
VUVLOx
Input supply UVLOx
VINx rising
1.31
VUVLOx(HYS)
VUVLOx hysteresis
VINx falling hysteresis
290
VOUTx
Output voltage range
V
0.8
VOUTx accuracy (2)
0.8 V ≤ VOUTx ≤ 5.2 V, 5 mA ≤ IOUTx ≤ 0.5 A
ΔVOUTx(ΔVINx)
Line regulation
IOUTx = 5 mA, 1.4 V ≤ VINx ≤ 6.5 V
ΔVOUTx(ΔIOUTx)
Load regulation
5 mA ≤ IOUTx ≤ 0.5 A
VDO
Dropout voltage
1.4 V ≤ VINx ≤ 5.3 V
IOUTx = 0.5 A, VFBx = 0.8 V – 3%
ILIM
Output current limit
VOUTx forced at 0.9 × VOUTx(TARGET),
GND pin current
UNIT
6.5
VREF
IGND
MAX
V
1.39
0.8 – 1%
5.2 + 1%
–1.0%
1.0%
0.8
Both channels enabled, per channel,
VINx = 6.5 V, IOUTx = 5 mA
Shutdown GND pin current
Both channels shutdown, per channel, PGx = (open),
VINx = 6.5 V, VENx = 0.4 V
IENx
ENx pin current
VINx = 6.5 V, 0 V ≤ VENx ≤ 6.5 V
VIL(ENx)
ENx pin low-level input voltage
(device disabled)
VIH(ENx)
ENx pin high-level input voltage
(device enabled)
ISS_CTRLx
SS_CTRLx pin current
VIT(PGx)
V
0.003
%/V
0.03
%/A
100
mV
1.1
1.5
A
2.1
3.5
mA
Both channels enabled, per channel,
VINx = 1.4 V, IOUTx = 0.5 A
ISDN
V
mV
4
15
μA
–0.2
0.2
μA
0
0.4
V
1.1
6.5
V
VINx = 6.5 V, 0 V ≤ VSS_CTRLx ≤ 6.5 V
–0.2
0.2
μA
PGx pin threshold
For PGx transitioning low with falling VOUTx,
expressed as a percentage of VOUTx(TARGET)
82%
Vhys(PGx)
PGx pin hysteresis
For PGx transitioning high with rising VOUTx,
expressed as a percentage of VOUTx(TARGET)
VOL(PGx)
PGx pin low-level output voltage
VOUTx < VIT(PGx), IPGx = –1 mA (current into device)
Ilkg(PGx)
PGx pin leakage current
VOUTx > VIT(PGx), VPGx = 6.5 V
INR/SSx
NR/SSx pin charging current
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V,
VSS_CTRLx = GND
4.0
6.2
9.0
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V, VSS_CTRLx = VINx
65
100
150
IFBx
0.1
88.9%
93%
1%
V
1
µA
µA
FBx pin leakage current
VINx = 6.5 V, VFBx = 0.8 V
PSRR
Power-supply rejection ratio
f = 500 kHz, VINx = 3.8 V, VOUTx = 3.3 V,
IOUTx = 250 mA, CNR/SSx = 10 nF, CFFx = 10 nF
40
dB
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 1 µF, CFFx = 100 nF
3.8
μVRMS
Noise spectral density
f = 10 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 10 nF, CFFx = 10 nF
11
nV/√Hz
Rdiss
Output active discharge
resistance
VENx = GND
250
Ω
Tsdx
Thermal shutdown temperature
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
(1)
(2)
–100
0.4
100
nA
°C
Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2.
When the device is connected to external feedback resistors at the FBx pins, external resistor tolerances are not included.
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6.6 Typical Characteristics
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
100
CNR/SS = 10 nF, CFF = 10 nF, COUT = 10 PF
CNR/SS = 0 nF, CFF = 0 nF, COUT = 10 PF
CNR/SS = 1000 nF, CFF = 1000 nF, COUT = 10 PF
80
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
80
60
40
20
0
10
10M
IOUTx = 500 mA, VINx = 5.3 V
VINx = 1.7 V
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
VINx = 1.55 V
VINx = 1.6 V
VINx = 1.65 V
40
20
100
1k
10k
100k
Frequency (Hz)
1M
80
10M
IOUTx = 10 mA
IOUTx = 50 mA
IOUTx = 100 mA
IOUTx = 250 mA
IOUTx = 500 mA
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTx = 1.2 V, VINx = 1.4 V, VENx = 3.8 V, IOUTx = 500 mA,
COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
Figure 3. Power-Supply Rejection Ratio vs
Frequency and Input Voltage
Figure 4. Power-Supply Rejection Ratio vs
Frequency and Output Current
110
100
COUTx = 10 PF
COUTx = 100 PF
COUTx = 200 PF
COUTx = 500 PF
COUTx = 500 PF || 1 mF OSCON
80
60
40
20
100
90
Channel Isolation (dB)
Power-Supply Rejection Ratio (dB)
1M
60
10M
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
80
70
60
50
40
30
20
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUTx = 5.0 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = ceramic, CFFx = 10 nF
Figure 5. Power-Supply Rejection Ratio vs
Frequency and Output Capacitance
6
10k
100k
Frequency (Hz)
100
VINx = 1.4 V
VINx = 1.45 V
VINx = 1.5 V
60
0
10
1k
Figure 2. Power-Supply Rejection Ratio vs
Frequency and CNR/SSx
100
0
10
100
VOUTx = 5 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = 10 µF, CFFx = 10 nF
Figure 1. Power-Supply Rejection Ratio at VOUTx = 5.0 V
80
CNR/SSx = 10 nF
CNR/SSx = 0 nF
CNR/SSx = 100 nF
CNR/SSx = 1000 nF
0
1E+1
VOUT1 to VOUT2
VOUT2 to VOUT1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
VOUTx = 1.8 V, IOUTx = 100 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
Figure 6. Channel-to-Channel Output Voltage Isolation vs
Frequency
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
50
CFFx = 10 nF, CNR/SSx = 10 nF
CFFx = 100 nF, CNR/SSx = 1 PF
Output Voltage Noise (PV/—Hz)
Output Votlage Noise (PVRMS)
14
12
10
8
6
Nominal Noise Figure
CNR/SSx = 1 PF, CFFx = 100 nF
CNR/SSx = 1 PF, CFFx = 100 nF, SS_CTRLx = GND
CNR/SSx = 10 nF, CFFx = 10 nF, COUTx = 22 PF||1 mF
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.0005
10
4
0.8
1.6
2.4
3.2
4
Output Voltage (V)
4.8
100
5.6
10k
Frequency
100k
Figure 7. Output Noise vs Output Voltage
10
VOUTx = 0.8 V, 3.94 PVRMS
VOUTx = 1.2 V, 4.31 PVRMS
VOUTx = 1.8 V, 5.1 PVRMS
VOUTx = 2.5 V, 6.03 PVRMS
VOUTx = 3.3 V, 7.43 PVRMS
VOUTx = 5.0 V, 10.3 PVRMS
CNR/SSx = None, 11.43 PVRMS
CNR/SSx = 0.01 PF, 4.94 PVRMS
CNR/SSx = 0.1 PF, 4.24 PVRMS
CNR/SSx = 1.0 PF, 4.22 PVRMS
1
Noise (PV/—Hz)
1
0.1
0.01
0.1
0.01
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
0.001
1E+1
1E+7
VINx = VOUTx + 1.0 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100
kHz, COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
VINx = 1.7 V, VOUTx = 1.2 V, IOUTx = 500 mA, VRMS BW = 10 Hz to
100 kHz, COUTx = 10 µF, CFFx = 10 nF
Figure 9. Noise vs Frequency and Output Voltage
Figure 10. Noise vs Frequency and CNR/SSx
10
10
CFFx = 0 PF
CFFx = 0.01 PF
CFFx = 0.1 PF
VINx = 1.5 V
VINx = 1.8 V
VINx = 2.5 V
VINx = 3.3 V
1
Noise (PV/—Hz)
1
Noise (PV/—Hz)
10M
Figure 8. Output Noise at VOUTx = 5 V
10
0.1
0.01
0.001
1E+1
1M
IOUTx = 500 mA
IOUTx = 500 mA
Noise (PV/—Hz)
1k
0.1
0.01
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 500 mA, VRMS BW = 10 Hz to
100 kHz, COUTx = 10 µF, CNR/SSx = 10 nF
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF, CNR/SSx = 10 nF
Figure 11. Noise vs Frequency and CFFx
Figure 12. Noise vs Frequency and VINx
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
10
12
RMS Output Noise (PVRMS)
COUTx = 10 PF, 4.94 PVRMS
COUTx = 22 PF, 5.05 PVRMS
COUTx = 100 PF, 5.66 PVRMS
0.1
0.01
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
10
8
6
4
2
0
1E-6
1E+7
VOUTx = 1.8 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz,
CFFx = 0.01 µF
1E-5 0.0001 0.001
0.01
0.1
1
Noise Reduction Capacitor [CNR/SSx] (PF)
VOUTx = 1.8 V, IOUTx = 500 mA, CFFx = 0.01 µF,
BW = 10 Hz to 100 kHz
Figure 13. Noise vs Frequency and COUTx
Figure 14. RMS Output Noise vs CNR/SSx
50
AC-Coupled Output Voltage (mV)
RMS Output Noise (PVRMS)
12
10
8
6
4
2
0
1E-6
2
VOUTx = 5.0 V
VOUTx = 3.3 V
VOUTx = 1.2 V
VOUTx = 0.9 V
IOUTx
25
1.5
0
1
-25
0.5
-50
1E-5
0.0001
0.001
0.01
Feed-Forward Capacitor [CFFx] (PF)
10
0.1
VOUTx = 1.8 V, IOUTx = 500 mA, CNR/SSx = 1 µF,
BW = 10 Hz to 100 kHz
Output Current (A)
Noise (PV/—Hz)
1
0
200
400
600
Time (Ps)
800
0
1000
VINx = VOUTx + 0.3 V, IOUTx = 10 mA to 500 mA, COUTx = 10 µF,
CFFx = CNR/SSx = 10 nF
Figure 16. Load Transient Response vs VOUTx
Figure 15. RMS Output Noise vs CFFx
AC-Coupled Output Votlage (mV)
50
IOUTx = 1 mA to 500 mA
IOUTx = 10 mA to 500 mA
IOUTx = 50 mA to 500 mA
IOUTx = 100 mA to 500 mA
25
VINx
2 V/div
0
VOUTx
20 mV/div
-25
VPGx
1 V/div
-50
0
200
400
600
Time (Ps)
800
1000
VINx = 5.3 V, COUTx = 10 µF, CFFx = CNR/SSx = 10 nF
Time (200 Ps/div)
VINx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUTx = 0.8 V,
IOUTx = 500 mA, CNR/SSx = CFFx = 10 nF
Figure 17. Load Transient Response vs DC Load
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
1.25
Output Current (A)
1.2
VENx
1 V/div
1.15
VOUTx
200 mV/div
VPGx
200mV/div
1.1
1.05
1
0.95
-40qC
0qC
25qC
85qC
125qC
0.9
0
0.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
Time (50 Ps/div)
VINx = 3.4 V, VOUTx = 3.3 V, 125°C curve truncated because of
device entering thermal shutdown
VINx = 1.4 V
Figure 20. Start-Up (SS_CTRLx = GND, CNR/SSx = 0 nF)
Figure 19. Current Limit Foldback
VEN1
1 V/div
VEN1
1 V/div
VOUT1
200 mV/div
VOUT1
200 mV/div
VPG1
200 mV/div
VPG1
200 mV/div
Time (500 Ps/div)
Time (50 Ps/div)
VINx = 1.4 V
VINx = 1.4 V
Figure 22. Start-Up (SS_CTRLx = VINx, CNR/SSx = 10 nF)
Figure 21. Start-Up (SS_CTRLx = GND, CNR/SSx = 10 nF)
80
VOUT1
200 mV/div
Dropout Voltage (mV)
VEN1
1 V/div
VINx = 1.4 V
VINx = 1.8 V
VINx = 3.6 V
VPG1
200 mV/div
VINx = 4.8 V
VINx = 5.6 V
VINx = 5.8 V
60
40
20
0
0
Time (2 ms/div)
0.1
VINx = 1.4 V
Figure 23. Start-Up (SS_CTRLx = VINx, CNR/SSx = 1 µF)
0.2
0.3
Output Current (A)
0.4
0.5
Figure 24. Dropout Voltage vs Output Current
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
90
0.05
-40qC
0qC
85
25qC
85qC
125qC
Change in Output Voltage (%)
Dropout Voltage (mV)
80
75
70
65
60
55
50
45
40
0.025
0
-0.025
-40qC
0qC
25qC
85qC
125qC
-0.05
35
30
-0.075
1
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
IOUTx = 500 mA
Figure 25. Dropout Voltage vs Input Voltage
Figure 26. Load Regulation (VOUTx = 1.2 V)
0.045
-40qC
0qC
25qC
85qC
125qC
0.25
Change in Output Voltage (%)
Output Voltage Accuracy (%)
0.5
0
-0.25
-40qC
0qC
25qC
85qC
125qC
0.03
0.015
0
-0.015
-0.03
-0.5
1
1.5
2
2.5
3 3.5
4 4.5
Input Voltage (V)
5
5.5
6
0
6.5
0.1
IOUTx = 50 mA
Figure 27. Line Regulation (VOUTx = 0.8 V)
0.5
Figure 28. Load Regulation (VOUTx = 3.3 V)
0.06
-40qC
0qC
25qC
85qC
125qC
0.25
Change in Output Voltage (%)
Output Voltage Accuracy (%)
0.4
VINx = 3.8 V
0.5
0
-0.25
0.03
0
-0.03
-40qC
0qC
25qC
85qC
125qC
-0.06
-0.09
-0.5
3
3.5
4
4.5
5
Input Voltage (V)
5.5
6
6.5
0
0.1
IOUTx = 5 mA
0.2
0.3
Output Current (A)
0.4
0.5
VINx = 5.5 V
Figure 29. Line Regulation (VOUTx = 3.3 V)
10
0.2
0.3
Output Current (A)
Figure 30. Load Regulation (VOUTx = 5.0 V)
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
5
Shutdown Current (PA)
4
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
Ground Pin Current (mA)
-40qC
0qC
25qC
85qC
125qC
3
2
1
0
1
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
6.5
-40qC
0
0.1
0.15
D001
25qC
85qC
0.2 0.25 0.3 0.35
Output Current (A)
125qC
0.4
0.45
0.5
VINx = 1.4 V, both channels enabled
Both channels
Figure 32. Ground Current vs Output Current
Figure 31. Shutdown Current vs Input Voltage
5
500
-40qC
0qC
25qC
85qC
125qC
-40qC
0qC
25qC
85qC
125qC
400
PG Voltage (mV)
4.5
GND Current (mA)
0.05
0qC
4
300
200
3.5
100
3
0.5
0
1
1.5
2
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
6.5
0
0.5
D001
1
1.5
2
PG Current (mA)
2.5
3
Both channels enabled
Figure 34. PGx Low Level vs PGx Current (VINx = 1.4 V)
Figure 33. Ground Current vs Input Voltage
90
500
-40qC
0qC
25qC
85qC
125qC
89.7
%VOUTx(TARGET)
PG Voltage (mV)
400
300
200
100
89.4
89.1
VINx = 1.4 V, Falling Threshold
VINx = 1.4 V, Rising Threshold
VINx = 6.5 V, Falling Threshold
VINx = 6.5 V, Rising Threshold
88.8
0
0
0.5
1
1.5
2
PG Current (mA)
2.5
3
88.5
-40
Figure 35. PGx Low Level vs PGx Current (VINx = 6.5 V)
0
40
80
Temperature (qC)
120
160
Figure 36. PGx Threshold vs Temperature
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Typical Characteristics (continued)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
200
0.03
100
70
50
0.02
INR/SSx
Current (PA)
0.025
0.015
0.01
30
20
10
7
5
VNx = 1.4 V, SS_CTRLx = GND
VNx = 1.4 V, SS_CTRLx = VINx
VNx = 6.5 V, SS_CTRLx = GND
VNx = 6.5 V, SS_CTRLx = VINx
3
2
0.005
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
1
-40
110 125
0
40
80
Temperature (qC)
120
160
VINx = VPGx = 6.5 V
Figure 37. PGx Leakage Current vs Temperature
Figure 38. Soft-Start Current vs Temperature
(SS_CTRLx = GND)
1.4
1
VINx = 1.4 V, Falling Threshold
VINx = 1.4 V, Rising Threshold
VINx = 6.5 V, Falling Threshold
VINx = 6.5 V, Rising Threshold
0.8
0.7
Rising Threshold
Falling Threshold
1.3
Input Voltage (V)
Enable Threshold (V)
0.9
1.35
1.25
1.2
1.15
1.1
1.05
1
0.6
0.95
0.5
-40
0
40
80
Temperature (qC)
120
160
Figure 39. Enable Threshold vs Temperature
12
0.9
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
Figure 40. Input UVLOx Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A87 is a monolithic, dual-channel, low-dropout (LDO) regulator, and each channel is low-noise, highPSRR, and capable of sourcing a 500-mA load with only 100 mV of maximum dropout. These features make the
device a robust solution to solve many challenging problems in generating a clean, accurate power supply.
The various features for each of the TPS7A87 fully independent LDOs simplify using the device in a variety of
applications. As detailed in the Functional Block Diagram section, these features are organized into three
categories, as shown in Table 1.
Table 1. Features
VOLTAGE REGULATION
SYSTEM START-UP
INTERNAL PROTECTION
High accuracy
Programmable soft-start
Foldback current limit
Low-noise, high-PSRR output
Sequencing controls
Fast transient response
Power-good output
Thermal shutdown
7.2 Functional Block Diagram
Curren t
Limit
IN1
OUT1
Charge
Pump
Acti ve
Discha rge
0.8-V
VREF
SS_CTRL1
+
Erro r
Amp
±
Softstart
Control
INR/SSx
NR/SS1
FB1
±
UVLO
0.89 x V REF
Inte rnal
Ena ble
Control
+
PG1
Thermal
Shu tdo wn
EN1
Curren t
Limit
IN2
OUT2
Charge
Pump
Acti ve
Discha rge
0.8-V
VREF
SS_CTRL2
Softstart
Control
+
Erro r
Amp
±
INR/SSx
NR/SS2
FB2
±
UVLO
Inte rnal
Ena ble
Control
0.89 x V REF
+
PG2
Thermal
Shu tdo wn
EN2
GND
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7.3 Feature Description
7.3.1 Voltage Regulation Features
7.3.1.1 DC Regulation
An LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (VREF), as
shown in Figure 41. VREF is designed to have a very low-bandwidth at the input to the error amplifier through the
use of a low-pass filter (VNR/SSx).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes
from the combination of the output capacitor and pass element. The pass element also presents a high input
impedance to the source voltage when operating as a current source. A positive LDO can only source current
because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision bandgap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation
required by the device to regulate the output voltage at a given current level, thereby improving system
efficiency. Combined, these features help make this device a good approximation of an ideal voltage source.
This device replaces two stand-alone power-supplies, and also provides load-to-load isolation. The LDOs can
also be put in series (cascaded) to achieve even higher PSRR by connecting the output of one channel to the
input of the other channel.
VINx
To Load
±
+
R1
VREF
R2
GND
NOTE: VOUTx = VREF × (1 + R1x / R2x).
Figure 41. Simplified Regulation Circuit
7.3.1.2 AC and Transient Response
Each LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the
output current (load transient) resulting from the LDO high-input impedance and low output-impedance across
frequency. This same capability also means that each LDO has a high power-supply rejection-ratio (PSRR) and,
when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (smallsignal) and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other
channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The choice of external component values optimizes the small- and large-signal response. The NR/SSx capacitor
(CNR/SSx) and feed-forward capacitor (CFFx) easily reduce the device noise floor and improve PSRR; see the
Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.
7.3.2 System Start-Up Features
In many different applications, the power-supply output must turn-on within a specific window of time to either
ensure proper operation of the load or to minimize the loading on the input supply or other sequencing
requirements. Each LDO start-up is well-controlled and user-adjustable, solving the demanding requirements
faced by many power-supply design engineers in a simple fashion.
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Feature Description (continued)
7.3.2.1 Programmable Soft-Start (NR/SSx)
Soft-start directly controls the output start-up time and indirectly controls the output current during start-up (inrush current).
The external capacitor at the NR/SSx pin (CNR/SSx) sets the output start-up time by setting the rise time of the
internal reference (VNR/SSx), as shown in Figure 42. SS_CTRLx provides additional control over the rise time of
the internal reference by enabling control over the charging current (INR/SSx) for CNR/SSx. The voltage at the
SS_CTRLx pin (VSS_CTRLx) must be connected to ground (GND) or VINx.
Note that if CNR/SSx = 0 nF and the SS_CTRLx pin is connected to VINx, then the output voltage overshoots during
start-up.
SW
INR/SSx
RNRx
NR/SSx Control
VREF
+
CNR/SSx
VFBx
±
GND
Figure 42. Simplified Soft-Start Circuit
7.3.2.2 Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of
the high power levels inherent in a PDN, and the variations between all of the supplies. Control of each channel
turn-on and turn-off time is set by the specific channel enable circuit (ENx) and undervoltage lockout circuit
(UVLOx), as shown in Figure 43 and Table 2.
ENx
Internal Enable
Control
UVLOx
Figure 43. Simplified Turn-On Control
Table 2. Sequencing Functionality Table
INPUT VOLTAGE
VINx ≥ VUVLOx
VINx < VUVLOx – VHYS
(1)
ENABLE STATUS
LDO
STATUS
ACTIVE
DISCHARGE
POWER-GOOD
ENx = 1
On
Off
PGx = 1 when VOUTx ≥ VIT(PGx)
ENx = 0
Off
On
PGx = 0
ENx = don't care
Off
On (1)
PGx = 0
The active discharge remains on as long as VINx provides enough headroom for the discharge circuit to function.
7.3.2.2.1 Enable (ENx)
The enable signal (VENx) is an active-high digital control that enables the LDO when the enable voltage is past
the rising threshold (VENx ≥ VIH(ENx)) and disables the LDO when the enable voltage is below the falling threshold
(VENx ≤ VIL(ENx)). The exact enable threshold is between VIH(ENx) and VIL(ENx) because ENx is a digital control. In
applications that do not use the enable control, connect ENx to VINx.
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7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit responds quickly to glitches on VINx and attempts to disable the output of the device if either
of these rails collapse.
As a result of the fast response time of the input supply UVLOx circuit, fast and short line transients well below
the input supply UVLOx falling threshold (brownouts) can cause momentary glitches during the edges of the
transient. These glitches are typical in most LDOs and, in most applications, the brownouts required for these
glitches do not result from the local input capacitance; see the Undervoltage Lockout (UVLOx) Control section for
more details.
7.3.2.2.3 Active Discharge
When either ENx or UVLOx is low, the device connects a resistor of several hundred ohms from VOUTx to GND,
discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUTx > VINx,
which can cause damage to the device (when VOUTx > VINx + 0.3 V); see the Reverse Current Protection section
for more details.
7.3.2.3 Power-Good Output (PGx)
The PGx signal provides an easy solution to meet demanding sequencing requirements because PGx signals
when the output nears its nominal value. PGx can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUTx(Target)). A simplified schematic is shown in Figure 44.
The PGx signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active
high. The power-good circuit sets the PGx pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFFx) delays the output voltage and, because the power-good circuit
monitors the FBx pin, the PGx signal can indicate a false positive. A simple solution to this scenario is to use an
external voltage detector device, such as the TPS3780; see the Feed-Forward Capacitor (CFFx) section for more
information.
VPGx
VBG
VINx
VFBx
±
+
GND
ENx UVLOx
GND
GND
Figure 44. Simplified PGx Circuit
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7.3.3 Internal Protection Features
In many applications, fault events can occur that damage devices in the system. Short-circuits and excessive
heat are the most common fault events for power supplies. The TPS7A87 implements circuitry for each LDO to
protect the device and its load during these events. Continuously operating in these fault conditions or above a
junction temperature of 125°C is not recommended because the long-term reliability of the device is reduced.
7.3.3.1 Foldback Current Limit (ICLx)
The internal current limit circuit protects the LDO against short-circuit and excessive load current conditions. The
output current decreases (folds back) when the output voltage falls to better protect the device, as described in
Figure 19. Each channel features its own independent current limit circuit.
7.3.3.2 Thermal Protection (Tsdx)
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current
limit or high ambient temperature. Each channel features its own independent thermal shutdown circuit.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal
shutdown temperature (Tsdx). The output turns on again after TJ decreases below the falling thermal shutdown
temperature (Tsdx).
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be
greater than or equal to Tsdx, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can
cycle on and off when thermal shutdown is reached under these conditions.
7.4 Device Functional Modes
Table 3 provides a quick comparison between the regulation and disabled operation.
Table 3. Device Functional Modes Comparison
OPERATING MODE
Regulation
(1)
Disabled (2)
(1)
(2)
PARAMETER
VINx
ENx
IOUTx
TJ
VINx > VOUTx(nom) + VDO
VENx > VIH(ENx)
IOUTx < ICLx
TJ < Tsd
VINx < VUVLOx
VENx < VIL(ENx)
—
TJ > Tsd
All table conditions must be met.
The device is disabled when any condition is met.
7.4.1 Regulation
The device regulates the output to the targeted output voltage when all the conditions in Table 3 are met.
7.4.2 Disabled
When disabled, the pass device is turned off, the internal circuits are shutdown, and the output voltage is actively
discharged to ground by an internal resistor from the output to ground.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 External Component Selection
8.1.1.1 Setting the Output Voltage (Adjustable Operation)
Each LDO resistor feedback network sets the output voltage, as shown in Figure 45, with an output voltage
range of 0.8 V to 5.2 V.
VIN1
IN1
CIN1
TPS7A87
VOUT1
OUT1
R11
EN1
FB1
COUT1
SS_CTRL1
R21
NR/SS1
CNR/SS1
PG1
VIN2
VOUT2
OUT2
IN2
CIN2
R12
EN2
FB2
COUT2
SS_CTRL2
R22
NR/SS2
CNR/SS2
GND
PG2
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Figure 45. Adjustable Operation
Equation 1 relates the values R1x and R2x to VOUTx(Target) and VFBx. Equation 1 is a rearranged version of
Equation 2, simplifying the feedback resistor calculation. The current through the feedback network must be
equal to or greater than 5 μA for optimum noise performance and accuracy, as shown in Equation 3.
VOUTx = VFBx × (1 + R1x / R2x)
R1x = (VOUTx / VFBx – 1) × R2x
R2x < VREF / 5 µA
(1)
(2)
(3)
The input bias current into the error amplifier (feedback pin current, IFBx) and tighter tolerance resistors must be
taken into account for optimizing the output voltage accuracy.
18
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Application Information (continued)
Table 4 shows the resistor combinations for several common output voltages using commercially-available, 1%
tolerance resistors.
Table 4. Recommended Feedback-Resistor Values
(1)
FEEDBACK RESISTOR VALUES (1)
TARGETED OUTPUT
VOLTAGE (V)
R1x (kΩ)
R2x (kΩ)
CALCULATED OUTPUT
VOLTAGE (V)
0.80
Short
Open
0.800
0.90
1.37
11.0
0.900
0.95
1.91
10.2
0.950
1.00
2.55
10.2
1.000
1.05
3.32
10.7
1.048
1.10
3.57
9.53
1.100
1.15
4.64
10.7
1.147
1.20
5.49
11.0
1.199
1.35
6.98
10.2
1.347
1.50
9.31
10.7
1.496
1.80
13.70
11.0
1.796
1.90
14.70
10.7
1.899
2.50
22.60
10.7
2.490
2.85
27.40
10.7
2.849
3.00
29.40
10.7
2.998
3.30
33.20
10.7
3.282
3.60
35.70
10.2
3.600
4.50
44.20
9.53
4.510
5.00
56.20
10.7
5.002
5.20
53.60
9.76
5.193
R1x is connected from OUTx to FBx; R2x is connected from FBx to GND; see Figure 45.
8.1.1.2 Capacitor Recommendations
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output pins. Multilayer ceramic capacitors have become the industry standard for these types of applications
and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for an effective capacitance derating of approximately 50%, but at higher VINx and
VOUTx conditions (that is, VINx = 5.5 V to VOUTx = 5.0 V) the derating can be greater than 50% and must be taken
into consideration.
8.1.1.3 Input and Output Capacitor (CINx and COUTx)
The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (5 µF or
greater of effective capacitance) at each input and output. Locate the input and output capacitors as near as
practical to the respective input and output pins to minimize the trace inductance from the capacitor to the
device.
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8.1.1.4 Feed-Forward Capacitor (CFFx)
Although a feed-forward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a
10-nF external CFFx optimizes the transient, noise, and PSRR performance. A higher capacitance CFFx can be
used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output
voltage is settled. The maximum recommended value is 100 nF.
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the
time constant from CFFx. For a detailed description, see the Pros and Cons of Using a Feed-Forward Capacitor
with a Low Dropout Regulator application report (SBVA042).
8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
Although a noise-reduction and soft-start capacitor (CNR/SSx) from the NR/SSx pin to GND is not required, CNR/SSx
is highly recommended to control the start-up time and reduce the noise-floor of the device. The typical value
used is 10 nF, and the maximum recommended value is 10 µF.
8.1.2 Start-Up
8.1.2.1 Circuit Soft-Start Control (NR/SSx)
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an
external capacitor (CNR/SSx). This soft-start eliminates power-up initialization problems when powering fieldprogrammable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to
the input power bus.
The output voltage (VOUTx) rises proportionally to VNR/SSx during start-up as the LDO regulates so that the
feedback voltage equals the NR/SSx voltage (VFBx = VNR/SSx). As such, the time required for VNR/SSx to reach its
nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SSx), the soft-start capacitance (CNR/SSx),
and the internal reference (VREF). The approximate soft-start ramp time (tSSx) can be calculated with Equation 4:
tSSx = (VREF × CNR/SSx) / INR/SSx
(4)
The SS_CTRLx pin for each output sets the value of the internal current source, maintaining a fast start-up time
even with a large CNR/SSx capacitor. When the SS_CTRLx pin is connected to GND, the typical value for the
INR/SSx current is 6.2 µA. Connecting the SS_CTRLx pin to INx increases the typical soft-start charging current to
100 µA. The larger charging current for INR/SSx is useful when smaller start-up ramp times are needed or when
using larger noise-reduction capacitors.
Not using a noise-reduction capacitor on the NR/SSx pin and tying the SS_CTRLx pin to VINx results in output
voltage overshoot of approximately 10%. Connecting the SS_CTRLx pin to GND or using a capacitor on the
NR/SSx pin minimizes the overshoot.
Values for the soft-start charging currents are provided in the Electrical Characteristics table.
8.1.2.1.1 In-Rush Current
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, this soft-start
current can be estimated by Equation 5:
VOUTx(t)
COUTx ´ dVOUTx(t)
IOUTx(t) =
+
RLOAD
dt
where:
•
•
•
20
VOUTx(t) is the instantaneous output voltage of the turn-on ramp
dVOUTx(t) / dt is the slope of the VOUTx ramp
RLOAD is the resistive load impedance
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8.1.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum
operational voltage range, and ensures that the device properly shuts down when the input supply collapses.
Figure 46 and Table 5 explain the UVLOx circuit response to various input voltage events, assuming VENx ≥
VIH(ENx).
UVLOx Rising Threshold
UVLOx Hysteresis
VINx
C
VOUTx
tAt
tBt
tDt
tEt
tFt
tGt
Figure 46. Typical UVLOx Operation
Table 5. Typical UVLOx Operation Description
REGION
EVENT
VOUTx STATUS
A
Turn-on, VINx ≥ VUVLOx
0
Start-up
COMMENT
B
Regulation
1
Regulates to target VOUTx
C
Brownout, VINx ≥ VUVLOx – VHYS
1
The output can fall out of regulation but the device is still enabled.
D
Regulation
1
Regulates to target VOUTx
E
Brownout, VINx < VUVLOx – VHYS
0
The device is disabled and the output falls because of the load and
active discharge circuit. The device is reenabled when the UVLOx
rising threshold is reached by the input voltage and a normal startup then follows.
F
Regulation
1
Regulates to target VOUTx
G
Turn-off, VINx < VUVLOx – VHYS
0
The output falls because of the load and active discharge circuit.
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During
this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time;
however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of
the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs
are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall
time of the input supply when operating near the minimum VINx.
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8.1.2.3 Power-Good (PGx) Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The
power-good circuit asserts whenever FBx, VINx, or ENx are below their thresholds. The PGx operation versus the
output voltage is shown in Figure 47, which is described by Table 6.
PGx Rising Threshold
PGx Falling Threshold
VOUTx
E
C
PGx
tAt
tBt
tDt
tFt
tGt
Figure 47. Typical PGx Operation
Table 6. Typical PGx Operation Description
REGION
EVENT
PGx STATUS
FBx VOLTAGE
VFBx < VIT(PGx) + VHYS(PGx)
A
Turn-on
0
B
Regulation
Hi-Z
C
Output voltage dip
Hi-Z
D
Regulation
Hi-Z
E
Output voltage dip
0
VFBx < VIT(PGx)
F
Regulation
Hi-Z
VFBx ≥ VIT(PGx)
G
Turn-off
0
VFBx < VIT(PGx)
VFBx ≥ VIT(PGx)
The PGx pin is open-drain and connecting a pullup resistor to an external supply enables others devices to
receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply
voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and
100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and
the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor
is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFFx with a small CNR/SSx causes the power-good signal to incorrectly indicate that the output
voltage has settled during turn-on. The CFFx time constant must be greater than the soft-start time constant to
ensure proper operation of the PGx during start-up. For a detailed description, see the Pros and Cons of Using a
Feed-Forward Capacitor with a Low Dropout Regulator application report (SBVA042).
The state of PGx is only valid when the device operates above the minimum supply voltage. During short
brownout events and at light loads, power-good does not assert because the output voltage (therefore VFBx) is
sustained by the output capacitance.
8.1.3 AC and Transient Performance
LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output
isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop
gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The
output noise is primarily a result of the reference and error amplifier noise.
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Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency
spectrum (usually 10 Hz to 10 MHz). Equation 6 gives the PSRR calculation as a function of frequency for the
input signal [VINx(f)] and output signal [VOUTx(f)].
§ V (f ) ·
PSRR (dB) 20 Log10 ¨ INx
¸
© VOUTx (f ) ¹
(6)
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for
convenience.
A simplified diagram of PSRR versus frequency is shown in Figure 48.
Power-Supply Rejection Ratio (dB)
PSRR Boost Circuit Improves PSRR in This Region
Band Gap
Band-Gap
RC Filter
Error Amplifier,
Flat-Gain Region
Error Amplifier,
Gain Roll-Off
Output Capacitor
|ZCOUTx| Decreasing
Output Capacitor
|ZCOUTx| Increasing
10 Hz±1 MHz
Sub 10 Hz
100 kHz +
Frequency (Hz)
Figure 48. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply
voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for
the TPS7A87.
The TPS7A87 features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz; see Figure 4. To
achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the
100-kHz to 1-MHz band is recommended.
8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting
the other output. This attenuation appears in load transient tests on the other output; however, to numerically
quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See the Layout section on how to best
optimize the isolation performance.
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8.1.3.3 Output Voltage Noise
The TPS7A87 is designed for system applications where minimizing noise on the power-supply rail is critical to
system performance. For example, the TPS7A87 can be used in a phase-locked loop (PLL)-based clocking
circuit can be used for minimum phase noise, or in test and measurement systems where even small powersupply noise fluctuations reduce system dynamic range.
Charge Pump Spurs
fN
1/
oi
se
Wide-Band Noise
N
oi
se
ai
G
Integrated Noise
From Band-Gap and Error Amplifier
n
R
ol
ff
l-O
Output Voltage Noise Density (nV/¥+])
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower
frequencies as a function of 1/f). Figure 49 shows a simplified output voltage noise density plot versus frequency.
Measurement Noise Floor
Frequency (Hz)
Figure 49. Output Voltage Noise Diagram
For further details, see the How to Measure LDO Noise white paper (SLYY076).
8.1.3.4 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved in several ways, as described in Table 7.
Table 7. Effect of Various Parameters on AC Performance (1) (2)
NOISE
(1)
(2)
PSRR
PARAMETER
LOWFREQUENCY
MIDFREQUENCY
HIGHFREQUENCY
LOWFREQUENCY
CNR/SSx
+++
No effect
No effect
CFFx
++
+++
+
MIDFREQUENCY
HIGHFREQUENCY
+++
+
No effect
++
+++
+
+++
COUTx
No effect
+
+++
No effect
+
VINx – VOUTx
+
+
+
+++
+++
++
PCB layout
++
++
+
+
+++
+++
The number of +'s indicates the improvement in noise or PSRR performance by increasing the parameter value.
Shaded cells indicate the easiest improvement to noise or PSRR performance.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the
output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with
Equation 7. The typical value of RNR is 250 kΩ. The effect of the CNR/SSx capacitor increases when VOUTx(Target)
increases because the noise from the reference is gained up when the output voltage increases. For low-noise
applications, a 10-nF to 10-µF CNR/SSx is recommended.
fcutoff = 1 / (2 × π × RNR × CNR/SSx)
(7)
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feedforward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing
out the loop bandwidth, thus improving mid-band PSRR.
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A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing
the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the
internal circuits. However, a high power dissipation across the die increases the output noise because of the
increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and
isolating VOUTx at high frequencies.
Table 8 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions
with an input voltage of 5.4 V, an R1x of 12.1 kΩ, and a load current of 0.5 A. The 5-V output is chosen because
this output is the worst-case condition for output voltage noise.
Table 8. Output Noise Voltage at a 5-V Output with a 5.4-V Input
CNR/SSx (nF)
CFFx (nF)
COUTx (µF)
SS_CTRLx
OUTPUT VOLTAGE
NOISE (µVRMS)
10
10
22
VINx
10.8
1000
100
22
VINx
5.6
1000
100
22
GND
5.6
1000
100
22 || 1000
VINx
5.0
8.1.3.4.1 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
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Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in
Figure 50 are broken down in this section and are described in Table 9. Regions A, E, and H are where the
output voltage is in steady-state.
VOUTx
B
A
F
C
D
E
G
H
IOUTx
Figure 50. Load Transient Waveform
Table 9. Load Transient Waveform Description
26
REGION
DESCRIPTION
A
Regulation
COMMENT
B
Output current ramping
C
LDO responding to transient
Recovery from the dip results from the LDO increasing its sourcing current, and leads
to output voltage regulation.
D
Reaching thermal equilibrium
At high load currents the LDO takes some time to heat up. During this time the output
voltage changes slightly.
E
Regulation
F
Output current ramping
G
LDO responding to transient
H
Regulation
Regulation
Initial voltage dip is a result of the depletion of the output capacitor charge.
Regulation
Initial voltage rise results from the LDO sourcing a large current, and leads to the
output capacitor charge to increase.
Recovery from the rise results from the LDO decreasing its sourcing current in
combination with the load discharging the output capacitor.
Regulation
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The transient response peaks (VOUTx(max) and VOUTx(min)) are improved by using more output capacitance;
however, doing so slows down the recovery time (Wrise and Wfall). Figure 51 shows these parameters during a
load transient, with a given pulse duration (PW) and current levels (IOUTx(LO) and IOUTx(HI)).
VOUTx(max)
Wrise
VOUTx
Wfall
VOUTx(min)
IOUTx(HI)
PW
IOUTx
IOUTx(LO)
IOUTx(LO)
tfall
trise
Figure 51. Simplified Load Transient Waveform
8.1.4 DC Performance
8.1.4.1 Output Voltage Accuracy (VOUTx)
The device features an output voltage accuracy of 1% maximum that includes the errors introduced by the
internal reference, load regulation, line regulation, and operating temperature as specified by the Electrical
Characteristics table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to
the expected nominal output voltage stated as a percent.
8.1.4.2
Dropout Voltage (VDO)
D
S(
O
N
)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VINx – VOUTx) that is required for regulation. When VINx drops below the required VDO for
the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch, as shown in
Figure 52.
Sl
op
e
=
~R
VDO
IOUTx
Figure 52. Dropout Voltage versus Output Current
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VINx on this device because of the internal charge pump. Dropout voltage increases exponentially when the
input voltage nears its maximum operating voltage because the charge pump multiplies the input voltage by a
factor of 4 and then is internally clamped to 8.0 V.
8.1.4.2.1 Behavior when Transitioning from Dropout into Regulation
Some applications can have transients that place the LDO into dropout, such as slower ramps on VINX for startup or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
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A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in
the right range, as shown in Figure 53. This condition is easily avoided through either the use of an enable
signal, or by increasing the soft-start time with CSS/NRx.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VINx = VOUTx(nom) + VDO
Voltage
Output Voltage
Dropout
VOUTx = VINx - VDO
Output Voltage in
normal regulation.
Time
Figure 53. Start-Up Into Dropout
8.1.5 Reverse Current Protection
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the body diode on the pass element instead of the normal
conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device
resulting from risks of electromigration and excess heat being dissipated across the device. If the current flow
gets high enough, a latch-up condition can be entered.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUTx > VINx + 0.3 V:
• If the device has a large COUTx and the input supply collapses quickly with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
If excessive reverse current flow is expected in the application, then external protection must be used to protect
the device. Figure 54 shows one approach of protecting the device.
Schottky Diode
INx
CINx
Internal Body Diode
OUTx
TI Device
COUTx
GND
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Figure 54. Example Circuit for Reverse Current Protection Using a Schottky Diode
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8.1.6 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be approximated using Equation 8:
PD = (VOUTx – VINx) × IOUTx
(8)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to
Equation 9. The equation is rearranged for output current in Equation 10.
TJ = TA + θJA × PD
IOUTx = (TJ – TA) / [θJA × (VINx – VOUTx)]
(9)
(10)
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θJA recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area,
and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal
layout, θJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the
thermal resistance contribution by the PCB copper.
8.1.6.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the table and are used in accordance with Equation 11.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 8
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(11)
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8.1.6.2 Recommended Area for Continuous Operation (RACO)
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator can be separated into the
following parts, and is shown in Figure 55:
•
•
•
Output Current (A)
•
Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VINx – VOUTx) at a given output current level; see the Dropout Voltage (VDO) section for more details.
Limited by rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
Limited by thermals: The shape of the slope is given by Equation 10. The slope is nonlinear because the
junction temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when VINx –
VOUTx increases, the output current must decrease in order to ensure that the rated junction temperature of
the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and
reduces long-term reliability.
Limited by VINx range: The rated input voltage range governs both the minimum and maximum of VINx –
VOUTx.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited by Thermals
Limited by
Maximum VINx
Limited by
Minimum VINx
VINx ± VOUTx (V)
Figure 55. Continuous Operation Slope Region Description
30
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Figure 56 to Figure 61 show the recommended area of operation curves for this device on a JEDEC-standard,
high-K board with a θJA = 35.4°C/W, as given in the table.
0.75
0.75
TA = 55qC
TA = 70qC
TA = 85qC
0.45
0.3
0.15
0.45
0.3
0
0
1.5
3
VINx - VOUTx (V)
4.5
6
0
Figure 56. Recommended Area for Continuous Operation
for VOUTx = 0.8 V
1.5
3
VINx - VOUTx (V)
4.5
6
Figure 57. Recommended Area for Continuous Operation
for VOUTx = 1.2 V
0.75
0.75
TA = 55qC
TA = 70qC
TA = 85qC
TA = 105qC
RACO at TA = 105qC
TA = 55qC
TA = 70qC
TA = 85qC
0.6
Output Current (A)
0.6
Output Current (A)
TA = 105qC
RACO at TA = 105qC
0.15
0
0.45
0.3
0.15
TA = 105qC
RACO at TA = 105qC
0.45
0.3
0.15
0
0
0
1.5
3
VINx - VOUTx (V)
4.5
6
0
Figure 58. Recommended Area for Continuous Operation
for VOUTx = 1.8 V
1.5
3
VIN - VOUT (V)
4.5
6
Figure 59. Recommended Area for Continuous Operation
for VOUTx = 2.5 V
0.75
0.75
TA = 55qC
TA = 70qC
TA = 85qC
TA = 105qC
RACO at TA = 105qC
TA = 55qC
TA = 70qC
TA = 85qC
0.6
Output Current (A)
0.6
Output Current (A)
TA = 55qC
TA = 70qC
TA = 85qC
0.6
Output Current (A)
Output Current (A)
0.6
TA = 105qC
RACO at TA = 105qC
0.45
0.3
0.15
TA = 105qC
RACO at TA = 105qC
0.45
0.3
0.15
0
0
0
1.5
3
VINx - VOUTx (V)
4.5
6
Figure 60. Recommended Area for Continuous Operation
for VOUTx = 3.3 V
0
0.5
1
VINx - VOUTx (V)
1.5
2
Figure 61. Recommended Area for Continuous Operation
for VOUTx = 5.0 V
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8.2 Typical Application
This section discusses the implementation of the TPS7A87 to regulate from a common input voltage to two
output voltages of the same value. This application is common for when two noise-sensitive loads must have the
same supply voltage but have high channel-to-channel isolation. The schematic for this application circuit is
provided in Figure 62.
VINx
INx
CINx
VOUTx
OUTx
R1x
ENx
COUTx
FBx
SS_CTRLx
R2x
NR/SSx
VPULL-UP
CNR/SSx
TI Device
RPGx
VPGx
PGx
GND
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Figure 62. Application Example (Single Channel)
8.2.1 Design Requirements
For the design example shown in Figure 62, use the parameters listed in Table 10 as the input parameters.
Table 10. Design Parameters
PARAMETER
Input voltages (VIN1 and VIN2)
Maximum ambient operating temperature
DESIGN REQUIREMENT
1.8 V, ±3%, provided by the dc-dc converter switching at 750 kHz
85°C
Output voltages (VOUT1 and VOUT2)
1.2 V, ±1%, output voltages are isolated
Output currents (IOUT2 and IOUT2)
400 mA (maximum), 10 mA (minimum)
Channel-to-channel isolation
Isolation greater than 50 dB at 100 kHz
RMS noise
< 5 µVRMS, bandwidth = 10 Hz to 100 kHz
PSRR at 750 kHz
> 40 dB
Startup time
< 5 ms
8.2.2 Detailed Design Procedure
The output voltages can be set to 1.2 V by selecting the correct values for R1x and R2x; see Equation 1.
Input and output capacitors are selected in accordance with the External Component Selection section. Ceramic
capacitances of 10 µF for both inputs and outputs are selected.
To minimize noise, a feed-forward capacitance (CFFx) of 10 nF is selected.
Channel-to-channel isolation depends greatly on the layout of the design. To minimize crosstalk between the
outputs, keep the output capacitor grounds on separate sides of the design. See the Layout section for an
example of how to layout the TPS7A87 to achieve best PSRR, channel-to-channel isolation, and noise.
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8.2.3 Application Curves
50
60
40
20
0
10
2
VOUTx = 5.0 V
VOUTx = 3.3 V
VOUTx = 1.2 V
VOUTx = 0.9 V
IOUTx
25
1.5
0
1
-25
0.5
-50
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 63. Power-Supply Rejection Ratio vs Frequency
Output Current (A)
80
IOUTx = 10 mA
IOUTx = 50 mA
IOUTx = 100 mA
IOUTx = 250 mA
IOUTx = 500 mA
AC-Coupled Output Voltage (mV)
Power-Supply Rejection Ratio (dB)
100
0
200
400
600
Time (Ps)
800
0
1000
Figure 64. Load Transient Response vs Time and VOUTx
9 Power Supply Recommendations
Both inputs of the TPS7A87 are designed to operate from an input voltage range between 1.4 V and 6.5 V. The
input voltage range must provide adequate headroom in order for the device to have a regulated output. This
input supply must be well regulated. If the input supply is noisy or has a high output impedance, additional input
capacitors with low ESR can help improve the output noise performance.
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10 Layout
10.1 Layout Guidelines
General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit
board and as near as practical to the respective LDO pin connections. Place ground return connections to the
input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly
discouraged and negatively affects system performance.
10.1.1 Board Layout
To maximize the performance of the device, following the layout example illustrated in Figure 65 is
recommended. This layout isolates the analog ground (AGND) from the noisy power ground. Components that
must be connected to the quiet analog ground are the noise-reduction capacitors (CNR/SSx) and the lower
feedback resistors (R2x). These components must have a separate connection back to the thermal pad of the
device. To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite
sides of the layout and only connect back to the device at opposite sides of the thermal pad. Connecting the
GND pins directly to the thermal pad and not to any external plane is recommended.
To maximize the output voltage accuracy, the connection from each output voltage back to the top output divider
resistors (R1x) must be made as close as possible to the load. This method of connecting the feedback trace
eliminates the voltage drop from the device output to the load.
To improve thermal performance, a 3 × 3 thermal via array must connect the thermal pad to internal ground
planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating
temperature of the device.
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10.2 Layout Example
Thermal Ground
RPG1
AGND
R21
PG1
R11
CNR/SS1
CFF1
EN1
NR/SS1
SS_CTRL1
PG1
FB1
CIN1
VOUT1 SENSE
on Bottom
Layer
20
19
18
17
16
COUT1
IN1
1
15
OUT1
IN1
2
14
OUT1
GND
3
13
GND
IN2
4
12
OUT2
IN2
5
11
OUT2
VIN1
VOUT1
VOUT2
VIN2
8
9
SS_CTRL2
PG2
10
FB2
7
NR/SS2
COUT2
6
EN2
CIN2
CFF2
VOUT2 SENSE
on Bottom
Layer
CNR/SS2
R12
PG2
R22
AGND
RPG2
Circles denote PCB via connections.
Thermal Ground
Figure 65. TPS7A87 Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A87.
The summary information for this fixture is shown in Table 11.
Table 11. Design Kits & Evaluation Modules (1)
(1)
NAME
PART NUMBER
TPS7A88 evaluation module
TPS7A88EVM User's Guide
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
The EVM can be requested at the Texas Instruments web site (www.ti.com) through the TPS7A87 product folder.
11.1.1.2 SPICE Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A87 is available through the TPS7A87 product folder
under simulation models.
11.1.2 Device Nomenclature
Table 12. Ordering Information (1)
PRODUCT
TPS7A87XXYYYZ
(1)
DESCRIPTION
XX represents the output voltage. 01 is the adjustable output version.
YYY is the package designator.
Z is the package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS37xx Dual-Channel, Low-Power, High-Accuracy Voltage Detectors Data Sheet (SBVS250)
• TPS7A88 Evaluation Module User's Guide (SBVU027)
• Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator Application Report
(SBVA042)
• How to Measure LDO Noise White Paper (SLYY076)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A8701RTJR
ACTIVE
QFN
RTJ
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPS7A87
TPS7A8701RTJT
ACTIVE
QFN
RTJ
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPS7A87
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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