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TPS82130
SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
TPS82130 17-V Input 3-A Step-Down Converter MicroSiP™ Module with Integrated
Inductor
1 Features
3 Description
•
•
•
•
•
•
•
•
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•
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The TPS82130 is a 17-V input 3-A step-down
converter MicroSiP™ power module optimized for
small solution size and high efficiency. The module
integrates a synchronous step-down converter and an
inductor to simplify design, reduce external
components and save PCB area. The low profile and
compact solution is suitable for automated assembly
by standard surface mount equipment.
1
3-mm × 2.8-mm × 1.5-mm MicroSiP™ Package
3-V to 17-V Input Range
3-A Continuous Output Current
DCS-Control™ Topology
Power Save Mode for Light Load Efficiency
20-µA Operating Quiescent Current
0.9-V to 6-V Adjustable Output Voltage
100% Duty Cycle for Lowest Dropout
Power Good Output
Programmable Soft Start-up with Tracking
Thermal Shutdown Protection
–40°C to 125°C Operating Temperature Range
Create a Custom Design using the TPS82130 with
the WEBENCH® Power Designer
To maximize efficiency, the converter operates in
PWM mode with a nominal switching frequency of
2 MHz and automatically enters power save mode
operation at light load currents. In power-save mode,
the device operates with typically 20-µA quiescent
current. Using the DCS-Control™ topology, the
device achieves excellent load transient performance
and accurate output voltage regulation.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
TPS82130
Industrial Applications
Telecom and Networking Applications
Solid State Drives
PACKAGE
µSiL (8)
BODY SIZE (NOM)
3.00 mm × 2.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
Simplified Schematic
1.8-V Output Application
12-V Input Voltage Efficiency
TPS82130
VIN
C1
10µF
C3
3.3nF
VOUT
EN
SS/TR
GND
R1
124kΩ
FB
PG
R3
100kΩ
C2
22µF
VOUT
1.8 V/3 A
R2
100kΩ
POWER GOOD
Copyright © 2016, Texas Instruments Incorporated
90
Efficiency (%)
VIN
12 V
100
80
70
VOUT = 1.0 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
60
50
1m
10m
100m
Load (A)
1
5
D017
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS82130
SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommend Operating Conditions...........................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
9
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
10.3 Thermal Consideration.......................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Development Support ...........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
12.1 Tape and Reel Information ................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2017) to Revision D
•
Page
Added Tape and Reel Information........................................................................................................................................ 22
Changes from Revision B (August 2016) to Revision C
Page
•
Added WEBENCH information to the Features, Detailed Design Procedure, and Device Support sections ....................... 1
•
Changed the Output voltage MAX value From: 5 V to: 6 V in the Recommend Operating Conditions table ........................ 4
•
Added Table 1, Power Good Pin Logic ................................................................................................................................ 10
Changes from Revision A (February 2015) to Revision B
Page
•
Changed storage temperature to -55°C from -40°C............................................................................................................... 4
•
Updated thermal information .................................................................................................................................................. 4
•
Added FB voltage accuracy at TJ = 0°C to 85°C condition .................................................................................................... 5
•
Changed derating curve based on ambient temperature .................................................................................................... 13
•
Changed derating curve based on ambient temperature ..................................................................................................... 13
•
Added derating curve for VOUT = 1.0 V ................................................................................................................................. 14
•
Deleted Thermal pictures ..................................................................................................................................................... 17
•
Added "Receiving Notification of Documentation Updates" section..................................................................................... 18
Changes from Original (December 2015) to Revision A
•
2
Page
Production Data release ........................................................................................................................................................ 1
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SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
5 Pin Configuration and Functions
8-Pin µSiL Package
(SIL0008C Top View)
EN
1
VIN
2
GND
3
VOUT
4
Thermal
Pad
8
SS/TR
7
PG
6
FB
5
VOUT
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has
an internal pull-down resistor of typically 400 kΩ when the device is disabled.
EN
1
I
VIN
2
PWR
GND
3
VOUT
4, 5
PWR
FB
6
I
Feedback reference pin. An external resistor divider connected to this pin programs the
output voltage.
PG
7
O
Power good open drain output pin. A pull-up resistor can be connected to any voltage
less than 6V. Leave it open if it is not used.
SS/TR
8
I
Soft startup and voltage tracking pin. An external capacitor connected to this pin sets the
internal reference voltage rising time.
Input pin.
Ground pin.
Exposed Thermal Pad
Output pin.
The exposed thermal pad must be connected to the GND pin. Must be soldered to
achieve appropriate power dissipation and mechanical reliability.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Voltage at pins (2)
Sink current
MIN
MAX
VIN
-0.3
20
EN, SS/TR
-0.3
VIN + 0.3
PG, FB
-0.3
7
VOUT
0
PG
UNIT
V
7
10
mA
Module operating temperature
–40
125
°C
Storage temperature
–55
125
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
VIN
Input voltage
VPG
Power good pull-up resistor voltage
VOUT
Output voltage
IOUT
Output current
TJ
Module operating temperature range for 100,000 hours lifetime (1)
(1)
MIN
MAX
UNIT
3
17
V
6
V
6
V
0.9
0
3
A
-40
110
°C
The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where
high power dissipation is present, the maximum operating temperature or maximum output current must be derated. For applications
where the module operates continuously at 125 °C temperature, the maximum lifetime is reduced to 50,000 hours.
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
TPS82130
(JEDEC 51-5)
TPS82130EVM-720
UNIT
58.2
46.1
°C/W
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
9.4
9.4
°C/W
RθJB
Junction-to-board thermal resistance
14.4
14.4
°C/W
ψJT
Junction-to-top characterization parameter
0.9
0.9
°C/W
ψJB
Junction-to-board characterization parameter
14.2
14.0
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
21.3
21.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. Theta-JA can be improved with a custom PCB design containing thermal vias where possible.
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6.5
SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
Electrical Characteristics
TJ = -40°C to 125°C and VIN = 3.0V to 17V. Typical values are at TJ = 25°C and VIN = 12V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN
No load, device not switching
20
35
µA
ISD
Shutdown current into VIN
EN = Low
1.5
7.4
µA
2.7
2.8
V
2.9
3.0
VUVLO
TJSD
Under voltage lock out threshold
Thermal shutdown threshold
VIN falling
2.6
VIN rising
2.8
V
TJ rising
160
°C
TJ falling
140
°C
LOGIC INTERFACE (EN)
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg(EN) Input leakage current into EN pin
0.9
EN = High
0.65
V
0.45
0.3
V
0.01
1
µA
µA
CONTROL (SS/TR, PG)
ISS/TR
VPG
SS/TR pin source current
Power good threshold
2.1
2.5
2.8
VOUT rising, referenced to VOUT nominal
92%
95%
99%
VOUT falling, referenced to VOUT nominal
87%
90%
94%
VPG,OL Power good low-level voltage
Isink = 2mA
0.1
0.3
V
Ilkg(PG) Input leakage current into PG pin
VPG = 1.8V
1
400
nA
OUTPUT
PWM mode
VFB
Feedback regulation voltage
PSM
Ilkg(FB)
Feedback input leakage current
785
800
815
TJ = 0°C to 85°C
788
800
812
COUT = 22 µF
785
800
823
COUT = 2x22 µF, TJ = 0°C to 85°C
788
800
815
1
100
VFB = 0.8V
Line regulation
IOUT = 1A, VOUT = 1.8V
0.00
2
Load regulation
IOUT = 0.5A to 3A, VOUT = 1.8V
0.12
mV
nA
%/V
%/A
POWER SWITCH
High-side FET on-resistance
RDS(on
)
Low-side FET on-resistance
ISW = 500mA, VIN ≥ 6V
90
ISW = 500mA, VIN = 3V
120
ISW = 500mA, VIN ≥ 6V
40
ISW = 500mA, VIN = 3V
50
100% mode, VIN ≥ 6V
125
100% mode, VIN = 3V
160
RDP
Dropout resistance
ILIMF
High-side FET switch current limit
VIN = 6V, TA = 25°C
fSW
PWM switching frequency
IOUT = 1A, VOUT = 1.8V
3.6
4.2
170
70
mΩ
4.9
2.0
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A
MHz
5
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SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
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6.6 Typical Characteristics
50
250
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
$
4XLHVFHQW &XUUHQW
'URSRXW 5HVLVWDQFH P
40
200
150
100
30
20
10
VIN = 3.0 V
VIN = 6.0 V
50
-40
-20
0
20
40
60
80
Module Temperature (°C)
100
0
120
3
5
7
9
11
Input Voltage (V)
D014
13
15
17
D025
Figure 2. Quiescent Current
Figure 1. Dropout Resistance
6KXWGRZQ &XUUHQW
$
8
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
6
4
2
0
3
5
7
9
11
Input Voltage (V)
13
15
17
D026
Figure 3. Shutdown Current
6
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SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
7 Detailed Description
7.1 Overview
The TPS82130 synchronous step-down converter MicroSiP™ power module is based on DCS-Control™ (Direct
Control with Seamless transition into Power Save Mode). This is an advanced regulation topology that combines
the advantages of hysteretic and voltage mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in PSM (Power Save Mode) at light load currents. In PWM mode, the converter operates with its
nominal switching frequency of 2.0MHz having a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and
minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to PSM without effects on the output voltage. The TPS82130 offers excellent DC voltage regulation and load
transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
PG
VIN
VFB
High Side
Current Sense
VREF
EN
400kΩ(1)
Bandgap
Undervoltage Lockout
Thermal Shutdown
L
(2)
MOSFET Driver
Control Logic
VIN
Ramp
SS/TR
Voltage
Clamp
VREF
Timer
ton
Direct Control
and
Compensation
FB
Comparator
Error Amplifier
DCS - Control
VOUT
22pF
TM
VREF
GND
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
(2) The integrated inductor of 1 µH in the module.
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PWM and PSM Operation
The TPS82130 includes an on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM modes, is
estimated as:
V
t ON = 500ns ´ OUT
VIN
(1)
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Feature Description (continued)
In PWM mode, the TPS82130 operates with pulse width modulation in continuous conduction mode (CCM) with
a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0MHz
is achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than
half the inductor's ripple current estimated by Equation 2.
V - VOUT
DIL = t ON ´ IN
(2)
L
To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current
decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM,
the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high
efficiency. PSM is also based on the tON circuitry. The switching frequency in PSM is estimated as:
2 ´ IOUT
fPSM =
V - VOUT
V
t ON2 ´ IN ´ IN
VOUT
L
(3)
In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced
by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical
specification table and given for a 22-µF output capacitor.
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such cases.
When VIN decreases to typically 15% above VOUT, the TPS82130 can't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
7.3.2 Low Dropout Operation (100% Duty Cycle)
The TPS82130 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode,
the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications
to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain a minimum output voltage is given by:
VIN(min) = VOUT(min) + IOUT ´ RDP
(4)
Where
RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor
VOUT(min) = Minimum output voltage the load can accept.
7.3.3 Switch Current Limit
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition.
If the inductor peak current reaches the switch current limit after a propagation delay of typically 30 ns, the highside FET is turned off and the low-side FET is turned on to ramp down the inductor current.
7.3.4 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 200 mV.
7.3.5 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8
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7.4 Device Functional Modes
7.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. Accordingly, the shutdown mode is forced if the EN
pin is pulled Low with a shutdown current of typically 1.5 μA.
An internal pull-down resistor of 400kΩ is connected to the EN pin when the EN pin is Low. The pulldown resistor
is disconnected when the EN pin is High.
7.4.2 Soft Startup (SS/TR)
The internal voltage clamp controls the output voltage slope during startup. This avoids excessive inrush current
and ensures a controlled output voltage rise time. When the EN pin is pulled high, the device starts switching
after a delay of typically 55μs and the output voltage rises with a slope controlled by an external capacitor
connected to the SS/TR pin. Using a very small capacitor or leaving the SS/TR pin floating provides fastest
startup time.
The TPS82130 is able to start into a pre-biased output capacitor. During the pre-biased startup, both the power
MOSFETs are not allowed to turn on until the internal voltage clamp sets an output voltage above the pre-bias
voltage.
When the device is in shutdown, undervoltage lockout or thermal shutdown, the capacitor connected to SS/TR
pin is discharged by an internal resistor. Returning from those states causes a new startup sequence.
7.4.3 Voltage Tracking (SS/TR)
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 4.
VOUT1
VOUT2
TPS82130
R3
R1
SS/TR
R2
FB
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Output Voltage Tracking
When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in
Equation 5.
VOUT 2
R2
R3 + R4
» 0.64 ´
´
R1 + R2
R4
VOUT1
(5)
When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated
at 0.8 V. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So the resulting
decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the
SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
Details about tracking and sequencing circuits are found in SLVA470.
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Device Functional Modes (continued)
7.4.4 Power Good Output (PG)
The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open drain output and is specified to sink up to 2 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin floating when it is not used. Table 1 shows the PG pin logic.
Table 1. Power Good Pin Logic
PG Logic Status
Device State
Enable (EN=High)
High Impedance
VFB ≥ VTH_PG
VFB ≤ VTH_PG
√
√
Shutdown (EN=Low)
UVLO
Thermal Shutdown
Power Supply Removal
10
Low
√
0.7 V < VIN < VUVLO
√
TJ > TSD
√
VIN < 0.7 V
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The output voltage of the TPS82130 is adjusted by component selection. The following section discusses the
design of the external components to complete the power supply design for several input and output voltage
options by using typical applications as a reference.
8.2 Typical Applications
8.2.1
1.8-V Output Application
TPS82130
VIN
12 V
VIN
C1
10µF
VOUT
EN
SS/TR
C3
3.3nF
GND
R1
124kΩ
FB
PG
R3
100kΩ
C2
22µF
VOUT
1.8 V/3 A
R2
100kΩ
POWER GOOD
Copyright © 2016, Texas Instruments Incorporated
Figure 5. 1.8-V Output Application
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
12V
Output voltage
1.8V
Output ripple voltage
< 20mV
Output current rating
3A
The components used for measurements are given in the following table.
Table 3. List of Components
DESCRIPTION
MANUFACTURER
C1
REFERENCE
10 µF, 25 V, X7R, ±20%, size 1206, C3216X7R1E106M160AE
TDK
C2
22 µF, 10 V, ±20%, X7S, size 0805, C2012X7S1A226M125AC
TDK
C3
3300 pF, 50 V, ±5%, C0G/NP0, size 0603,
GRM1885C1H332JA01D
R1, R2, R3
Standard
Murata
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82130 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
= 0.8 V ´ ç 1 +
÷
R2 ø
R2 ÷ø
è
è
(6)
R2 should not be higher than 100kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. Figure 5 shows the
external resistor divider value for a 1.8-V output. Choose appropriate resistor values for other outputs.
In case the FB pin gets opened, the device clamps the output voltage at the VOUT pin internally to about 7V.
8.2.1.2.3
Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR ceramic capacitors are required. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device.
A 10-µF or larger input capacitor is required. The output capacitor value can range from 22μF up to more than
400μF. Higher values are possible as well and can be evaluated through the transient response. Larger soft start
times are recommended for higher output capacitances.
High capacitance ceramic capacitors have a DC bias effect, which will have a strong influence on the final
effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage
rating in combination with dielectric material are responsible for differences between the rated capacitor value
and the effective capacitance.
8.2.1.2.4 Soft Start-up Capacitor Selection
A capacitance connected between the SS/TR pin and the GND allows programming the startup slope of the
output voltage. A constant current of 2.5 μA charges the external capacitor. The capacitance required for a given
soft startup time for the output voltage is given by:
I
CSS / TR = t SS / TR ´ SS / TR
1.25 V
(7)
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8.2.1.3 Application Performance Curves
100
100
90
90
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 12 V, VOUT = 1.8 V, unless otherwise noted.
80
70
60
50
1m
80
70
60
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
50
10m
100m
Load (A)
1
3
5
5
100
100
90
90
80
70
50
1m
15
17
D019
70
60
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
50
10m
100m
Load (A)
1
5
3
5
9
11
Input Voltage (V)
13
15
17
D020
Figure 9. Efficiency, VOUT = 1.8 V
100
100
90
90
80
70
60
7
D002
Efficiency (%)
Efficiency (%)
13
80
Figure 8. Efficiency, VOUT = 1.8 V
50
1m
9
11
Input Voltage (V)
Figure 7. Efficiency, VOUT = 1.0 V
Efficiency (%)
Efficiency (%)
Figure 6. Efficiency, VOUT = 1 V
60
7
D001
80
70
60
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
50
10m
100m
Load (A)
1
5
3
D003
Figure 10. Efficiency, VOUT = 2.5 V
5
7
9
11
Input Voltage (V)
13
15
Product Folder Links: TPS82130
D021
Figure 11. Efficiency, VOUT = 2.5 V
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90
90
Efficiency (%)
100
Efficiency (%)
100
80
70
80
70
60
60
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
VIN = 5.0 V
VIN = 12 V
50
50
1m
10m
100m
Load (A)
1
5
5
7
Figure 12. Efficiency, VOUT = 3.3 V
90
Efficiency (%)
90
Efficiency (%)
100
80
70
60
60
100m
Load (A)
1
5
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
6
7
8
9
D023
10 11 12 13
Input Voltage (V)
14
15
16
17
D024
Figure 15. Efficiency, VOUT = 5 V
4
4
3
3
Output Current (A)
Output Current (A)
D022
50
10m
2
1
2
1
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
55
65
VIN = 5.0 V
VIN = 12 V
75
85
95
105
Ambient Temperature (°C)
115
125
0
45
55
D015
θJA = 46.1 °C/W
VOUT = 3.3V
Figure 16. Thermal Derating, VOUT = 1.8 V
14
17
70
Figure 14. Efficiency, VOUT = 5.0 V
VOUT = 1.8V
15
80
VIN = 12 V
0
45
11
13
Input Voltage (V)
Figure 13. Efficiency, VOUT = 3.3 V
100
50
1m
9
D004
65
75
85
95
105
Ambient Temperature (°C)
115
125
D016
θJA = 46.1 °C/W
Figure 17. Thermal Derating, VOUT = 3.3 V
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4
Output Voltage Accuracy (%)
1.0
Output Current (A)
3
2
1
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
0
45
55
65
75
85
95
105
Ambient Temperature (°C)
115
0.5
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
1m
125
10m
D027
100m
Load (A)
1
5
D005
VIN = 12V
Figure 18. Thermal Derating, VOUT = 1.0 V
Figure 19. Load Regulation
5x106
Switching Frequency (Hz)
Output Voltage Accuracy (%)
1.0
0.5
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
3
5
7
9
11
Input Voltage (V)
13
15
106
105
104
103
1m
17
D006
IOUT = 1A
VOUT = 1.8V
Figure 20. Line Regulation
TA = 25°C
TA = -40°C
TA = 85°C
10m
100m
Load (A)
1
5
D009
VIN = 12V
Figure 21. Switching Frequency
Switching Frequency (Hz)
3x106
VIN
50mV/DIV
AC
2x106
VOUT
10mV/DIV
AC
1x106
VOUT = 1.0 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0x100
3
5
7
9
11
Input Voltage (V)
13
15
D018
IOUT = 1A
Figure 22. Switching Frequency
Time - 500ns/DIV
17
D007
IOUT = 3A
Figure 23. Input and Output Ripple in PWM Mode
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VIN
20mV/DIV
AC
IOUT
2A/DIV
VOUT
50mV/DIV
AC
VOUT
10mV/DIV
AC
7LPH
V ',9
7LPH
V ',9
D008
No Load
D010
IOUT = 0A to 3A, 1A/µs
Figure 24. Input and Output Ripple in PSM Mode
Figure 25. Load Transient
VEN
5V/DIV
IOUT
2A/DIV
VPG
5V/DIV
VOUT
1V/DIV
VOUT
50mV/DIV
AC
IOUT
2A/DIV
7LPH
V ',9
7LPH
V ',9
D011
IOUT = 0.5A to 3A, 1A/µs
D012
No Load
Figure 26. Load Transient
Figure 27. Startup without Load
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
IOUT
2A/DIV
7LPH
V ',9
D013
ROUT = 0.68Ω
Figure 28. Startup / Shutdown with Resistance Load
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 3V and 17V. The average
input current of the TPS82130 is calculated as:
´I
1 V
IIN = ´ OUT OUT
h
VIN
(8)
Ensure that the power supply has a sufficient current rating for the applications.
10 Layout
10.1 Layout Guidelines
•
•
•
•
TI recommends placing all components as close as possible to the IC. The input capacitor placement
specifically, must be closest to the VIN and GND pins of the device.
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or
internal layer ground planes using vias.
Refer to Figure 29 for an example of component placement, routing and thermal design.
10.2 Layout Example
C3
VIN
C1
R2
EN
SS/TR
VIN
PG
GND
FB
VOUT
VOUT
R1
VOUT
GND
C2
Figure 29. TPS82130 PCB Layout
10.3 Thermal Consideration
The output current of the TPS82130 needs to be derated when the device operates in a high ambient
temperature or delivers high output power. The amount of current derating is dependent upon the input voltage,
output power, PCB layout design and environmental thermal condition. Care should especially be taken in
applications where the localized PCB temperature exceeds 65°C.
The TPS82130 module temperature must be kept less than the maximum rating of 125°C. Three basic
approaches for enhancing thermal performance are below:
• Improve the power dissipation capability of the PCB design.
• Improve the thermal coupling of the TPS82130 to the PCB.
• Introduce airflow into the system.
To estimate approximate module temperature of TPS82130, apply the typical efficiency stated in this datasheet
to the desired application condition to find the module's power dissipation. Then calculate the module
temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how to use
the thermal parameters in real applications, see the application notes: SZZA017 and SPRA953.
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11 Device and Documentation Support
11.1 Development Support
11.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82130 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
MicroSiP, DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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SLVSCY5D – FEBRUARY 2016 – REVISED NOVEMBER 2018
PACKAGE OUTLINE
SIL0008D
MicroSiP TM - 1.53 mm max height
SCALE 4.000
MICRO SYSTEM IN PACKAGE
2.9
2.7
B
A
PIN 1 INDEX
AREA
(2.5)
3.1
2.9
PICK AREA
NOTE 3
(2)
1.53 MAX
C
0.08 C
1.1±0.1
EXPOSED
THERMAL PAD
SYMM
(0.1)
TYP
5
4
SYMM
2X
1.9±0.1
1.95
1
8
6X 0.65
(45 X0.25)
PIN 1 ID
0.52
8X
0.48
8X
0.42
0.38
0.1
0.05
C A
C
B
4221520/A 07/2015
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
(1.1)
8X (0.5)
8
1
8X (0.4)
SYMM
(1.9)
(0.75)
6X (0.65)
5
4
SYMM
( 0.2) VIA
TYP
(2.1)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:20X
0.05 MIN
ALL SIDES
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(R0.05) TYP
DETAIL
NOT TO SCALE
4221520/A 07/2015
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
SOLDER MASK EDGE
8X (0.5)
1
(R0.05) TYP
(1.04)
8
8X (0.4)
METAL
TYP
(0.85)
SYMM
(1.05)
6X (0.65)
5
4
SYMM
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221520/A 07/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
22
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS82130SILR
uSiP
SIL
8
3000
330.0
12.4
3.05
3.25
1.68
8.0
12.0
Q1
TPS82130SILT
uSiP
SIL
8
250
178.0
13.2
3.05
3.25
1.68
8.0
12.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS82130SILR
uSiP
SIL
8
3000
383.0
353.0
58.0
TPS82130SILT
uSiP
SIL
8
250
223.0
194.0
35.0
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PACKAGE OPTION ADDENDUM
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10-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS82130SILR
ACTIVE
uSiP
SIL
8
3000
RoHS & Green
NIAU
Level-2-260C-1 YEAR
-40 to 125
H6
TXI1300EC
TPS82130SILT
ACTIVE
uSiP
SIL
8
250
RoHS & Green
NIAU
Level-2-260C-1 YEAR
-40 to 125
H6
TXI1300EC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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