Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
TPS9260x-Q1 Single- and Dual-Channel Automotive Headlight LED Driver
1 Features
3 Description
•
•
The TPS9260x-Q1 family of devices is a singlechannel and dual-channel high-side-current LED
driver. With full protection and diagnostics, this family
of devices is dedicated for and ideally suited to
automotive front lighting. The base of each
independent driver is a peak-current-mode boost
controller. Each controller has two independent
feedback loops, a current-feedback loop with a highside current-sensing shunt and a voltage-feedback
loop with an external resistor-divider network. The
controller delivers a constant output voltage or a
constant output current. The connected load
determines whether the device regulates a constant
output current (if the circuit reaches the current setpoint earlier than voltage set-point) or a constant
output voltage (if the circuit reaches the voltage setpoint is reached first, for example, in an open-load
condition).
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Input Voltage: 4 V–40 V (45 V Abs. Max.)
Output Voltage: 4 V–75 V (80 V Abs. Max.)
Fixed-Frequency Current-Mode Controller With
Integrated Slope Compensation
Two Regulation Loops, Constant-Current Output
and Constant-Voltage Output of Each Channel
High-Side Current Sense:
– 150-mV or 300-mV Sense Voltage (EEPROM
Option)
– ±6-mV Offset (Achieving Approx. 4% or 2%
LED Current Accuracy)
Output Voltage Sense, Internal Voltage
Reference: 2.2 V ±5%
Integrated Low-Side NMOS-FET Driver: Peak
Gate-Drive Current Typ. 0.7 A
Frequency Synchronization
Both PWM Dimming and Analog Dimming
Diagnostic:
– High-Side Current (LED Current) Available as
Analog Output
– Open-LED and Short-to-GND Detection
– Shorted Output Protection
Internal Under- and Overvoltage Lockout
2 Applications
•
•
Each controller supports all typical topologies such as
boost, boost-to-battery, SEPIC, or flyback.
Uses of the high-side PMOS FET driver are for PWM
dimming of the LED string and for cutoff in case of an
external short circuit to GND to protect the circuit.
Device Information(1)
PART NUMBER
SENSE-VOLTAGE
RANGE
CHANNELS
TPS92601-Q1,
TPS92601B-Q1
15 mV–150 mV
1
TPS92601A-Q1(2)
30 mV–300 mV
1
TPS92602-Q1,
TPS92602B-Q1
15 mV–150 mV
2
TPS92602A-Q1(2)
30 mV–300 mV
2
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Device is available as a preview only.
Automotive Headlight LED Driver
High-Brightness LED Applications
Figure 1. Typical Schematic
VBAT
VBAT
Part of
TPS92602-Q1
VIN
RT
DIAG1
GDRV1
COMP1
ISNS1
DIAG2
GDRV2
COMP2
ISNS2
ICTRL1
PWIN1
VCC
ISP1
ISN1
VOUT1
PWMO1
OVFB1
PGND1
Part of
TPS92602-Q1
CHANNEL
2
ICTRL2
PWIN2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
PGND2
AGND
CHANNEL
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2015) to Revision E
Page
•
Changed Device Information table ........................................................................................................................................ 1
•
Changed the pinout diagrams ................................................................................................................................................ 3
•
Changed VCC to VCC throughout the data sheet. .................................................................................................................. 4
Changes from Revision C (September 2014) to Revision D
Page
•
Changed the device status for the TPS92601-Q1 from Product Preview to Production Data ............................................... 1
•
Added single-channel in addition to the dual-channel text throughout the data sheet .......................................................... 1
•
Changed the Handling Ratings table to ESD Ratings and moved the storage temperature to the Absolute Maximum
Ratings table .......................................................................................................................................................................... 4
•
Updated the units of the Q(GS) equation (Equation 37) ...................................................................................................... 24
•
Updated the units of the Q(GS) equation (Equation 71) and the resulting values ............................................................... 31
•
Updated the rDS(on) values as a result of Equation 72........................................................................................................... 31
Changes from Revision B (August 2014) to Revision C
•
Page
Changed the package type for the TPS92601-Q1 and TPS92601A-Q1................................................................................ 3
Changes from Revision A (April 2014) to Revision B
Page
•
Added a column to the Device Comparison table ................................................................................................................. 1
•
Changed Device Information table ........................................................................................................................................ 1
•
Changed pinout diagram and combined Pin Function tables................................................................................................. 3
Changes from Original (March 2014) to Revision A
•
2
Page
Added all new content following the first page ....................................................................................................................... 3
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
5 Pin Configuration and Functions
TPS92602x-Q1 PWP PowerPAD™ Package
28-Pin HTSSOP With Exposed Thermal Pad
Top View
TPS92601x-Q1 PWP PowerPAD Package
20-Pin HTSSOP Package With Exposed Thermal Pad
Top View
ICTRL1
1
28
PWMO1
COMP1
2
27
VOUT1
OVFB1
3
26
RT
4
25
DIAG1
5
24
PGND1
GND
6
23
ISNS1
PWMIN1
7
22
GDRV1
ICTRL1
1
20
PWMO1
ISN1
COMP1
2
19
VOUT1
ISP1
OVFB1
3
18
ISN1
RT
4
17
ISP1
DIAG1
5
16
PGND1
GND
6
15
ISNS1
PWMIN1
7
14
GDRV1
VIN
8
13
VCC
NC
9
12
NC
NC
10
11
NC
Thermal
Thermal
VIN
8
21
VCC
PWMIN2
9
20
GDRV2
Pad
OVFB2
10
19
ISNS2
ICTRL2
11
18
PGND2
COMP2
12
17
ISP2
DIAG2
13
16
ISN2
PWMO2
14
15
VOUT2
Pad
Not to scale
NC – No internal connection
Not to scale
NC – No internal connection
Pin Functions
PIN
TPS92601-Q1
TPS92601A-Q1
TPS92601B-Q1
20 PINS
TPS92602-Q1
TPS92602A-Q1
TPS92602B-Q1
28 PINS
COMP1
2
2
O
Compensation network (channel 1)
COMP2
—
12
O
Compensation network (channel 2)
DIAG1
5
5
O
Diagnostic pin (open, short, LED current) (channel 1)
DIAG2
—
13
O
Diagnostic pin (open, short, LED current) (channel 2)
GDRV1
14
22
O
Gate driver NMOS-FET (channel 1)
GDRV2
—
20
O
Gate driver NMOS-FET (channel 2)
GND
6
6
—
Ground
ICTRL1
1
1
I
LED current-control pin, analog dimming (channel 1)
ICTRL2
—
11
I
LED current control pin, analog dimming (channel 2)
ISN1
18
26
I
Current-sense input – negative (channel 1)
ISN2
—
16
I
Current-sense input – negative (channel 2)
ISNS1
15
23
I
Overcurrent sense input (channel 1)
ISNS2
—
19
I
Overcurrent sense input (channel 2)
ISP1
17
25
I
Current-sense input – positive (channel 1)
ISP2
—
17
I
Current-sense input – positive (channel 2)
—
—
NAME
I/O
DESCRIPTION
9
NC
10
11
No internal connection
12
OVFB1
3
3
I
Voltage-feedback input (channel 1)
OVFB2
—
10
I
Voltage feedback input (channel 2)
PGND1
16
24
—
Power ground (channel 1)
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
3
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Pin Functions (continued)
PIN
TPS92601-Q1
TPS92601A-Q1
TPS92601B-Q1
20 PINS
TPS92602-Q1
TPS92602A-Q1
TPS92602B-Q1
28 PINS
PGND2
—
18
—
PWMIN1
7
7
I
PWM input and channel enable or disable function (channel 1)
PWMIN2
—
9
I
PWM input and channel enable or disable function (channel 2)
PWMO1
20
28
O
PWM PMOS-FET driver output (channel 1)
PWMO2
—
14
O
PWM PMOS-FET driver output (channel 2)
RT
4
4
I
Oscillator pin and pin for external sync. frequency
VCC
13
21
O
Gate-drive supply voltage (external decoupling capacitor)
NAME
I/O
DESCRIPTION
Power ground (channel 2)
VIN
8
8
I
Supply voltage
VOUT1
19
27
I
Connect to boost output voltage (channel 1)
VOUT2
—
15
I
Connect to boost output voltage (channel 2)
Thermal pad
—
Solder to achieve appropriate power dissipation. Connect to PGND.
6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature (unless otherwise noted)
MIN
Supply voltage
VIN, PWMINx (4)
MAX
–0.3
(4)
UNIT
40
V
Output voltage
VOUTx, ISPx, ISNx, PWMOx
–0.3
80
V
Differential voltage
(VOUTx – PWMOx) (4)
–0.3
8.8
V
Grounds
PGNDx (4)
–0.3
0.3
V
GDRVx, ISNSx
Other pins
VCC current
(4)
–0.3
8.8
V
OVFBx (4)
–0.3
80
V
VCC
–0.3
8.8
V
ICTRLx, COMPx, RT, DIAGx (4)
–0.3
3.6
V
220
mA
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
(3)
(4)
Gate-driver supply
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
The algebraic convention, whereby the most-negative value is a minimum and the most-positive value is a maximum.
All voltages are with respect to ground (GND pin), unless otherwise specified.
For the TPS9602-Q1 device, x = 1 or 2. For the TPS9601-Q1 device, x is blank.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
(1)
±2000
Other pins
V(ESD)
(1)
4
Electrostatic discharge
Charged-device model (CDM), per
AEC Q100-011
UNIT
±500
Corner pins (1, 14, 15, 28 for
TPS92602x-Q1; 1, 10, 11, 20 for
TPS92601x-Q1)
V
±750
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
6.3 Recommended Operating Conditions
over operating free-air temperature (unless otherwise noted)
Supply voltage
MIN
MAX
VIN (first connection to battery, full functionality)
6
26
V
VIN (battery voltage during cranking profile, full functionality)
4
26
V
26
40
V
4
75
V
VIN
Output sense
VOUTx, ISPx, ISNx (1)
PWMINx: enable and disable functionality
PWMIN
Other pins
(1)
UNIT
0
40
V
PWMINx: PWM functionality (1)
0
7
V
ISNSx, OVFBx (1)
0
8
V
VCC
3
8
V
ICTRLx, RT (1)
0
3.3
V
100
mA
Gate-driver supply current, VCC (2)
TA
Ambient temperature range
–40
125
°C
TJ
Junction temperature range
–40
150
°C
(1)
(2)
For the TPS9602-Q1 device, x = 1 or 2. For the TPS9601-Q1 device, x is blank.
Note available current for low-side gate drivers to drive the external BOOST FETs
6.4 Thermal Information
THERMAL METRIC
(1)
TPS92601-Q1
TPS92602-Q1
PWP (HTSSOP)
PWP (HTSSOP)
20 PINS
28 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
37
37.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.4
19.3
°C/W
RθJB
Junction-to-board thermal resistance
17.7
16.7
°C/W
ψJT
Junction-to-top characterization parameter
0.9
0.8
°C/W
ψJB
Junction-to-board characterization parameter
17.5
16.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, seeSemiconductor and IC Package Thermal Metrics application report,
SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
V(VIN_norm)
V(VIN_crank)
Input voltage range
Normal mode after initial start-up, VIN rising
6
40
Normal mode after initial start-up, VIN falling
4
40
V
V(UVLO)
Undervoltage lockout
PWM1 = PWM2 = High, VIN falling,f(PWMOx) <
V(VOUTx) – 2 V
3.72
4
V
V(UVsh)
Undervoltage shutdown
PWM1 = PWM2 = High, VIN falling, quiescent
current < 2 µA
2.8
3.5
V
V(OVSH)
Overvoltage shutdown
PWM1 = PWM2 = High, VIN falling, V(PWMOx) =
V(VOUTx), V(GRDVx) = 0
40
40.7
V
SUPPLY CURRENT
I(stby)
Shutdown current
VIN = 12 V, PWMIN1 and PWMIN2 = low for >
t(CH_OFF),
TA = 25°C
2
VIN = 12 V, PWMIN1 and PWMIN2 = low for >
t(CH_OFF),
TA = 125°C
3
t(CH_OFF)
Channel OFF timer
PWMINx = low
t(CH_ON)
Channel ON timer
PWMINx = high, VCC = 5.5 V
Inom
Normal-mode current in OVP loop
VIN = 12 V, PWMINx = high
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
µA
9.5
14
8
18
ms
1
ms
12
mA
Submit Documentation Feedback
5
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Electrical Characteristics (continued)
TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
5.5
6.6
MAX
UNIT
GATE DRIVER SUPPLY VCC
V(VCC)
Output voltage
VIN > 6 V
V(VCC_dr)
Drop-out voltage
4 V < VIN < 8 V, I(VCC) < 50 mA
C(VCC)
VCC buffer capacitance
I(VCC)
Output current (only for internal usage)
I(VCC_LIM)
Current limit
2.2
VCC shorted to ground
150
Gate-source voltage to switch on boost NMOS
FET. Depends on VCC
5.5
10
7.4
V
400
mV
20
µF
80
mA
220
mA
7.4
V
GATE DRIVER – LOW-SIDE BOOST NMOS-FET
VGS(NMOS)
NMOS gate-source voltage
6.6
D(MAX)
Maximum duty cycle
tr(NMOS)
Gate driver rising
VCC = 6.6 V, no load
22
tf(NMOS)
Gate driver falling
VCC = 6 V, no load
8.5
rDS(on)(Source,Nmos)
Gate driver resistance, sourcing
VCC = 6.6 V, 100-mA load
2.5
4
Ω
rDS(on)(Sink,Nmos)
Gate driver resistance, sinking
VCC = 6.6 V, 100-mA load
2.5
4
Ω
100
115
mV
65
µA
93.8%
ns
ns
CURRENT LIMIT – NMOS FET
V(ISNSx)
Voltage limit threshold across sensecurrent resistor
t(ISNSx)
Leading edge blanking
I(ISNSx)
Current on ISNSx
A(PS)
VC current-mode gain (ΔVvc / ΔVsns)
83
200
40
50
ns
4
V/V
150
mA
GATE DRIVER – HIGH-SIDE PWM PMOS-FET
I(PWMOx_Source)
Peak source current
V(OUT) – V(PWMOx) = 6.5 V, V(OUT) = 40 V
I(PWMOx_Sink)
Peak sink current
V(OUT) – V(PWMOx) = 0 V, V(OUT) = 40 V
V(PWMOx)
Output voltage
VGS(PMOS)
PMOS gate-source voltage
PWMx = high, V(OUT) = 40 V
VGS(NMOS)
NMOS gate-source voltage
Sufficient gate-source voltage to switch on the
NMOS FET; this depends on VCC.
tr(PMOS)
HS gate driver rising
No load
1
µs
tf(PMOS)
HS gate driver falling
No load
3
µs
f(PWMIN)
Dimming frequency
See PWM dimming section
2
kHz
V(thLOW)
Logic low
Switch off PMOS dimming FET (low below)
V(thHIGH)
Logic high
Switch on PMOS dimming FET (high above)
R(PWMIN_pd)
Pulldown resistance at PWMINx pin
10
4
mA
75
V
6
6.9
8
V
5.5
6.6
7.4
V
PWM DIMMING
0.2
0.8
V
150
kΩ
2
90
V
120
PWMIN to LED turnoff time
80
ns
PWMIN to LED turnon time
60
ns
INTERNAL PLL OSCILLATOR
f(OSC)
Oscillator range
RT: 20-kΩ resistor. See Equation 2 and Figure 4
for f(OSC) vs RT
100
600
–20%
20%
100
kHz
Δf(OSC)
Oscillator accuracy
f(EXT)
Ext. synchronization
600
kHz
t(CLKpw)
Minimum clock input pulse duration
70
ns
V(RTthLO)
RT low voltage
0.8
V
V(RTthHI)
RT high voltage
t(RTdelay)
RT rising edge to GDRV1 rising edge
t(PLLlock)
PLL lock-in time
6
Submit Documentation Feedback
2
V
35
200
ns
µs
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Electrical Characteristics (continued)
TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-SIDE CURRENT-SENSE ERROR AMPLIFIER VFBx < 2.1 V
V(SPSN,Com)
V(SPSN_Diff)
Common-mode voltage ISPx, ISNx
Full-scale sense voltage ISPx – ISNx
4
74
4 V < V(SPSN_Com) < 75 V, VFBx < 2.1 V,
TPS92601-Q1, TPS92602-Q1,TPS92601B-Q1,
TPS92602B-Q1
150
4 V < V(SPSN_Com) < 75 V, VFBx < 2.1 V,
TPS92601A-Q1, TPS92602A-Q1
300
mV
V(SPSN_AC)
Sense-voltage accuracy
Common-mode voltage 4 V to 75 V
I(BIAS_SPSN)
Input bias current ISPx, ISNx
4 V < V(SPSN_Com) < 75 V, V(SPSN_Diff) = 150 mV
100
135
Input offset current ISPx, ISNx
TPS92601-1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1, 4 V < V(SPSN_Com) < 75 V,
V(SPSN_Diff) = 150 mV
TPS92601A-Q1, TPS92602A-Q1, 4 V <
V(SPSN_Com) < 75 V, V(SPSN_Diff) = 300 mV
175
200
I(offset_SPSN)
gMC
–6
mV
µA
µA
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1
HS current-sense gain
6
40
Forward transconductance
A(HSCS)
V
TPS92601A-Q1, TPS92602A-Q1
1
mS
5
V/V
2.5
V/V
CURRENT CONTROL ICTRL – ANALOG DIMMING FOR ALL PARAMETERS: VFBx < 2.1 V
I(DIM_LIN)
K(DIMfactor)
Linear analog dimming range
Dimming factor, V(ICTRL) / V(SNSPx)
10%
9.7
10
10.3
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1, TA = 125ºC (1)
9.5
10
10.5
4.85
5
5.15
4.75
5
5.25
TPS92601A-Q1, TPS92602A-Q1, TA = 25ºC
(1)
TPS92601A-Q1, TPS92602A-Q1, TA = 125ºC (1)
V(ICTRLx)
Adjustable voltage range
R(ICTRLpd)
Pulldown resistance at ICTRLx pin
100%
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1, TA = 25ºC (1)
See Figure 13
0
0.75
1
1.5
V
1.2
MΩ
ERROR AMPLIFIER - REFERENCE VOLTAGE
V(VFB)
Voltage feedback
ΔV(VFB)
Voltage FB accuracy
I(BIAS)
Input bias current
g(Mv)
Forward transconductance
2.2
–5%
V
5%
VFB = 2.2 V
500
nA
1
mS
3.5
ms
INTERNAL SOFT-START
t(softstart)
Soft-start time, internal soft-start
COMP 0 V to 1.5 V
DIAGNOSIS – DIAGx PIN
V(OPLED)
V(DIAG_OP)
V(SHLED)
Open LED failure
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1
10
TPS92601A-Q1, TPS92602A-Q1
20
Low-level voltage, DIAGx pin
DIAGx pin pulled low, I(DIAGx) = 100 µA
Shorted LED failure
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1
225
TPS92601A-Q1, TPS92602A-Q1
450
0.15
V(DIAG_SH)
High-level voltage, DIAGx pin
V(ILED1)
V(ILED2)
Range for tracking LED current on DIAGx
pin
Voltage range on DIAGx pin (VIN > 6 V)
V(DIAG_AC)
Offset of DIAG output buffer
At input of DIAG buffer
12.5
Factor V(DIAG) / V(SPSN)
Within linear analog dimming range and DIAG
tracking range. Exclusive offset V(DIAG_AC),
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1,
TPS92602B-Q1
Within linear analog dimming range and DIAG
tracking range. Exclusive offset V(DIAG_AC),
TPS92601A-Q1, TPS92602A-Q1
6.25
K(DIAG_factor)
(1)
mV
DIAGx pin pulled high, I(DIAGx) = 100 µA
V
mV
3
3.47
0.2
2.85
0.2
2.85
–12
12
V
V
mV
Within linear analog dimming range (10%–100%). Exclusive offset V(SPSN_AC) = 6 mV
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
7
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Electrical Characteristics (continued)
TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMPENSATION NETWORK – COMPx PIN
V(COMPx)
Compensation-network output-pin voltage
0
3.3
V
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
T(HYS)
Hysteresis
165
°C
20
°C
6.6 Typical Characteristics
Load is eight LEDs per channel at 500 mA, –40ºC ≤ TA ≤ 125ºC, –40ºC ≤ TJ ≤ 150ºC, C(COMP) = 0.22 µF, unless otherwise
noted.
510
100
CH1
508
98
CH2
96
LED Current (mA)
Boost Efficiency (%)
506
94
92
90
504
502
500
498
496
494
88
492
490
86
8
10
12
14
16
18
V(VIN) Voltage (V)
20
8
10
14
16
18
V(VIN) Voltage (V)
Figure 2. Boost Efficiency vs Input Voltage
20
C002
Figure 3. Line Regulation
700
600
600
500
Output Current (mA)
Switching Frequency (kHZ)
12
C001
500
400
300
200
CH1
CH2
400
300
200
100
100
0
0
0
20
40
60
80
100
R(RT) Resistance (kŸ)
120
140
0
20
40
60
80
Dimming Duty Cycle (%)
C003
100
C004
f(PWM) = 200 Hz
Figure 4. Switching Frequency vs R(RT) Resistance
8
Submit Documentation Feedback
Figure 5. I(OUT) vs PWM Dimming Duty Cycle
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Typical Characteristics (continued)
Load is eight LEDs per channel at 500 mA, –40ºC ≤ TA ≤ 125ºC, –40ºC ≤ TJ ≤ 150ºC, C(COMP) = 0.22 µF, unless otherwise
noted.
3000
180
160
2500
120
V(DIAGx) (mV)
ISP t ISN (mV)
140
100
80
60
2000
1500
1000
40
500
20
0
0
0
500
1000
1500
2000
V(ICTRLx) (mV)
0
2500
100
503
603
502
Output Current (mA)
601
597
595
593
591
589
200
250
C006
Figure 7. V(DIAGx) vs V(ISPx – ISNx)
605
599
150
ISP t ISN (mV)
Figure 6. Analog Dimming: Differential Sense Voltage,
V(ISPx – ISNx) vs V(ICTRLx)
Switching Frequency (kHZ)
50
C005
CH1
CH2
501
500
499
498
497
496
587
585
495
±40 ±25 ±10
5
20
35
50
65
80
Ambient Temperature (ƒC)
95
110 125
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
Ambient Temperature (ƒC)
C007
C008
R(RT) = 20 kΩ
Figure 8. Switching Frequency vs Ambient Temperature
Figure 9. V(ISPx – ISNx) vs Ambient Temperature
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
9
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TPS92602y-Q1 device is a dual-channel LED driver. The base of each independent driver is a peak-currentmode boost controller. The two boost controllers operate 180° out-of-phase in order to reduce ripple currents and
radiation.
Each controller is independently configurable to regulate the output current (the typical case for driving LEDs) or
to regulate the output voltage. Depending on the chosen configuration for each channel, one loop is active while
the other loop only acts in case of a failure condition. In a constant-current application, the inactive voltage loop
sets the maximum output-voltage limit (and hence becomes active in case of output overvoltage due to an open
LED). In constant-voltage applications, the inactive current loop sets the maximum output current limit (and
hence becomes active in case of output overcurrent because of an LED short to ground).
The TPS92601y-Q1 device is a single-channel version of the TPS92602y-Q1 device. Both devices have the
same functions.
7.2 Functional Block Diagram
V(BAT)
L
VIN
TPS9260x-Q1
LDO
VDD
LDO
VCC
Int. FET
C
D
LED
VCC
Int. FET
CVCC
Voltage
Monitor
TJ
Shutdown
ISP
+
UVLO
±
VDD
Shutdown
Logic
VOUT
DIAG
Osc
or
PLL
ROSC
VCC
CLRZ
CLRZ
D
CLK
QZ
Q
VDD
Slope
Compensation
CP
±
±
VDD
VDD
VDD
C Z RZ
VDD
PWMIN
PWMO
MP
Overcurrent
Detect
GDRV
ISNS
+
+
+
COMP
VDD
1
CLRZ
&
RT
RLED_SNS
ISN
Softstart
RSNS
100 mV
ROVFB_B
OVFB
±
+
±
+
+
2.2 V
ROVFB_A
0.75 V
ICTRL
PGND
GND
Figure 10. Block Diagram, TPS9260xy-Q1 in Boost-To-Battery Configuration
10
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Functional Block Diagram (continued)
TPS9260x-Q1
VBAT
TPS9260x-Q1
VBAT
TPS9260x-Q1
VBAT
TPS9260x-Q1
VBAT
TPS9260x-Q1
VBAT
VCC
VCC
VCC
VCC
VCC
BOOST-TO-BATTERY
SEPIC
BOOST
FLYBACK
BUCK-TO-BATTERY
Note: The SEPIC and flyback topologies require two extra diodes per channel for start-up, because the minimum common-mode voltage of the current-regulation amplifier is 4 V.
Figure 11. Supported Topologies per Channel
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
Each boost controller uses an adjustable fixed-frequency peak-current-mode control. In a constant-current
application, the device senses the output current across an external shunt resistor at the ISPx and ISNx pins,
amplifies and level-shifts it to ground-reference, and compares it to the voltage applied on the ICTRLx pin by the
primary error amplifier, which drives the COMPx pin. In a constant-voltage application, the device compares the
output voltage through external resistors on the OVFBx pin to an internal 2.2-V voltage reference by a secondary
error amplifier, which drives the COMPx pin. Depending on the chosen application, only one of the error
amplifiers is active.
An internal oscillator initiates the turnon of the external boost-power NMOS switch. The device compares the
error-amplifier output to the switch current sensed on the ISNSx pin. When the power-switch current reaches the
level set by the COMPx voltage, the power NMOS switch turns off. The COMPx pin voltage increases and
decreases as the output current increases and decreases. The device implements a current limit by clamping the
COMPx pin voltage to a maximum level.
7.3.2 Slope-Compensation Output Current
Each controller adds a compensating ramp to the switch-current signal. This slope compensation prevents subharmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
11
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Feature Description (continued)
7.3.3 Boost-Current Limit
Each controller achieves peak-current-mode control using a comparator that monitors the current through the
external boost FET at the ISNSx pin by comparing it with the voltage on the COMPx pin. A redundant currentlimit comparator, which compares the voltage on the ISNSx pin with a typical 100-mV reference voltage, limits
the current through the external boost FET. If the voltage on the ISNSx pin exceeds this typical 100-mV
threshold, the on-cycle of the respective boost controller immediately terminates. The current-limit comparator
has a lead-edge blanking time to avoid any unwanted triggering of the current limit during switch-on of the
external boost FET. One can set the current-limit level with an external resistor, as calculated with the following
equation.
100 mV
I (Lim) =
R (LIM)
(1)
7.3.4 Oscillator and PLL
The switching frequency is adjustable over a range from 100 kHz to 600 kHz by placing a resistor on the RT pin.
The RT pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To
determine the timing resistance for a given switching frequency, use Equation 2 or the curve in Figure 4. To
reduce the solution size one would typically set the switching frequency as high as possible, but give
consideration to tradeoffs of the supply efficiency, maximum input voltage, and minimum controllable on-time.
12.5 MHz ´ 1 kW
R RT [kW] =
f (OSC) [MHz]
(2)
One can also use the RT pin to synchronize the controllers to an external system clock, over a range from 100
kHz to 600 kHz. Apply a square wave to the RT pin to use this synchronization feature. The square wave must
transition lower than 0.8 V and higher than 2 V on the RT pin and have an on-time greater than 70 ns and an off
time greater than 70 ns. The synchronization frequency range is 100 kHz to 600 kHz. The rising edge of GDRV1
is synchronized to the falling edge of the RT pin signal.
Leaving the RT pin open or shorted to ground with no external system clock signal is present disables both boost
controllers, and both PWM dimming FETs switch off. In order to recover from this global failure state, (for
example, after the failure condition on the RT pin has been removed) there must be one global disable-andenable cycle (active shutdown by pulling both PWMINx pins low for t > t(CH_OFF), and setting one or both PWMINx
pins high for t > t(CH_ON)).
7.3.5 Control Loop Compensation
Modeling of the TPS9260xy-Q1 control loop is like that for any current-mode controller. Using a first-order
approximation, one can model the uncompensated loop as a single pole created by the output capacitor and, in
the boost and buck-boost topologies, a right half-plane zero created by the inductor, where both have a
dependence on the dynamic resistance of the LED string. There is also in the model a high-frequency pole
which, however, is near the switching frequency and plays no part in the compensation design process.
Therefore, the loop analysis neglects this high-frequency pole. Because TI recommends ceramic capacitors for
use with LED drivers due to long lifetimes and high ripple-current rating, one can also neglect the ESR of the
output capacitor in the loop analysis. Finally, there is a dc gain of the uncompensated loop which depends on
internal controller gains and the external sensing network. A boost regulator serves as an example case. See the
Detailed Design Procedure section for compensation of all topologies.
Equation 3 gives the whole-loop gain for a boost regulator.
æ
s( j) ö æ
s( j)
ç1 +
÷ ´ çç 1 w
w
ezc ø è
ezrhp
è
Tu = Tuo ´
æ
ö
s( j)
ç1 +
÷
ç
÷
w
ep0 ø
è
ö
÷
÷
ø
(3)
Equation 4 approximates the output pole (ωep0).
12
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Feature Description (continued)
wep0 =
2
r(D) ´ Co
where
•
•
r(D): LED and R(ILED_SNS) dynamic resistance
CO: Output capacitor
(4)
Use Equation 5 to calculate the right half-plane zero (ωezrhp).
wezrhp =
r(D) ´ D' 2
L1
(5)
Use Equation 6 to calculate the output capacitor and ESR zero (ωezc).
1
wezc =
resr ´ Co
(6)
The EA transfer function with compensation capacitor and resistor of the system is described in Equation 7 is
shown in Equation 7.
s( j) ö
æ
ç 1 + wez1 ÷
è
ø
Tuo = Adc ´
æ
s( j) ö æ
s( j) ö
ç1 +
÷ ´ ç1 +
÷
wep1 ø è
wep2 ø
è
where
Adc is the error-amplifier (EA) dc gain
(7)
Use Equation 8 to calculate the EA output with compensation capacitor pole (ωep1).
1
wep1 =
R (o) ´ Cz
where
R(o) is the EA output impendence
(8)
The EA higher frequency pole (ωep2 to filter the high-frequency noise, which is higher than whole-loop bandwidth)
is shown in Equation 9.
1
wep2 =
R z ´ Cp
(9)
The EA output ESR zero (ωez1) is shown in Equation 10.
1
wez1 =
R z ´ Cz
(10)
Compensator design should give adequate phase margin (above 45°) at the crossover frequency. A simple
compensator using a single capacitor at the COMP pin adds a dominant pole to the system, which ensures
adequate phase margin if placed low enough. At high duty cycles, the RHP zero places extreme limits on the
achievable bandwidth with this type of compensation. However, because an LED driver is essentially free of
output transients (except catastrophic failures, open or short), the dominant pole approach, even with reduced
bandwidth, is usually the best approach.
7.3.6 LED Open-Circuit Detection
An open LED in any channel interrupts the current flow of that channel. If the LED current in the sensing circuit
falls below the defined threshold thOLED, then the device pulls the DIAGx pin of the affected channel low (for
example, for use as an interrupt to a microcontroller). The output-voltage regulation is with respect to the set
point of the voltage-control loop (resistor divider network on the OVFBx pin). Removal of the failure releases the
DIAGx pin automatically.
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
13
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Feature Description (continued)
7.3.7 Output Short-Circuit and Overcurrent Detection
In case of an external short circuit of a boost output supply line to GND, the respective boost controller of the
affected channel is no longer able to limit the current through the control loop. This is because of the conductive
path from the supply voltage to the shorted output through the inductor and the boost diode.
To protect the external components from excessive currents, the controller of the affected channel interrupts the
path to its output by switching off the high-side PWM-dimming PMOS-FET. The interruption occurs as soon as
the high-side current-sense amplifier detects a common-mode voltage below 4 V, or when the voltage on the
VOUTx pin is below 4 V, or once the high-side current-sense amplifier hits the shorted-output detection threshold
V(OPLED). The protection of each channel operates in this way, independently of the other channel (see statediagram in Figure 14). The device pulls the DIAGx pin of the affected channel high, and the controller of the
affected channel remains in this channel-fail state. In order to reset the controller of the affected channel (for
example, after removal of a short circuit) there must be one disable-and-enable cycle for the affected channel by
pulling the PWMINx pin low for t > t(CH_OFF), and setting it high for t > t(CH_ON).
7.3.8 Measuring LED Current During a Non-Failure Condition
In regular operation mode, one can measure the actual output current of the controller with an external
microcontroller by sensing the voltage at the DIAGx pin. The DIAGx pin voltage between 0.2 V and 2.85 V
represents in a linear relation the output current measured by the current-sense block across the external shunt
resistor. Parameter DIAGfactor gives the scale factor of typically 12.5 (the TPS92601y-Q1 or TPS92602y-Q1
device with 150-mV full-scale current-sense voltage) or 6.25 (the TPS92601A-Q1 or TPS92602A-Q1 device with
300-mV full-scale current-sense voltage). Figure 12 gives the relation between the DIAGx pin voltage and the
current-sense voltage.
VDIAGx
Short Circuit or
Overcurrent Detected
HIGH, 3 V < VDIAG < 3.465 V
Default Working Point
0.2 V to 2.85 V
for VIN > 6 V
Normal Operation
LOW, 0 V < VDIAG < 0.15 V
TPS92601-Q1, TPS92602-Q1: 20 mV*
TPS92601A-Q1, TPS92602A-Q1: 40 mV*
Open LED Detected
225 mV*
450 mV*
150 mV*
300 mV*
VISPx_ISNx
* Approximate voltages
Figure 12. DIAGx Pin Function
When the device is in global shutdown mode (when both PWMINx pins go low for t > t(CH_OFF)), both DIAGx pins
are low.
14
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Feature Description (continued)
7.3.9 LED Dimming Options
The device offers two different approaches to regulate and control the brightness and the color of the LEDs:
analog dimming and PWM dimming.
7.3.9.1 Analog Dimming
An analog voltage applied to the ICTRLx pin allows changing the output current for each channel on the fly from
10%–100% of full-scale. Typically, this approach is used to:
• Reduce the default current in a narrow range to adjust to different binning classes of the LEDs
• Reduce the current at high temperatures (protect LEDs from overtemperature)
• Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply)
Implementing this analog dimming function is possible with an analog approach (discrete resistor and NTC
network) or with a more-flexible approach by using a microcontroller. Internally clamping the maximum voltage
on the ICTRLx pin at 1.5 V simplifies the analog implementation. So applying any higher voltage has no effect on
the output current (which remains at its current set point at 100% of full scale, that is, 150 mV or 300 mV drop at
the external current shunt resistor).
V(ISPx_ISNx)
TPS92601A-Q1, TPS92601-Q1,
TPS92602A-Q1, TPS92602-Q1,
300 mV
150 mV
Linear Analog Dimming
Region
10%–100%
30 mV
15 mV
0 mV
0 mV
150 mV
1.5 V
V(ICTRLx)
Figure 13. Analog Dimming – ICTRLx Pin
7.3.9.2 PWM Dimming
To change the brightness of an LED string by a certain magnitude without affecting the lighting-color of the LED,
it is necessary to use PWM dimming topology. Turning the LEDs ON and OFF at a certain frequency with a
certain duty cycle reduces the brightness without changing the LED current (so not affecting the color).
The integrated high-side PMOS-FET gate driver turns the LED string ON and OFF following the supplied signal
frequency and duty cycle on the PWMIN pin. During the OFF time of the FET, the device stops the internal
control loop by disconnecting the loop internally and then stores the value of the compensation network. This
technique allows fastest recovery of the regulator with the following ON time, as the control loop restarts from the
point at which it stopped. The average LED current during ON time is almost the same as the LED current with
no PWM dimming (duty cycle 100%). For very low duty cycles, the time required by the controller to ramp up the
inductor current form 0 A becomes more significant relative to the overall ON time, leading to lower average
current. So for very low duty cycles, the relation between average current and duty cycle is no longer linear.
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
15
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Feature Description (continued)
One must maintain a minimum on-time in order for PWM dimming to operate in the linear region of its transfer
function. Because of disabling the controller during dimming, the PWM pulse must be long enough that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
boost-to-battery topologies, the minimum ON time (in seconds) for which the PWM dimming operates in the
linear region is:
2 ´ I(LED) ´ V(out) ´ L
t(PWMON _ MIN) =
V(IN)2
(11)
To ensure that the applied dimming-pulse duration matches with the effective dimming-pulse duration, TI
recommends synchronizing the dimming pulses with the switching clock of the boost converter. Choose the
external inductor and output capacitors according to the requirements for the minimum duty cycle.
7.4 Device Functional Modes
7.4.1 Undervoltage and Overvoltage Shutdown
During normal operation (6 V < V(VIN) < 40 V), when the supply voltage at the VIN pin drops below 4 V during
cranking, each boost controller is disabled (when previously in normal operation). As long as the battery voltage
stays above 3.5 V, both PWM dimming FETs are still controllable through the PWMINx pins, and the VCC
regulator is still active. The supply voltage recovering above 4 V re-enables each boost controller (which was
working normally before the supply voltage drop). When supply voltage at the VIN pin drops below 3.5 V, the
device enters standby due to battery undervoltage. From standby mode, re-enabling the device can only occur
when the supply voltage is above 6 V and one or both PWMINx pins are high for t > t(CH_ON)). See the state
diagram in Figure 14. When the supply voltage at the VIN pin goes above 40 V during load-dump, the device
disables both boost controllers due to battery overvoltage, and switches both PWM dimming FETs off. The VCC
regulator is still active. Once the battery voltage is below 40 V, the device recovers from this global failure state
after a global disable-and-enable cycle (active shutdown by pulling both PWMINx pins low for t > t(CH_OFF), and
setting one or both PWMINx pins high for t > t(CH_ON)). See the state diagram in Figure 14.
7.4.2 Overtemperature Shutdown
When the junction temperature rises above 165ºC, both boost controllers are disabled due to junction
overtemperature, and both PWM dimming FETs are switched off. Once the junction temperature is below 145ºC,
the device recovers from this global failure state or a global disable-and-enable cycle (active shutdown by pulling
both PWMINx pins low for t > t(CH_OFF), and setting one or both PWMINx pins high for t > t(CH_ON)). See the state
diagram in Figure 14.
7.4.3 Device State Diagram
Figure 14 shows the state diagram of the device, with a short description of the device behavior in each state.
16
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Device Functional Modes (continued)
Main State Machine
V(VIN) > 6 V AND
Wakeup
Standby
V(VCC) disabled
Both boost controllers
disabled
Both PWM dimming
FETs switched off
Both DIAGx pins low
VIN > 40 V OR
Missing Clock OR
TJ > 165°C
Active
V(VCC) enabled
One or both channels
active (see Active
Sub-State Machine)
Global Failure
VCC enabled
Both boost controllers
disabled
Both PWM dimming
FETs switched off
DIAG1 and 2 pins low
PowerOnReset OR
PowerDown
WakeUp =
.(V
(PWMIN1) = 1 for t > t(CH_ON) OR V(PWMIN2) = 1 for t > t(CH_ON))
PowerDown = .(V(PWMIN1) = 0 for t > t(CH_ON) AND V(PWMIN2) = 0 for t > t(CH_ON))
Missing Clock = RT terminal open AND no sync pulse (CH_ON)
PowerOnReset = V(VIN) < 3.5 V
Active Sub-State Machine
Each channel can independently follow this State Machine.
Low-Voltage
V(PWMINx) = 0 for t > t(CH_OFF)
Boost controller
disabled
PWM dimming FET
controllable through
PWMINx pin
DIAGx pin shows
measured current
Main State ≠ Active
3.5 V < V(VIN) < 4 V
V(VIN) > 6 V
V(VIN) > 6 V AND
V(PWMINx) = 1 for t > t(CH_ON)
OFF
ON
Boost controller
enabled
PWM dimming FET
controllable through
PWMINx terminal
DIAGx terminal shows
measured current
Boost controller
disabled
PWM dimming FET
switched off
DIAGx terminal low
V(PWMINx) = 0 for t > t(CH_OFF)
V(PWMINx) = 0 for t > t(CH_OFF)
Channelx Failure
Detected
Channel-Fail
Boost controller
disabled
PWM dimming FET
switched off
DIAGx terminal high
Channelx Failure Detected = (V (VOUTx) < 4 V OR V(SPSNx_Com) < 4V OR V(SPSNx_Diff) > th(SHOUT))
NOTE: In the case of an open LED on channel x, the DIAGx pin is low, but the boost controller and the PWM
dimming FET of channel x work normally. Hence, the behavior is as in the ON state or the low-voltage state.
Figure 14. Device State Diagram
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
17
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes the application-level considerations when designing with the TPS9260xy-Q1 family of
devices. For corresponding calculations, see the following section.
8.2 Typical Applications
In an application directly connected to a battery, if the application is a passenger car, V(VIN) is from 9 V to 16 V,
and LED forward voltage is always higher than battery, then one can select the boost topology. If the LED
forward voltage is between 9 V and 16 V, boost-to-battery or single-ended primary-inductance converter (SEPIC)
topology is appropriate.
8.2.1 Boost Regulator With Separate or Paralleled Channels
A boost application is appropriate for a situation where V(VIN) is from 9 V to 16 V and LED forward voltage is
always higher than battery the battery voltage. One can use the boost-regulator topology with each channel
driving a separate LED string. For higher-current applications, connect both channels in parallel to drive a single
LED string. The per-channel design parameters and calculations are the same in either case.
18
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Typical Applications (continued)
VBAT
CIN1
L1
VIN
Q1
D1
DIAG1
RSNS1
GDRV1
CO1
COMP1
ISNS1
RLIM1
CHANNEL
1
ICTRL1
PWIN1
ISP1
ISN1
VOUT1
PWMO1
OVFB1
PGND1
ROV1
ROV2
VCC
VBAT
RT
CIN2
TPS92602-Q1
L2
Q1
D2
DIAG2
RSNS2
GDRV2
COMP2
ISNS2
CO2
RLIM2
CHANNEL
2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
PGND2
ICTRL2
PWIN2
ROV3
AGND
ROV4
Figure 15. Boost Regulator (VIN < VO) Simplified Schematic, Separate Channels
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
19
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Typical Applications (continued)
VBAT
CIN1
L1
VIN
Q1
D1
DIAG1
RSNS1
GDRV1
CO1
COMP1
ISNS1
RLIM1
CHANNEL
1
ICTRL1
PWIN1
ISP1
ISN1
VOUT1
PWMO1
OVFB1
PGND1
ROV1
ROV2
VCC
VBAT
CIN2
TPS92602-Q1
RT
L2
Q1
D2
DIAG2
RSNS2
GDRV2
COMP2
ISNS2
CO2
RLIM2
CHANNEL
2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
PGND2
ICTRL2
PWIN2
ROV3
AGND
ROV4
Figure 16. Boost Regulator (VIN < VO) Simplified Schematic, Paralleled Channels
20
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Typical Applications (continued)
LED_B1
LED_B2
D7
J_B1
D1
D8
1
2
D9
1
2
D10
1
2
1
2
VBAT1
R1
464k
OVP1
B150-13-F
0.7V
D2
VBAT2
R2
464k
OVP2
R3
30.0k
White
GND
R4
30.0k
AGND
R5
0.15
AGND
U1
0.1uF
AGND
8
21
DIAG1 5
GND
R7
510
2
C5
0.22uF
C6
270pF
1
PWM1 7
AGND
AGND
LED_B1
VIN
VCC
DIAG1
GDRV1
COMP1
ISNS1
ISP1
ISN1
VOUT1
PWMO1
OVFB1
ICTRL1
PWMIN1
R8
10.0k
PGND1
DIAG2 13
R12
R11
20.0k
12
510
C8
0.22uF
C9
270pF
11
PWM2 9
AGND
AGND
AGND
DIAG2
GDRV2
COMP2
ISNS2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
ICTRL2
PWMIN2
+5V
R13
10.0k
PGND2
4
White
MP_PMOS1
B150-13-F
0.7V
C1
C2
10uF
C3
0.1uF
White
White
RT
GND
PAD
GND
23
25
26
27
28
3 OVP1
24
GND
GND
10uF/50V
100V
J_VBAT1
L_B1
R9
VBAT1
10A
22u
R10
C7
19
J_VBAT2
L_B2
10
VBAT2
D5
10A
22u
D6
C10
10uF/50V
MN_POWER2
OVP2
R14
0.012
18
GND
R16
0.15
6
GND LED_B2
TPS92602-Q1
R15
20.0k
GND
D4
MN_POWER1
D3
10
20
17
16
15
14
10
C4
3.3uF/100V
R6
0.012
22
GND
R17
20.0k
C11
3.3u/100V
MP_PMOS2
R18
0
AGND
AGND
GND
AGND
J_B2
GND
D11
1
D12
2
White
1
D13
2
1
D14
2
White
1
White
2
White
GND
Figure 17. Boost Regulator (VIN < VO) Detailed Schematic
8.2.1.1 Design Requirements
For this boost regulator example, use the following as the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Connect to battery (6 V to 16 V)
Output current per channel (I(setting))
1A
Output voltage
30 V (9 white LEDs)
Input ripple voltage
400 mV
Output ripple current
±10%
Operating frequency
600 kHz
8.2.1.2 Detailed Design Procedure
To
•
•
•
•
•
•
begin the design process, one must decide on a few parameters. The designer must know the following:
Input voltage range
Output current per channel
Output voltage
Input ripple voltage
Output ripple current
Operating frequency
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
21
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
8.2.1.2.1 Switching Frequency
The RT pin resistor sets the switching frequency of the TPS92602y-Q1 device. Use Equation 2 to calculate the
required value for R17. The calculated value is 20.83 kΩ. Use the nearest standard value of 20 kΩ.
8.2.1.2.2 Maximum Output-Current Set Point
The constant output current of the TPS92602y-Q1 device is adjustable by using the external current-shunt
resistor. In the application circuit of Figure 17, R5 is the channel 1 current-shunt resistor, and R16 is the channel2 current shunt resistor. Equation 12 and Equation 13 calculate the resistors that determine maximum output
current.
R(sense) = VSPSN_Diff / I(setting)
R5 = R16 = 150 mV / 1 A = 0.15 Ω
(12)
(13)
8.2.1.2.3 Output Overvoltage-Protection Set Point
The output overvoltage protection threshold of the TPS92602y-Q1 device is externally adjustable using a resistor
divider network. In the application circuit of Figure 17, this divider network comprises R1 and R3 for channel1
and R2 and R4 for channel2. The following equation gives the relationship of the overvoltage-protection
threshold (V(OVPT)) to the resistor divider.
R1 / R3 = R2 / R4 = (V(OVPT) – V(VFB)) / V(VFB)
(14)
The load is nine white LEDs, the forward voltage is about 30 V. For an overvoltage protection margin of 20%,
V(OVPT) is: V(OVPT) = 30 × 1.2 = 36 V. So R1 / R3 = R2 / R4 = (36 – 2.2) / 2.2 = 15.36. Select R3 = R4 = 30 kΩ;
then R1 = R2 = 460 kΩ. Use the nearest standard value of 464 kΩ.
8.2.1.2.4 Duty Cycle Estimation
Estimate the duty cycle of the main switching MOSFET using Equation 15 and Equation 16.
V(OUT) - V(IN- max) + V(FD) 30 V - 16 V + DMIN 0.5 V
D (MIN) »
=
= 47.5%
V(OUT) + V(FD)
30 V + 0.5 V
where
D is the duty cycle in these and all following equations
V(OUT) - V(IN- min) + V(FD) 30 V - 6 V + 0.5 V
D (MAX) »
=
= 80.3%
V(OUT) + V(FD)
30 V + 0.5 V
(15)
(16)
Using an estimated forward drop of 0.5 V for a Schottky rectifier diode, the approximate duty cycle is 47.5%
(minimum) to 80.3% (maximum).
8.2.1.2.5 Inductor Selection
The peak-to-peak ripple is limited to 30% of the maximum output current.
I(OUT- max)
1
I(Lrip- max) = 0.3 ´
= 0.3 ´
= 0.571 A
1 - D (MIN)
1 - 0.475
(17)
Estimate the minimum inductor size using Equation 18.
V(IN- max)
1
16 V
1
L (MIN) >>
´ D (MIN) ´
=
´ 0.475 ´
= 22.1 mH
I(Lrip-max)
f (SW ) 0.571 A
600 kHz
(18)
Select the nearest standard inductor value of 22 µH. Estimate the ripple current using Equation 19.
V(IN)
1
16 V
1
I(RIPPLE) »
´ D (MIN) ´
=
´ 0.475 ´
= 0.575 A
L
f (SW ) 22 mH
600 kHz
(19)
I(RIPPLE-Vinmin) »
V(IN)
L
´ D (MIN) ´
1
f (SW )
6V
1
=
´ 0.475 ´
= 0.365 A
22 mH
600 kHz
(20)
The worst-case peak-to-peak ripple current occurs at 47.5% duty cycle and is estimated as 0.575 A. Equation 21
estimates the worst-case rms current through the inductor.
22
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
2
I(Lrms)
2
2
æ I(OUT- max) ö æ 1
æé 1
ùö
ö
= (I(L-avg) ) + ç ê ´ I(RIPPLE) ú ÷ » ç
÷ + ç ´ I(RIPPLE-Vinmin) ÷
ç
÷
ûø
ø
è ë12
è 1 - D (MAX) ø è 12
2
2
æ 1A ö æ 1
ö
= ç
+ ç ´ 0.365 A ÷ = 5.08 A rms
÷
è 1 - 0.803 ø è 12
ø
(21)
The worst-case rms inductor current is 5.08 A rms. Equation 22 estimates the peak inductor current.
I(OUT- max) 1
1
I(Lpeak) »
+ ´ I(RIPPLE- Vinmin) =
+ 0.5 ´ 0.365 = 5.26 A
1 - D (MAX) 2
1 - 0.083
(22)
Select a 22-µH inductor with a minimum rms current rating of 5.08 A and minimum saturation current rating of
5.26 A. The selection is a Wurth 74435572200 inductor (shielded-drum core, ferrite, 22 µH, 11 A, 0.0146 Ω,
SMD).
Equation 23 estimates the power dissipation of this inductor
P(L) » (I(Lrms) )2 ´ DCR
(23)
The Wurth 74435572200 inductor with 14.6-mΩ DCR dissipates 404 mW of power.
8.2.1.2.6 Rectifier Diode Selection
The circuit uses a low-forward-voltage-drop Schottky diode as a rectifier diode to reduce power dissipation and
improve efficiency. Use 80% derating for the diode on VOUTx to allow for for ringing on the switch node.
Equation 24 gives the rectifier-diode minimum reverse-breakdown voltage.
V(VOPT)
V(BR)(R- min) ³
= 1.25 ´ 36 V = 45 V
0.8
(24)
The diode must have a reverse-breakdown voltage greater than 45 V. Equation 25 and Equation 26 estimate the
rectifier diode peak and average currents.
I(D-avg) » I(OUT- max) = 1 A
(25)
I(D-peak) = I(L-peak) = 5.26 A
(26)
For this design, average current is 1 A and peak current is 5.26 A.
Equation 27 estimates the power dissipation in the diode.
P(D- max) » V(F) ´ I(OUT- max) = 0.5 V ´ 1 A = 0.5 W
(27)
For this design, the maximum power dissipation is estimated as 0.5 W. After reviewing 45-V and 60-V Schottky
diodes, the selection is the 30BQ060PbF diode, Schottky, 60 V, 3 A, SMC. This diode has a forward voltage drop
of 0.5 V at 1 A, so the conduction power dissipation is approximately 500 mW, less than half its rated power
dissipation.
8.2.1.2.7 Output Capacitor Selection
Assume a maximum LED current ripple of 0.1 × I(LED). Also, assume that the dynamic impedance of the chosen
LED is 0.2 Ω (1.8 Ω total for the nine-LED string). The total output-voltage ripple calculation is then as per
Equation 28.
V(VOUT-ripple) = 0.1 A ´ 1.8 W = 180 mV
(28)
Assuming a ripple contribution of 95% from bulk capacitance, Equation 29 calculates the output capacitor.
I(OUT) ´ D
æ 1 A ´ 0.803 ö
1
1
C (OUT) =
´
=ç
= 7.83 mF
÷´
V(VOUT-ripple) ´ 0.95 f (SW ) è 180 mV ´ 0.95 ø 600 kHz
ESR =
V(VOUT-ripple)
I(L-peak)
=
9 mV
= 1.71 mW
5.26 A
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
(29)
(30)
Submit Documentation Feedback
23
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
Use three 3.3-μF capacitors in parallel to achieve the minimum output capacitance of 10 μF. Ensure that the
chosen capacitors meet the minimum bulk capacitance requirement at the operating voltage.
8.2.1.2.8 Input Capacitor Selection
Because a boost converter has continuous input current, the input capacitor senses only the inductor ripple
current. Equation 31 and Equation 32 calculate the input capacitor values.
I(L-RIPPLE)
0.575 A
C (IN) =
=
= 4 mF
4 ´ v (IN-RIPPLE) ´ f (SW ) 4 ´ 60 mV ´ 600 kHz
(31)
ESR =
V(VIN-RIPPLE)
I(L-RIPPLE)
=
60 mV
= 52 mW
2 ´ 0.575 A
(32)
For this design, to meet a maximum input ripple of 60 mV requires a minimum 4-µF input capacitor with ESR
less than 52 mΩ. Select a 10-µF X7R ceramic capacitor.
8.2.1.2.9 Current Sense and Current Limit
The maximum allowable current sense resistor value is limited by R(ISNSx). Equation 33 gives this limitation.
V(SNS)
100 mV
R (ISNSx) =
=
= 14.62 mW
1.3 ´ I(L-peak) 1.3 ´ 5.26 A
(33)
Select a 15-mΩ resistor.
8.2.1.2.10 Switching MOSFET Selection
The TPS92602y-Q1 device drives a ground-referenced N-channel FET. The breakdown voltage is the output
voltage plus any voltage spike, with 30% added for a safety margin as shown in Equation 34.
V(BD-MOS- min) ³ V(VOPT) ´ 1.3 = 1.3 ´ 36 V = 46.8 V
(34)
Select an N-channel FET with breakdown voltage of 50 V.
Estimate the rDS(on) and gate charge based on the desired efficiency target.
æ1 ö
æ 1
ö
P(DISS-total) » P(OUT) ´ ç - 1÷ = 30 V ´ 1 A ´ ç
- 1÷ = 1.578 W
è 0.95 ø
èh ø
(35)
For a target of 95% efficiency with a 16-V input voltage at 1 A, maximum power dissipation is limited to 1.578 W.
The main power-dissipating devices are the MOSFET, inductor, diode, current-sense resistor and the integrated
circuit, the TPS92602y-Q1 device.
P(FET) < P(DISS-total) - P(L) - P(D) - P(RSNS) - V(IN- max) ´ I(VDD)
(36)
This assumption leaves 740 mW of power dissipation for the MOSFET. Allowing half for conduction and half for
switching losses, we can determine a target rDS(on) and Q(GS) for the MOSFET by Equation 37 and Equation 38.
3 ´ P(FET) ´ I(DRIVE)
3 ´ 0.5 W ´ 0.7 A
Q (GS) <
=
= 29.2 nC
2 ´ V(OUT) ´ I(OUT) ´ f (SW ) 2 ´ 30 V ´ 1 A ´ 600 kHz
(37)
Calculate a target MOSFET gate-to-source charge of less than 29.2 nC to limit the switching losses to less than
250 mW.
P(FET)
0.5 W
rDS(on) <
=
= 12 mW
2
2
2 ´ I(RMS) ´ D 2 ´ (5.08 A) ´ 0.803
(
)
(38)
Selecting a target MOSFET rDS(on) of 12 mΩ limits the conduction losses to less than 250 mW.
24
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
8.2.1.2.11 Loop Compensation
The COMP pin on the TPS92602y-Q1 device is for external compensation, allowing optimization of the loop
response for each application. The COMP pin is the output of the internal transconductance amplifier. External
resistor R7, along with ceramic capacitors C5 and C6 (see Figure 17 ), connect to the COMP pin to provide
poles and zero. The poles and zero, along with the inherent pole and zero in a peak-current-mode control boost
converter, determine the closed-loop frequency response. Thhis connection is important to converter stability and
transient response. The first step is to calculate the pole and the right half-plane zero of the peak-current-mode
boost converter by Equation 39 and Equation 40. To make the loop stable, the loop must have sufficient phase
margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half-plane zero on
loop stability, choose a crossover frequency less than 1/5 of f(ZRHP).
I(OUT)
1
f (p) =
=
2p ´ V(OUT) ´ C(OUT) 2p ´ R (OUT) ´ C(OUT)
where
•
•
C(OUT) is the bulk output capacitance calculated previously
R(OUT) is the effective output impedance
(39)
2
f (ZRHP) =
R (OUT) =
V(OUT) ´ (1 - D)
2p ´ L ´ I(OUT)
(40)
(R (LED) + R (SENSE) ) ´ V(LED)
(R (LED) + R (SENSE) ) ´ I(LED) + V(LED)
where
R(LED) is the dynamic impedance of the LED string in ohms at the operating current
(41)
The loop compensation consists of a series resistor and capacitor (R(COMP) and C(COMP)) from COMP to SGND.
R(COMP) sets the crossover frequency and C(COMP) sets the zero frequency of the integrator. For optimum
performance, use the following equations:
gM(COMP) = 1000
R (COMP) =
C (COMP) =
(42)
f (ZRHP) ´ R (ISNSx)
5 ´ f (p) ´ (1 - D(MAX) ) ´ R (SENSE) ´ 5 ´ GM(COMP)
(43)
1
2p ´ R (COMP) ´ 5 ´ f (p)
where
f(p) is the pole frequency of the power stage calculated by Equation 39
(44)
An output capacitor that is an electrolytic capacitor which has large ESR requires a capacitor to cancel the zero
of the output capacitor. Equation 45 calculates the value of this capacitor.
C (OUT) ´ R (ESR)
C6 =
R (COMP)
(45)
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
25
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
8.2.1.3 Application Curves
26
Figure 18. PWM Dimming at 200 Hz, 5% Duty Cycle
Figure 19. PWM Dimming at 200 Hz, 50% Duty Cycle
Figure 20. PWM Dimming at 200 Hz, 95% Duty Cycle
Figure 21. Switching and LED Current Ripple
When I(OUT) = 1 A
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
8.2.2 Boost-to-Battery Regulator
When the LED forward voltage is between 9 V and 16 V, an appropriate selection is boost-to-battery topology,
which can share the same layout and components as the boost topology, with just a different way to connect
load.
VBAT
CIN1
L1
CO1
VIN
Q1
D1
DIAG1
RSNS1
GDRV1
COMP1
ISNS1
RLIM1
CHANNEL
1
ICTRL1
PWIN1
ISP1
ISN1
VOUT1
PWMO1
OVFB1
PGND1
ROV1
ROV2
VCC
VBAT
RT
TPS92602-Q1
L2
CIN2
CO2
Q1
D2
DIAG2
RSNS2
GDRV2
COMP2
ISNS2
RLIM2
CHANNEL
2
ICTRL2
AGND
PWIN2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
PGND2
ROV3
ROV4
Figure 22. Boost-to-Battery Regulator Simplified Schematic
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
27
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
D7
D8
1
LED_B1
LED_B2
J_B1
2
1
D10
1
White
White
D1
D9
2
2
1
White
2
White
VBAT1
R1
464k
OVP1
B150-13-F
0.7V
D2
VBAT2
R2
464k
OVP2
R3
30.0k
MP_PMOS1
R4
30.0k
B150-13-F
0.7V
C1
AGND
R5
0.15
AGND
U1
C2
10uF
C3
0.1uF
0.1uF
AGND
8
21
DIAG1 5
GND
R7
510
2
C5
0.22uF
C6
270pF
1
PWM1 7
AGND
AGND
LED_B1
VIN
VCC
DIAG1
GDRV1
COMP1
ISNS1
ISP1
ISN1
VOUT1
PWMO1
OVFB1
ICTRL1
PWMIN1
R8
10.0k
PGND1
DIAG2 13
R12
R11
20.0k
12
510
C8
0.22uF
C9
270pF
11
PWM2 9
AGND
AGND
AGND
DIAG2
GDRV2
COMP2
ISNS2
ISP2
ISN2
VOUT2
PWMO2
OVFB2
ICTRL2
PWMIN2
+5V
R13
10.0k
PGND2
4
RT
GND
PAD
GND
23
25
26
27
28
3 OVP1
24
GND
GND
D3
10uF/50V
100V
J_VBAT1
L_B1
R9
VBAT1
5.3A
22u
R10
C7
L_B2
10
19
D5
VBAT2
J_VBAT2
5.3A
22u
D6
C10
10uF/50V
MN_POWER2
OVP2
R14
0.020
18
GND
R16
0.15
6
GND LED_B2
TPS92602-Q1
R15
20.0k
GND
D4
MN_POWER1
10
20
17
16
15
14
10
C4
16.2uF/45V
R6
0.020
22
GND
R17
20.0k
MP_PMOS2
R18
0
C11
16.2u/45V
AGND
AGND
GND
AGND
J_B2
GND
D11
1
D12
2
D13
1
2
1
White
White
D14
2
White
1
2
White
Figure 23. Boost-to-Battery Regulator Detailed Schematic
8.2.2.1 Design Requirements
For this boost-to-battery regulator example, use the following as the design parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Connect to battery (6 V to 16 V)
Output current per channel (I(setting))
1A
Output voltage
13.2 V (4 white LEDs)
Input ripple voltage
400 mV
Output ripple current
±10%
Operating frequency
600 kHz
8.2.2.2 Detailed Design Procedure
To
•
•
•
•
•
•
28
begin the design process, one must decide on a few parameters. The designer must know the following:
Input voltage range
Output current per channel
Output voltage
Input ripple voltage
Output ripple current
Operating frequency
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
8.2.2.2.1 Switching Frequency
The RT pin resistor sets the switching frequency of the TPS92602y-Q1 device to 600 kHz. Use Equation 2 to
calculate the required value for R17. The calculated value is 20.83 kΩ. Use the nearest standard value of 20 kΩ.
8.2.2.2.2 Maximum Output-Current Set Point
The output constant of the TPS92602y-Q1 device is adjustable by using the external current-shunt resistor. In
the application circuit of Figure 23, R5 is the channel 1 current-shunt resistor, and R16 is the channel-2 current
shunt resistor. Equation 46 and Equation 47 calculate the resistors that determine maximum output current.
R(sense) = VSPSN_Diff / I(setting)
R5 = R16 = 150 mV / 1 A = 0.15 Ω
(46)
(47)
8.2.2.2.3 Output Overvoltage-Protection Set Point
The output overvoltage protection threshold of the TPS92602y-Q1 device is externally adjustable using a resistor
divider network. In the application circuit of Figure 23, this divider network comprises of R1 and R3 for channel1
and R2 and R4 for channel2. The following equation gives the relationship of the overvoltage-protection
threshold (V(OVPT)) to the resistor divider.
R1 / R3 = R2 / R4 = (V(OVPT) – V(VFB)) / V(VFB)
(48)
The load is four white LEDs, the forward voltage is about 13.2 V, maximum V(VIN) is 16 V, so the maximum
output is 13.2 + 16 = 29.2 V, which is close to 30 V. Allowing 20% margin for overvoltage protection, V(OVPT) is:
V(OVPT) = 30 × 1.2 = 36 V. So R1 / R3 = R2 / R4 = (36 – 2.2) / 2.2 = 15.36. Select R3 = R4 = 30 kΩ; then R1 =
R2 = 460 kΩ. Use the nearest standard value of 464 kΩ.
8.2.2.2.4 Duty Cycle Estimation
Estimate the duty cycle of the main switching MOSFET using Equation 49 and Equation 50.
V(LED) + V(FD)
13.2 V + 0.5 V
D (MIN) »
=
= 46.1%
V(LED) + V(MAX) + V(FD) 30 V + 16 V + 0.5 V
where
D is the duty cycle in these and all following equations
V(LED) + V(FD)
13.2 V + 0.5 V
D (MAX) »
=
= 69.5%
V(LED) + V(MIN) + V(FD) 13.2 V + 6 V + 0.5 V
(49)
(50)
Using an estimated forward drop of 0.5 V for a Schottky rectifier diode, the approximate duty cycle is 46.1%
(minimum) to 69.5% (maximum).
8.2.2.2.5 Inductor Selection
The peak-to-peak ripple is limited to 30% of the maximum output current.
I(OUT- max)
1
I(Lrip- max) = 0.3 ´
= 0.3 ´
= 0.556 A
1 - D (MIN)
1 - 0.461
(51)
Estimate the minimum inductor size using Equation 52
V(IN- max)
1
16 V
1
L (MIN) >>
´ D (MIN) ´
=
´ 0.475 ´
= 22.1 mH
I(Lrip-max)
f (SW ) 0.571 A
600 kHz
(52)
Select the nearest higher standard inductor value of 22 µH. Estimate the ripple current using Equation 53.
V(IN)
1
16 V
1
I(RIPPLE) »
´ D (MIN) ´
=
´ 0.461´
= 0.559 A
L
f (SW ) 22 mH
600 kHz
(53)
I(RIPPLE-Vinmin) »
V(IN)
L
´ D (MIN) ´
1
f (SW )
6V
1
=
´ 0.695 ´
= 0.316 A
22 mH
600 kHz
(54)
The worst-case peak-to-peak ripple current occurs at 46.1% duty cycle and is estimated as 0.559 A. Equation 55
estimates the worst-case rms current through the inductor.
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
29
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
2
I(Lrms)
2
2
æ I(OUT- max) ö æ 1
æé 1
ùö
ö
= (I(L-avg) ) + ç ê ´ I(RIPPLE) ú ÷ » ç
÷ + ç ´ I(RIPPLE-Vinmin) ÷
ç
÷
ûø
ø
è ë12
è 1 - D (MAX) ø è 12
2
2
æ 1A ö æ 1
ö
= ç
+ ç ´ 0.3316 A ÷ = 3.28 A rms
÷
è 1 - 0.695 ø è 12
ø
(55)
The worst-case rms inductor current is 3.28 A rms. Equation 56 estimates the peak inductor current.
I(OUT- max) 1
1
I(Lpeak) »
+ ´ I(RIPPLE- Vinmin) =
+ 0.5 ´ 0.316 = 3.44 A
1 - D (MAX) 2
1 - 0.695
(56)
Select a 22-µH inductor with a minimum rms current rating of 3.44 A and minimum saturation current rating of
3.44 A. The selection is a Wurth 7447709220 inductor (shielded-drum core, ferrite, 22 µH, 5.3 A, 0.0233 Ω,
SMD).
Equation 57 estimates the power dissipation of this inductor
P(L) » (I(Lrms) )2 ´ DCR
(57)
The Wurth 7447709220 inductor with 23.3-mΩ DCR dissipates 251 mW of power.
8.2.2.2.6 Rectifier Diode Selection
The circuit uses a low-forward-voltage-drop Schottky diode as a rectifier diode to reduce power dissipation and
improve efficiency. Use 80% derating for the diode on VOUTx to allow for ringing on the switch node.
Equation 58 gives the rectifier-diode minimum reverse-breakdown voltage.
V(VOPT)
V(BR)(R- min) ³
= 1.25 ´ 36 V = 45 V
0.8
(58)
The diode must have a reverse-breakdown voltage greater than 45 V. Equation 59 and Equation 60 estimate the
rectifier diode peak and average currents.
I(D-avg) » I(OUT- max) = 1 A
(59)
I(D-peak) = I(L-peak) = 3.44 A
(60)
For this design, average current is 1 A and peak current is 3.44 A.
Equation 61 estimates the power dissipation in the diode.
P(D- max) » V(F) ´ I(OUT- max) = 0.5 V ´ 1 A = 0.5 W
(61)
For this design, the maximum power dissipation is estimated as 0.5 W. After reviewing 45-V and 60-V Schottky
diodes, the selection is the 30BQ060PbF diode, Schottky, 60 V, 3 A, SMC. This diode has a forward voltage drop
of 0.5 V at 1 A, so the conduction power dissipation is approximately 500 mW, less than half its rated power
dissipation.
8.2.2.2.7 Output Capacitor Selection
Assume a maximum LED current ripple of 0.1 × I(LED). Also, assume that the dynamic impedance of the chosen
LED is 0.2 Ω (0.8 Ω total for the four-LED string). The total output voltage ripple calculation is then as per
Equation 62.
V(VOUT-ripple) = 0.1 A ´ 0.8 W = 80 mV
(62)
Assuming a ripple contribution of 95% from bulk capacitance, Equation 64 calculates the output capacitor.
I(OUT) ´ D
æ 1 A ´ 0.695 ö
1
1
C (OUT) =
´
=ç
= 15.2 mF
÷´
V(VOUT-ripple) ´ 0.95 f (SW ) è 80 mV ´ 0.95 ø 600 kHz
ESR =
30
V(VOUT-ripple)
I(L-peak)
=
4 mV
= 1.16 mW
3.44 A
Submit Documentation Feedback
(63)
(64)
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
Use five 3.3-μF capacitors in parallel to achieve the minimum output capacitance of 15.2 μF. Ensure that the
chosen capacitors meet the minimum bulk capacitance requirement at the operating voltage.
8.2.2.2.8 Input Capacitor Selection
Because a boost converter has continuous input current, the input capacitor senses only the inductor ripple
current. The input capacitor value can be calculated by Equation 65 and Equation 66.
I(L-RIPPLE)
0.559 A
C (IN) =
=
= 3.89 mF
4 ´ v (IN-RIPPLE) ´ f (SW ) 4 ´ 60 mV ´ 600 kHz
(65)
ESR =
V(VIN-RIPPLE)
I(L-RIPPLE)
=
60 mV
= 53.67 mW
2 ´ 0.559 A
(66)
For this design, to meet a maximum input ripple of 60 mV requires a minimum 4-µF input capacitor with ESR
less than 52 mΩ. Select a 10-µF X7R ceramic capacitor.
8.2.2.2.9 Current Sense and Current Limit
The maximum allowable current sense resistor value is limited by R(ISNSx). Equation 67 gives this limitation.
V(SNS)
100 mV
R (ISNSx) =
=
= 22.36 mW
1.3 ´ I(L-peak) 1.3 ´ 3.44 A
(67)
Select a 20-mΩ resistor.
8.2.2.2.10 Switching MOSFET Selection
The TPS92602y-Q1 device drives a ground-referenced N-channel FET. The breakdown voltage is the output
voltage plus any voltage spike, with 30% added for a safety margin as shown in Equation 68.
V(BD-MOS- min) ³ V(VOPT) ´ 1.3 = 1.3 ´ 36 V = 46.8 V
(68)
Select an N-channel FET with breakdown voltage of 50 V.
Estimate the rDS(on) and gate charge based on the desired efficiency target.
æ1 ö
æ 1
ö
P(DISS-total) » P(OUT) ´ ç - 1÷ = 13.2 V ´ 1 A ´ ç
- 1÷ = 1.148 W
è 0.92 ø
èh ø
(69)
For a target of 92% efficiency with a 16-V input voltage at 1 A, maximum power dissipation is limited to 1.148 W.
The main power-dissipating devices are the MOSFET, inductor, diode, current-sense resistor and the integrated
circuit, the TPS92602y-Q1 device.
P(FET) < P(DISS-total) - P(L) - P(D) - P(RSNS) - V(IN- max) ´ I(VDD)
(70)
This assumption leaves 600 mW of power dissipation for the MOSFET. Allowing half for conduction and half for
switching losses, we can determine a target rDS(on) and Q(GS) for the MOSFET by Equation 71 and Equation 72.
3 ´ P(FET) ´ I(DRIVE)
3 ´ 0.4 W ´ 0.7 A
Q (GS) <
=
= 28.3 nC
2 ´ V(OUT) ´ I(OUT) ´ f (SW ) 2 ´ 13.2 V ´ 1 A ´ 600 kHz
(71)
Calculate a target MOSFET gate-to-source charge of less than 28.3 nC to limit the switching losses to less than
200 mW.
P(FET)
0.4 W
rDS(on) <
=
= 26.7 mW
2
2
2 ´ I(RMS) ´ D 2 ´ (3.28 A) ´ 0.695
(
)
(72)
Selecting a target MOSFET rDS(on) of 26.7 mΩ limits the conduction losses to less than 250 mW.
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
31
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
8.2.2.2.11 Loop Compensation
The COMP pin on the TPS92602y-Q1 device is for external compensation, allowing optimization of the loop
response for each application. The COMP pin is the output of the internal transconductance amplifier. The
external resistor R7, along with ceramic capacitors C5 and C6 (see Figure 23 ), connect to the COMP pin to
provide poles and zero. The poles and zero, along with the inherent pole and zero in a peak-current-mode
control boost converter, determine the closed-loop frequency response. This is important to converter stability
and transient response. The first step is to calculate the pole and the right half-plane zero of the peak-currentmode boost converter by Equation 73 and Equation 74. To make the loop stable, the loop must have sufficient
phase margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half-plane zero
on the loop stability, choose the crossover frequency less than 1/5 of f(ZRHP).
I(OUT)
1
f (p) =
=
2p ´ V(OUT) ´ C(OUT) 2p ´ R (OUT) ´ C(OUT)
where
•
•
C(OUT) is the bulk output capacitance previously calculated
R(OUT) is the effective output impedance
(73)
2
f (ZRHP) =
R (OUT) =
V(OUT) ´ (1 - D)
2p ´ L ´ I(OUT)
(74)
(R (LED) + R (SENSE) ) ´ V(LED)
(R (LED) + R (SENSE) ) ´ I(LED) + V(LED)
where
R(LED) is the dynamic impedance of the LED string in ohms at the operating current
(75)
The loop compensation consists of a series resistor and capacitor (R(COMP) and C(COMP)) from COMP to SGND.
R(COMP) sets the crossover frequency and C(COMP) sets the zero frequency of the integrator. For optimum
performance, use the following equations:
gM(COMP) = 1000
R (COMP) =
C (COMP) =
(76)
f (ZRHP) ´ R (ISNSx)
5 ´ f (p) ´ (1 - D(MAX) ) ´ R (SENSE) ´ 5 ´ GM(COMP)
(77)
1
2p ´ R (COMP) ´ 5 ´ f (p)
where
f(p) is the pole frequency of the power stage calculated by Equation 73
(78)
An output capacitor that is an electrolytic capacitor which has large ESR requires a capacitor to cancel the zero
of the output capacitor. Equation 79 calculates the value of this capacitor.
C (OUT) ´ R (ESR)
C6 =
R (COMP)
(79)
32
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
8.2.2.3 TPS92602y-Q1 Application Curves
Figure 24. PWM Dimming at 2 kHz, 5% Duty Cycle
Figure 25. PWM Dimming at 2 kHz, 50% Duty Cycle
Figure 26. PWM Dimming at 2 kHz, 95% Duty Cycle
Figure 27. Switching and LED Current Ripple
When I(OUT) = 1 A
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
33
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
9 Power Supply Recommendations
The design of the devices is for operation via direct connection to a battery, so the input-voltage supply range is
from 4 V to 40 V. This input supply should be well regulated. If the input supply is located more than a few inches
from the TPS9260xy-Q1 family of devices, additional bulk capacitance may be required in addition to the ceramic
bypass capacitors.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
34
The performance of any switching regulator depends as much on the layout of the PCB as the component
selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing the
following paths. The main path for discontinuous current in the TPS9260xy-Q1 buck regulator contains the
input capacitor (CIN1), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor
(RLIM1). In the TPS9260xy-Q1 boost regulator, the discontinuous current flows through the output capacitor
(CO1), D1, Q1, and RLIM1. In the buck-boost regulator, both loops are discontinuous and require careful
attention to layout. Keep these loops as small as possible and the connections between all the components
short and thick to minimize parasitic inductance. In particular, make the switch node (where L1, D1 and Q1
connect) just large enough to connect the components. To minimize excessive heating, place large copper
pours adjacent to the short current path of the switch node.
The RT, COMP, ISNS, ICTRL, OVFB, ISP, and ISN pins are all high-impedance inputs which couple external
noise easily; therefore, minimize the loops containing these nodes whenever possible. In some applications,
the LED or LED array can be far away (several inches or more) from the TPS9260xy-Q1 family of devices, or
on a separate PCB connected by a wiring harness. When using an output capacitor where the LED array is
large or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the
effects of parasitic inductance on the ac impedance of the capacitor.
AGND and PGND must be separated and connected at the input GND connector.
The TPS9260xy-Q1 family of devices has two independent channels. in order to avoid crosstalk, the POWER
GND of CH1 and CH2 must be separated and connected at the input GND connector.
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
TPS92601-Q1, TPS92602-Q1
www.ti.com
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
10.2 Layout Example
Via of Signal Loop
Via of Power Ground
Exposed
Thermal
Pad Area
Trace on the top
Trace on the bottom
For high-current paths, (thick traces on the diagram) keep loops as
small as possible and the connections between all the components
short and thick to minimize parasitic inductance.
Via of Signal Ground
Cpx
1
ICTRL1
PWMO1
28
2
COMP1
VOUT1
27
3
OVFB1
ISN1
26
ISP1
25
PGND1
24
ISNS1
23
GDRV1
22
VCC
21
GDRV2
20
VBAT
Rzx
Czx
CVIN
4
RT
5
DIAG1
6
GND
7
PWMIN1
8
VIN
9
PWMIN2
TPS92602-Q1
TPS92602A-Q1
Current limit resistor GND
connected to PGND1
terminal with separate trace
Separate the PGGNDx of both channels and connect to VCC GND.
VBAT
10
OVFB2
ISNS2
19
11
ICTRL2
PGND2
18
12
COMP2
ISP2
17
13
DIAG2
ISN2
16
14
PWMO2
VOUT2
15
Power Ground on Bottom Layer
Signal Ground on Bottom Layer
Figure 28. TPS92602y-Q1 Board Layout
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
Submit Documentation Feedback
35
TPS92601-Q1, TPS92602-Q1
SLUSBP5E – MARCH 2014 – REVISED JULY 2018
www.ti.com
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS92601-Q1
Click here
Click here
Click here
Click here
Click here
TPS92601B-Q1
Click here
Click here
Click here
Click here
Click here
TPS92602-Q1
Click here
Click here
Click here
Click here
Click here
TPS92602B-Q1
Click here
Click here
Click here
Click here
Click here
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
36
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS92601-Q1 TPS92602-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS92601BQPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
92601B
TPS92601QPWPRQ1
NRND
HTSSOP
PWP
20
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
92601
TPS92602BQPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS92602B
TPS92602QPWPRQ1
NRND
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS92602
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
