TPSM82816
SLUSEY7 – DECEMBER 2022
TPSM82816 2.7-V to 6-V Input 6-A Step-Down MicroSiP™ Power Module with
Integrated Inductor and Frequency Synchronization
1 Features
3 Description
•
TPSM82816 is part of a family of pin-to-pin 3-A, 4-A
and 6-A compatible high efficiency and easy to use
synchronous step-down DC/DC power modules with
integrated inductors. The devices are based on a
fixed-frequency peak current-mode control topology.
The devices are used in telecommunication, test and
measurement, and medical applications with high
power density and ease of use requirements. Low
resistance switches allow up to 6-A continuous output
current at high ambient temperatures. The switching
frequency is externally adjustable from 1.8 MHz to
4 MHz and can also be synchronized to an external
clock in the same frequency range. In Power Save
Mode, the TPSM82816 automatically enters PFM at
light loads to maintain high efficiency across the
whole load range. The TPSM82816 provides a 1%
output voltage accuracy in PWM mode which helps
design a power supply with high output voltage
accuracy. The SS/TR pin sets the start-up time or
tracks the output voltage to an external source. This
allows external sequencing of different supply rails
and limits the inrush current during start-up.
•
•
•
•
•
•
2 Applications
•
•
•
•
•
Optical modules, data center interconnect
Signal measurement, source generation,
instrumentation
Patient monitoring and diagnostics
Wireless infrastructure
Ruggedized Communication: sensors, imaging,
and radar
Package Information
PART NUMBER
TPSM82816
(1)
VOUT
VIN
R1
FB
R2
External sync (optional)
COMP/FSET
SS/TR
RCF
CSS
PG
GND
Schematic
SIE (uSiP, 14)
For all available packages, see the orderable addendum at
the end of the data sheet.
90
CFF
85
EN
MODE/SYNC
BODY SIZE (NOM)
3.0 mm × 4.0 mm × 1.6
mm
95
VOUT
CIN
22 µF
PACKAGE(1)
100
TPSM82816
VOUT
2.7 V - 6 V
R3
COUT
2 × 47 µF
Efficiency (%)
•
•
•
•
•
•
•
•
Adjustable and synchronizable switching
frequency of 1.8 MHz to 4 MHz
Spread spectrum clocking (optional)
Selectable forced PWM or PFM/PWM operation
Output voltage accuracy ±1% (PWM operation)
Input voltage range: 2.7 V to 6 V
Output voltage range: 0.6 V to 5.5 V
Adjustable soft-start or tracking
Power-good output with window comparator
Precise ENABLE input allows
– User-defined undervoltage lockout
– Exact sequencing
100% duty cycle
Output discharge
26-µA typical quiescent current
Pin to Pin compatible with TPSM82813 (3A) and
TPSM82810 (4A)
Excellent thermal performance
–40°C to 125°C operating temperature range
80
75
70
65
60
55
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
50
FPWM
PSM
45
40
100u
1m
10m
100m
Output Current (A)
1
Efficiency vs Output Current; VIN = 5 V;
fSW = 1.8 MHz; TA = 25 °C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
6
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
9.3 System Examples..................................................... 21
9.4 Power Supply Recommendations.............................22
9.5 Layout....................................................................... 23
10 Device and Documentation Support..........................25
10.1 Device Support....................................................... 25
10.2 Documentation Support.......................................... 25
10.3 Receiving Notification of Documentation Updates..25
10.4 Support Resources................................................. 25
10.5 Trademarks............................................................. 25
10.6 Electrostatic Discharge Caution..............................25
10.7 Glossary..................................................................25
11 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2022
*
Initial Release
5 Device Comparison Table
2
DEVICE NUMBER
OUTPUT CURRENT
SPREAD SPECTRUM CLOCKING
TPSM82816SIER
6A
Set by COMP / FSET pin
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6 Pin Configuration and Functions
TOP VIEW
COMP
/FSET
6
14
GND 13
VIN
11
VIN 12
PG
3
2
GND
5
VOUT
5
8
9
GND 13
GND 14
12
VIN 11
VIN
VOUT
4
7
FB
MODE
/SYNC
EN
6
GND
GND
VIN
1
7
FB
MODE
/SYNC
GND
8
COMP
/FSET
SS/TR
9
SS/TR
10
BOTTOM VIEW
4
PG
3
EN
2
10
GND
VIN
1
Figure 6-1. uSiP 14-pin SIE Package
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
2
I
This pin is the enable pin of the device. Connect to logic low to disable the device. Pull high
to enable the device. Do not leave this pin unconnected.
FB
7
I
Voltage feedback input. Connect the output voltage resistor divider to this pin.
GND
MODE/SYNC
6, 10, 13, 14
4
Ground pin
I
The device runs in PSM (auto PFM/PWM transition) mode when this pin is pulled low.
When the pin is pulled high, the device runs in forced PWM mode. Do not leave this pin
unconnected. The MODE/SYNC pin can also be used to synchronize the device to an
external frequency. See Synchronizing to an External Clock.
COMP/FSET
9
I
Device compensation and frequency set input. A resistor from this pin to GND defines
the compensation of the control loop as well as the switching frequency if not externally
synchronized. The switching frequency is set to 2.25 MHz if the pin is tied to GND or VIN.
Spread spectrum is also enabled and disabled by this pin. See COMP/FSET. Do not leave
this pin unconnected.
PG
3
O
Open-drain power-good output with window comparator. This pin is pulled to GND while
VOUT is outside the power-good threshold. This pin can be left open or tied to GND if not
used. A pullup resistor can be connected to any voltage not larger than VIN.
SS/TR
8
I
Soft-start, tracking pin. A capacitor connected from this pin to GND defines the output
voltage rise time. The pin can also be used as an input for tracking and sequencing - see
Voltage Tracking.
VOUT
5
VIN
1, 11, 12
Output voltage pin. This pin is internally connected to the integrated inductor.
Power supply input. Connect the input capacitor as close as possible between the VIN and
GND pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
Pin
voltage(2)
Pin voltage(2)
Pin
voltage(2)
MIN
MAX
VIN, EN, MODE/SYNC
–0.3
6.5
V
FB
–0.3
4
V
COMP/FSET, PG, SS/TR, VOUT
–0.3
VIN + 0.3
ISINK_PG
Sink Current at PG pin
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
(2)
UNIT
V
10
mA
–40
125
°C
–40
125
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to the network ground terminal
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.7
6
V
VOUT
Output voltage range
0.6
5.5
V
IOUT
Output current
0
6
A
32 ×
V / VOUT
470
μF
COUT
Effective output capacitance(1)
CIN
Effective input capacitance(1)
5
RCF
ISINK_PG
Sink current at PG pin
TJ
Junction temperature
(1)
10
μF
4.5
100
kΩ
0
2
mA
–40
125
°C
The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC
bias effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check
the manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Please see the feature description for COMP/
FSET about the output capacitance vs compensation setting and output voltage.
7.4 Thermal Information
TPSM82816
THERMAL
METRIC(1)
4
UNIT
14 PINS
JEDEC 51-5
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
EVM
45.3
32.2
°C/W
29
n/a (2)
°C/W
(2)
°C/W
RθJB
Junction-to-board thermal resistance
27.4
ΨJT
Junction-to-top characterization parameter
5.7
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n/a
7.2
°C/W
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7.4 Thermal Information (continued)
TPSM82816
THERMAL
ΨJB
(1)
(2)
METRIC(1)
14 PINS
UNIT
JEDEC 51-5
EVM
16.2
12.7
Junction-to-board characterization parameter
°C/W
For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Not applicable to an EVM.
7.5 Electrical Characteristics
Over operating junction remperature range (TJ = –40°C to +125°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
18
36
μA
0.15
90
μA
2.6
2.7
V
2.5
2.6
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching,
MODE/SYNC = GND, VOUT = 0.6 V
ISD
Shutdown current
EN = GND
VUVLO
TJSD
Undervoltage lock out threshold
VIN rising
2.45
VIN falling
2.1
V
Thermal shutdown threshold
TJ rising
180
°C
Thermal shutdown hysteresis
TJ falling
15
°C
CONTROL and INTERFACE
VIH,EN
Input threshold voltage
EN rising
1.05
1.1
1.15
V
VIL,EN
Input threshold voltage
EN falling
0.96
1.0
1.05
V
IIH,EN
Input leakage current into EN
EN = VIN or GND
125
nA
VIH
Input-threshold voltage at MODE/SYNC
VIL
Input-threshold voltage at MODE/SYNC
0.3
V
IIH
Input leakage current into MODE/SYNC
250
nA
fSW
PWM Switching frequency range
MODE/SYNC = high
fSW
PWM Switching frequency
COMP/FSET = GND or VIN
fSW
PWM Switching frequency tolerance
using a resistor from COMP/FSET to
GND
fSYNC
Frequency range on MODE/SYNC pin for
synchronization
tSync_lock
Time to lock to external frequency
1.1
V
1.8
2.25
4
MHz
2.08
2.25
2.4
MHz
–12 %
12 %
1.8
4
50
Duty cycle of synchronization signal at
MODE/SYNC
20 %
µs
80 %
tDelay
Enable delay time
Time from EN high to device starts
switching; VIN applied already
tRamp
Output voltage ramp time, SS/TR pin
open
IOUT = 0 mA, time from device starts
switching to power good; device not in
current limit
ISS/TR
SS/TR source current
RDIS,SS/T
Internal discharge resistance on SS/TR
EN = low
Tracking gain
VFB / VSS/TR
Tracking offset
VFB when VSS/TR = 0 V
VTH_PG
UVP power good threshold voltage; dc
level
VOUT rising (%VFB)
92 %
95 %
98 %
VTH_PG
UVP power good threshold voltage; dc
level
VOUT falling (%VFB)
87 %
90 %
93 %
R
MHz
135
270
520
µs
90
150
220
µs
8
10
12
µA
0.7
1.1
1.5
kΩ
1
±1
mV
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7.5 Electrical Characteristics (continued)
Over operating junction remperature range (TJ = –40°C to +125°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
VOUT rising (%VFB)
107 %
110 %
113 %
OVP power good threshold voltage; dc
level
VOUT falling (%VFB)
104 %
107 %
111 %
VOL,PG
Low-level output voltage at PG
ISINK_PG = 2 mA
IIH,PG
Input leakage current into PG
VPG = 5 V
tPG,DLY
PG deglitch time
for a high level to low level transition on
the power good output
VTH_PG
OVP power good threshold voltage; dc
level
TEST CONDITIONS
0.01
UNIT
0.3
V
100
nA
40
µs
0.6
V
OUTPUT
6
VFB
Feedback voltage
VFB
Feedback voltage accuracy
PWM mode, VIN ≥ VOUT + 1 V
–1 %
1%
VFB
Feedback voltage accuracy
PFM mode, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5
V, Co,eff ≥ 47 µF
–1 %
2%
VFB
Feedback voltage accuracy
PFM mode, VIN ≥ VOUT + 1 V, VOUT < 1.5
V, Co,eff ≥ 68 µF
–1 %
2.5 %
VFB
Feedback voltage accuracy with voltage
tracking
VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V, PWM
mode
–5 %
5%
IIH,FB
Input leakage current into FB
VFB = 0.6 V
1
Load regulation
PWM mode
0.05
RDIS
Output discharge resistance
ton,min
Minimum on-time of high-side FET
RDP
Dropout Resistance
ILIMH
High-side FET switch current limit
DC value, VIN = 3 V to 6 V
ILIMNEG
Low-side FET negative current limit
DC value, MODE/SYNC = high
70
%/A
30
50
VIN ≥ 3.3 V
45
67
100% mode
27
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7.3
9.2
–3
nA
Ω
ns
mΩ
10.4
A
A
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7.6 Typical Characteristics
30
26
Shutdown current ISD (uA)
28
Quiescent current IQ (uA)
2
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
24
22
20
18
16
14
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
1.5
1
0.5
12
10
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
0
2.5
6
3
60
55
Dropout Resistance RDP (mΩ)
Switching Frequency (MHz)
2.3
2.29
2.28
2.27
2.26
2.25
2.24
2.23
VIN = 2.7 V
VIN = 3.3 V
VIN = 5.0 V
2.21
2.2
-40
-20
0
20
40
60
80
Junction Temperature (°C)
5
5.5
6
100
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125°C
50
45
40
35
30
25
20
15
10
2.5
120
Figure 7-3. Oscillator Frequency (COMP/FSET =
VIN)
3
3.5
4
4.5
Input Voltage (V)
5
5.5
Figure 7-4. Dropout Resistance
50
Output Discharge Resistance RDIS (Ω)
4
4.5
Input Voltage (V)
Figure 7-2. Shutdown Current
Figure 7-1. Quiescent Current
2.22
3.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
45
40
35
30
25
20
15
10
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
Figure 7-5. Discharge Resistance
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8 Detailed Description
8.1 Overview
The TPSM82816 synchronous switch mode DC/DC converter power modules are based on a fixed-frequency
peak current-mode control topology. The control loop is internally compensated. To optimize the bandwidth of
the control loop to the wide range of output capacitance that can be used with the TPSM82816, one of two
internal compensation settings can be selected. See COMP/FSET. The compensation setting is selected either
by a resistor from COMP/FSET to GND or by the logic state of this pin. The regulation network achieves fast and
stable operation with small external components and low-ESR ceramic output capacitors.
The device supports forced fixed frequency operation (FPWM) with the MODE/SYNC pin tied to a logic high
level. The frequency is defined as either 2.25 MHz (internally fixed when COMP/FSET is tied to GND or VIN)
or in a range of 1.8 MHz to 4 MHz (defined by a resistor from COMP/FSET to GND). Alternatively, the device
can be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE/SYNC
pin with no need for additional passive components. An internal PLL allows the device to change from internal
clock to external clock during operation. The synchronization to the external clock is done on the falling edge
of the clock applied at MODE/SYNC to the rising edge on the internal SW node. When the MODE/SYNC pin
is set to a logic low level, the device operates in power save mode (PSM). At low output current, the device
operates in PFM mode and automatically transitions to fixed-frequency PWM mode at higher output current. In
PFM operation, the switching frequency decreases linearly based on the load to sustain high efficiency down to
very low output current (see Power Save Mode Operation (PSM) for more details).
8.2 Functional Block Diagram
SW
VOUT
VIN
220 nH
Bias
Regulator
Gate Drive and Control
Ipeak
–
RDis
+
+
Izero
–
EN
MODE/SYNC
gm
PG
Oscillator
Device
Control
GND
VREF
+
-
SS/TR
COMP/FSET
Output
Discharge
FB
Thermal
shutdown
8.3 Feature Description
8.3.1 Precise Enable (EN)
The TPSM82816 starts operation when the rising EN threshold is exceeded. For proper operation, the EN pin
must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown. In
this mode, the internal high-side and low-side MOSFETs are turned off and the entire internal control circuitry is
switched off. The voltage applied at the EN pin of the TPSM82816 is compared to a fixed threshold of 1.1 V for a
rising voltage.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
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input of the EN pin. The Precise Enable input also allows you to drive the pin by a slowly changing voltage and
enables the use of an external RC network to achieve a precise power-up delay. See the Achieving a Clean
Start-up by Using a DC/DC Converter with a Precise Enable-pin Threshold Technical Brief for more details.
8.3.2 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device
is being disabled, but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active after the TPSM82816 has been enabled at least once since the supply voltage was applied.
The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage
lockout. The minimum supply voltage required for the discharge function to remain active is typically 2 V. Output
discharge is not activated during a current limit event.
8.3.3 COMP/FSET
This pin allows the user to set three different parameters independently:
• Internal compensation settings for the control loop (two settings available)
• The switching frequency in PWM mode from 1.8 MHz to 4 MHz
• Enable / disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. The resistor must
be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting
is sampled at the start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency, but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching
frequency or compensation. Do not leave the pin floating.
The switching frequency has to be selected based on the maximum input voltage in the application and the
output voltage to meet the specifications for the minimum on time.
Example: VIN = 5.5 V, VOUT = 1 V
V
fSw, max = V × OUT
= 5.5 V 1 V
× 67 ns = 2.71 MHz
IN tON, min
(1)
The compensation range has to be chosen based on the effective minimum capacitance used. The capacitance
can be increased from the minimum value as given in Table 8-1, up to the maximum of 470 µF in both
compensation ranges. If the capacitance of an output changes during operation, for example when load
switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the
minimum capacitance on the output. If the output capacitance exceeds 72 µF × V / VOUT[V], use the second
compensation setting to get the best load transient response. If the output capacitance only exceeds 32 µF ×
V / VOUT[V], use the first compensation setting. Compensating for large output capacitance but having too little
effective capacitance on the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
RCF kΩ = 18 MHz × kΩ
(2)
RCF kΩ = 60 MHz × kΩ
(3)
fS MHz
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
fS MHz
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
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RCF kΩ = 180 MHz × kΩ
fS MHz
(4)
Table 8-1. Switching Frequency and Compensation
COMPENSATION
RCF
SWITCHING FREQUENCY
MINIMUM OUTPUT
CAPACITANCE
For smallest output capacitance
(comp setting 1)
SSC disabled
10 kΩ ... 4.5 kΩ
1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)
according to Equation 2
32 µF × V / VOUT[V]
For smallest output capacitance
(comp setting 1)
SSC enabled
33 kΩ ... 15 kΩ
1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)
according to Equation 3
32 µF × V / VOUT[V]
For best transient response
(larger output capacitance)
(comp setting 2)
SSC disabled
100 kΩ ... 45 kΩ
1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)
according to Equation 4
72 µF × V / VOUT[V]
For smallest output capacitance
(comp setting 1)
SSC disabled
Tied to GND
Internally fixed 2.25 MHz
32 µF × V / VOUT[V]
For best transient response
(larger output capacitance)
(comp setting 2)
SSC enabled
Tied to VIN
Internally fixed 2.25 MHz
72 µF × V / VOUT[V]
The minimum output capacitance required for stability depends on the output voltage as stated in Table 8-1.
Refer to Output Capacitor for further details on the output capacitance required depending on the output voltage.
A too-high resistor value for RCF is decoded as "tied to VIN" and a value below the lowest range is decoded as
"tied to GND". The minimum output capacitance in Table 8-1 is for capacitors close to the output of the device. If
the capacitance is distributed, a lower compensation setting can be required.
8.3.4 MODE/SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current.
The MODE/SYNC pin forces PWM mode when set high. The pin also allows you to apply an external clock in
a frequency range from 1.8 MHz to 4 MHz for external synchronization. When an external clock is applied, the
device only operates in PWM mode. As with the switching frequency selection, the specification for the minimum
on-time has to be observed when applying the external clock signal. When using external synchronization, TI
recommends to set the switching frequency (as set by RCF) to a similar value as the externally applied clock.
This ensures that, if the external clock fails, the switching frequency stays in the same range and the settling
time to the internal clock is reduced. When there is no resistor from COMP/FSET to GND, but the pin is pulled
high or low, external synchronization is not possible. An internal PLL allows you to change from an internal
clock to external clock during operation. The synchronization to the external clock is done on the falling edge
of the applied clock to the rising edge of the internal SW pin (see Synchronizing to an External Clock). The
MODE/SYNC pin can be changed during operation.
8.3.5 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option, set by the COMP/FSET pin. When SSC is enabled,
the switching frequency is randomly changed in PWM mode when the internal clock is used. The frequency
variation is typically between the nominal switching frequency and up to 288 kHz above the nominal switching
frequency. When the device is externally synchronized, the TPSM82816 follows the external clock and the
internal spread spectrum block is turned off. SSC is also disabled during soft start.
8.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
MOSFETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input
voltage goes below the falling threshold.
10
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8.3.7 Power-Good Output (PG)
The device has a power-good output with window comparator. The PG pin goes high impedance after the FB
pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls
below 90% or rises higher than 110% of the nominal voltage (typical). Table 8-2 shows the typical PG pin logic.
The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup
resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails
by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.
Table 8-2. Power-Good Pin Logic
PG LOGIC STATUS
DEVICE STATE
HIGH IMPEDANCE
0.95 × VFB_NOM ≤ VFB ≤ 1.07 × VFB_NOM
Enabled (EN = High)
LOW
√
VFB < 0.9 × VFB_NOM or VFB > 1.1 ×
VFB_NOM
√
Shutdown (EN = Low)
√
UVLO
2 V ≤ VIN < VUVLO
√
Thermal Shutdown
TJ > TJSD
√
Power Supply Removal
VIN < 2 V
undefined
The PG pin has a 40-μs deglitch time on the falling edge. See Figure 8-1.
VTH,PG
VTH,PG
OVP
VO
VTH,PG
UVP
VTH,PG
PG
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
Figure 8-1. Power-Good Transient and Delay Behavior
8.3.8 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 180°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
PG goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During PFM the thermal shutdown is not active.
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8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPSM82816 has two operating modes: Forced PWM mode (FPWM) and Power Save Mode (PSM).
With the MODE/SYNC pin set to high, the TPSM82816 operates with pulse width modulation (PWM) in
continuous conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP/
FSET pin to GND or by an external clock signal applied to the MODE/SYNC pin.
With the MODE/SYNC pin set to low, the TPSM82816 operates with pulse frequency modulation (PFM) during
light load and will automatically transition into PWM as the load current increases.
8.4.2 Power Save Mode Operation (PSM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long
as the peak inductor current is above the PFM threshold of about 1.8 A. When the peak inductor current drops
below the PFM threshold, the device starts to skip switching pulses. The frequency set with the resistor on
COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz.
In power save mode, the switching frequency decreases linearly with the load current to maintain high efficiency.
The linear behavior of the switching frequency in power save mode is shown in Figure 8-2.
5
Switching Frequency (MHz)
1
0.1
0.01
0.001
0.0001
100u
FPWM
PSM
1m
10m
100m
Output Current (A)
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
1
6
Figure 8-2. Switching Frequency versus Output Current (VOUT = 1.8 V, RCF = 10 kΩ)
8.4.3 100% Duty-Cycle Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. When the
minimum off-time of typically 15 ns is reached, the TPSM82816 skips switching cycles while it approaches
100% mode. In 100% mode, the high-side MOSFET switch is constantly turned on. The minimum input voltage
to maintain a minimum output voltage is given by:
VIN(min) = VOUT(min) + IOUT × RDP
(5)
where:
•
•
RDP is the resistance from VIN to VOUT, which includes the high-side MOSFET on-resistance and DC
resistance of the inductor
VOUT(min) is the minimum output voltage the load can accept
This operation mode is particularly useful in battery-powered applications to achieve longest operation time by
taking full advantage of the whole battery voltage range.
8.4.4 Current Limit and Short-Circuit Protection
The TPSM82816 is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down
12
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the inductor current. The high-side MOSFET turns on again only if the current in the low-side MOSFET has
decreased below the low-side current limit. Due to internal propagation delays, the actual current can exceed the
static current limit. The dynamic current limit is given as:
where
•
•
•
•
V
Ipeak typ = ILIMH + LL × tPD
(6)
ILIMH is the static current limit, as specified in the electrical characteristics
L is the effective inductance (typically 220 nH)
VL is the voltage across the inductor (VIN - VOUT)
tPD is the internal propagation delay of typically 50 ns
The dynamic peak current is calculated as follows:
V − VOUT
Ipeak typ = ILIMH + IN220 nH
× 50 ns
(7)
The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back
through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned
off. In this scenario, both MOSFETs are off until the start of the next cycle. The negative current limit is only
active in Forced PWM mode.
8.4.5 Soft Start / Tracking (SS/TR)
The soft-start circuitry controls the output voltage slope during start-up. This action avoids excessive inrush
current and ensures a controlled output voltage rise time. This action also prevents unwanted voltage drops from
high impedance power sources or batteries. When EN is set high, the device starts switching after a delay of
about 270 μs. Then VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin.
A capacitor connected from SS/TR to GND is charged with 10 µA by an internal current source during soft start
until it reaches the reference voltage of 0.6 V. After reaching 0.6 V, the SS/TR pin voltage is clamped internally
while the SS/TR pin voltage keeps rising to a maximum of about 3.3 V. The capacitance required to set a certain
ramp-time (tramp) is:
CSS nF =
10μA × tramp ms
0.6 V
(8)
Leaving the SS/TR pin un-connected provides the fastest start-up ramp of 150 µs typically. If the device is set to
shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor of about 1.1 kΩ pulls the
SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new start-up sequence.
A voltage applied at the SS/TR pin can also be used to track a master voltage. The output voltage follows this
voltage in both directions up and down in forced PWM mode. In PSM mode, the output voltage decreases based
on the load current. An external voltage applied on SS/TR is internally clamped to the feedback voltage (0.6 V).
TI recommends to set the final value of the external voltage on SS/TR to be slightly above 0.6 V to make sure
the device operates with its internal reference voltage when the power-up sequencing is finished. See Voltage
Tracking.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPSM82816 is a synchronous step-down converter power module. The power inductor is integrated inside
the TPSM82816. The inductor is shielded and has an inductance of 220 nH. The TPSM82810, TPSM82813 and
TPSM82816 are pin-to-pin compatible.
9.2 Typical Application
TPSM82816
VOUT
2.7 V - 6 V
VOUT
VIN
VOUT
CIN
22 µF
R1
CFF
EN
FB
MODE/SYNC
R2
External sync (optional)
R3
COUT
2 × 47 µF
COMP/FSET
SS/TR
RCF
CSS
PG
GND
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
Table 9-1. List of Components
(1)
14
REFERENCE
DESCRIPTION
MANUFACTURER (1)
IC
TPSM82816
Texas Instruments
CIN
22 µF / X7R / 6.3 V; GRM21BZ70J226ME44L
Murata
COUT for VOUT < 1 V
3 × 47 µF / X6S / 6.3 V; JMK212BC6476MG-T
Taiyo Yuden
COUT for VOUT ≥ 1 V
2 × 47 µF / X6S / 6.3 V; JMK212BC6476MG-T
Taiyo Yuden
CSS
4.7 nF
Any
RCF
10 kΩ
Any
CFF
10 pF
Any
R1
Depending on VOUT
Any
R2
Depending on VOUT
Any
R3
100 kΩ
Any
See the Third-party Products Disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting the Output Voltage
The output voltage of the TPSM82816 is adjustable. Choose resistors R1 and R2 to set the output voltage within
a range of 0.6 V to 5.5 V according to Equation 9. To keep the feedback (FB) net robust from noise, set R2
equal to or lower than 100 kΩ to have at least 6 µA of current in the voltage divider. Lower values of FB resistors
achieve better noise immunity, and lower light load efficiency, as explained in the Design Considerations for a
Resistive Feedback Divider in a DC/DC Converter Technical Brief.
V
V
OUT
R1 = R2 × VOUT − 1 = R2 × 0.6 V
−1
FB
(9)
Table 9-2. Examples for setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
VOUT
R1
R2
Max CFF
at min Cout
OUTPUT VOLTAGE
0.8 V
16.9 kΩ
51 kΩ
15 pF
0.7988 V
1.0 V
20 kΩ
30 kΩ
13 pF
1.0 V
1.1 V
39.2 kΩ
47 kΩ
6.8 pF
1.101 V
1.2 V
68 kΩ
68 kΩ
3.9 pF
1.2 V
1.5 V
76.8 kΩ
51 kΩ
3.3 pF
1.5 V
1.8 V
80.6 kΩ
40.2 kΩ
3.3 pF
1.803 V
2.5 V
47.5 kΩ
15 kΩ
5.6 pF
2.5 V
3.3 V
88.7 kΩ
19.6 kΩ
3 pF
3.315 V
9.2.2.2 Feedforward Capacitor
A feedforward capacitor (CFF) is required in parallel with R1 to improve the transient response. The maximum
value for the feedforward capacitor CFF at the minimum output capacitance is determined by Equation 10:
× Ω
Cff, max nF = 266.1 nF
R
(10)
1
For examples of feedforward capacitor values for common output voltages when using the minimum required
output capacitance, refer to Table 9-2.
To improve the load transient performance, more output capacitance can be added. Increasing the CFF above
values given by Equation 10 can also improve the response with larger COUT. The converter's loop response
must be evaluated either through a simple load step or by a phase margin measurement. For details, please
refer to: AN-1733 Load Transient Testing Simplified Application Report.
9.2.2.3 Input Capacitor
For most applications, TI recommends a 22-µF nominal ceramic capacitor. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A X7R or X7T multilayer ceramic
capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as
possible to those pins. For applications with ambient temperatures below 85°C, a capacitor with X5R dielectric
can be used. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective
capacitance. Choose the right capacitor carefully in combination with considering its package size and voltage
rating. The minimum required input capacitance is 5 µF.
9.2.2.4 Output Capacitor
The architecture of the TPSM82816 allows the use of ceramic output capacitors which have low equivalent
series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep
its low resistance up to high frequencies and to get a narrow capacitance variation with temperature, TI
recommends to use an X7R or X7T dielectric. At temperatures below 85°C, an X5R dielectric can be used.
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Using a higher capacitance value has advantages like smaller voltage ripple and a tighter DC output accuracy
in power save mode. By changing the device compensation with a resistor from COMP/FSET to GND, the
device can be compensated in two steps based on the minimum capacitance used on the output. The maximum
capacitance is 470 µF in any of the compensation settings. The minimum capacitance required on the output
depends on the compensation setting and output voltage as shown in Table 8-1. For output voltages below
1 V, the minimum required capacitance increases linearly from 32 µF at 1 V to 53 µF at 0.6 V with the
compensation setting for smallest output capacitance. The other compensation setting scales the same. Ceramic
capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the
right capacitor carefully in combination with considering its package size and voltage rating.
16
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9.2.2.5 Application Curves
100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 5 V, VOUT = 1.8 V, 1.8 MHz, PWM mode, BOM = Table 9-1 unless otherwise noted.
75
70
65
60
55
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
50
45
40
100u
1m
10m
100m
Output Current (A)
1
75
70
65
60
55
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
50
45
40
6
0
0.5
1
1.5
2
PSM and FPWM
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
100
95
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
45
40
100u
1m
10m
100m
Output Current (A)
1
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
50
45
40
6
0
0.5
1
1.5
2
D002
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
100
75
70
65
60
10m
100m
Output Current (A)
5
5.5
6
1
75
70
65
60
55
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1m
4.5
Figure 9-5. Efficiency VIN = 3.3 V and TA = 85°C
95
40
100u
2.5 3 3.5 4
Output Current (A)
FPWM
100
45
6
70
55
Figure 9-4. Efficiency VIN = 3.3 V and TA = 25°C
50
5.5
75
PSM and FPWM
55
5
Figure 9-3. Efficiency VIN = 5.0 V and TA = 85°C
100
50
4.5
FPWM
Figure 9-2. Efficiency VIN = 5.0 V and TA = 25°C
55
2.5 3 3.5 4
Output Current (A)
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
50
45
6
40
0
0.5
D002
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
FPWM
PSM and FPWM
Figure 9-6. Efficiency VIN = 2.7 V and TA = 25°C
Figure 9-7. Efficiency VIN = 2.7 V and TA = 85°C
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2
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
2
1
0
-1
100u
1m
10m
100m
Output Current (A)
1
1
0
-1
100u
6
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
1m
TA = 25°C
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
0
1m
10m
100m
Output Current (A)
1
1
0
-1
100u
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1m
TA = 25°C
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
0
1m
10m
100m
Output Current (A)
6
1
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1
0
-1
100u
TA = 25°C
1m
10m
100m
Output Current (A)
1
6
TA = 25°C
Figure 9-12. Load Regulation VIN = 2.7 V (PSM)
18
1
Figure 9-11. Load Regulation VIN = 3.3 V (FPWM)
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1
-1
100u
10m
100m
Output Current (A)
TA = 25°C
Figure 9-10. Load Regulation VIN = 3.3 V (PSM)
2
6
Figure 9-9. Load Regulation VIN = 5.0 V (FPWM)
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1
-1
100u
1
TA = 25°C
Figure 9-8. Load Regulation VIN = 5.0 V (PSM)
2
10m
100m
Output Current (A)
Figure 9-13. Load Regulation VIN = 2.7 V (FPWM)
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7
6
5.5
5
4.5
4
3.5
6
5.5
5
4.5
4
3.5
3
3
2.5
2.5
2
70
75
80
RθJA = 32.2 °C/W
85
90
95
100 105
Ambient Temperature (°C)
fSW = 1.8 MHz
110
115
TJ,max = 125 °C
Figure 9-14. Safe Operating Area VIN = 5.0 V
VOUT = 1.8 V
VIN = 5.0 V
PSM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
6.5
Output Current (A)
Output Current (A)
7
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
6.5
2
70
75
80
RθJA = 32.2 °C/W
85
90
95
100 105
Ambient Temperature (°C)
fSW = 1.8 MHz
110
TJ,max = 125 °C
Figure 9-15. Safe Operating Area VIN = 3.3 V
VOUT = 1.8 V
VIN = 5.0 V
FPWM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
Figure 9-16. Load Transient Response
Figure 9-17. Load Transient Response
VOUT = 1.8 V
IOUT = 0 A
VOUT = 1.8 V
IOUT = 4 A
PSM
VIN = 5.0 V
TA = 25 °C
BW = 20 MHz
Figure 9-18. Output and Input Voltage Ripple
115
PWM
VIN = 5.0 V
TA = 25°C
BW = 20 MHz
Figure 9-19. Output and Input Voltage Ripple
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VOUT = 1.8 V
IOUT = 0 A
PSM
VIN = 5 V
TA = 25°C
CSS = 4.7 nF
Figure 9-20. Start-Up Timing
20
VOUT = 1.8 V
IOUT = 4 A
FPWM
VIN = 5 V
TA = 25°C
CSS = 4.7 nF
Figure 9-21. Start-Up Timing
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9.3 System Examples
9.3.1 Voltage Tracking
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 9-22. From 0 V to 0.6 V, the internal reference voltage to the internal error amplifier
follows the SS/TR pin voltage. When the SS/TR pin voltage is above 0.6 V, the voltage tracking is disabled and
the FB pin voltage is regulated at 0.6 V. The device achieves ratiometric, as shown in Figure 9-23 or coincidental
(simultaneous) output tracking, as shown in Figure 9-23.
The R2 value must be set properly to achieve accurate voltage tracking by taking the 10-μA charging current into
account. 1 kΩ or smaller is a sufficient value for R2. For decreasing SS/TR pin voltage, the device does not sink
current from the output when the device is in PSM. The resulting decrease of the output voltage can be slower
than the SS/TR pin voltage if the load is light.
In case both devices need to run in forced PWM mode after start-up, TI recommends to tie the MODE/SYNC pin
of the secondary device to the output voltage or the power good signal of the primary device. The TPSM82816
has a duty cycle limitation defined by the minimum on time. For tracking down to low output voltages, the
secondary device cannot follow after the minimum duty cycle is reached. Enabling FPWM mode while tracking is
in progress allows the user to ramp down the output voltage close to 0 V.
When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin.
Vout1
Vout2
TPSM8281x
R1
SS/TR
R3
FB
R2
R4
Figure 9-22. Schematic for Output Voltage Tracking
VOUT2
VOUT1
Output Voltage [V]
Output Voltage [V]
VOUT1
R1
R3
<
R2
R4
VOUT2
R1
R3
=
R2
R4
Time [s]
Time [s]
Figure 9-23. Ratiometric Voltage Tracking
Figure 9-24. Coincidental Voltage Tracking
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9.3.2 Synchronizing to an External Clock
The TPSM82816 can be synchronized by applying a clock on the MODE/SYNC pin. There is no need for any
additional circuitry as long as the input signal meets the requirements given in the electrical specifications. See
Figure 9-25. The clock can be applied, changed, and removed during operation. The value of the RCF resistor is
recommended to be chosen such that the internally defined frequency and the externally-applied frequency are
close to each other to have a fast settling time to the external clock. Synchronizing to a clock is not possible if
the COMP/FSET pin is connected to Vin or GND. Figure 9-26 and Figure 9-27 show the external clock being
applied and removed. When an external clock is applied, the device operates in PWM mode.
TPSM82816
VOUT
2.7 V - 6 V
VOUT
VIN
VOUT
CIN
22 µF
R1
CFF
EN
FB
MODE/SYNC
R2
External sync (optional)
R3
COUT
2 × 47 µF
COMP/FSET
SS/TR
RCF
CSS
PG
GND
Figure 9-25. Frequency Synchronization
VIN = 5 V
VOUT = 1.8 V
RCF = 10 kΩ
fEXT = 2.0 MHz
IOUT = 0.01 A
Figure 9-26. Applying and Removing the
Synchronization Signal (PSM)
VIN = 5 V
VOUT = 1.8 V
RCF = 10 kΩ
fEXT = 2.0 MHz
IOUT = 1 A
Figure 9-27. Applying and Removing the
Synchronization Signal (FPWM)
9.4 Power Supply Recommendations
The TPSM82816 device family has no special requirements for the input power supply. The output current of
the input power supply must be rated according to the supply voltage, output voltage, and output current of the
TPSM82816.
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9.5 Layout
9.5.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. Therefore, the PCB layout of the TPSM82816 demands careful attention to ensure best
performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI
radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter
Technical Brief for a detailed discussion of general best practices. Specific recommendations for the device are
listed below.
•
•
•
•
•
•
The input capacitor must be placed as close as possible to the VIN and GND pins of the device. This
placement is the most critical component placement. Route the input capacitor directly to the VIN and GND
pins avoiding vias.
Place the output capacitor ground close to the VOUT and GND pins and route it directly avoiding vias.
Place the FB resistors, R1 and R2, and the feedforward capacitor CFF close to the FB pin and place CSS
close to the SS/TR pin to minimize noise pickup.
Place the RCF resistor close to the COMP/FSET pin to minimize the parasitic capacitance.
The recommended layout is implemented on the EVM and shown in its TPSM8281xEVM-089 Evaluation
Module User's Guide and in Layout Example.
The recommended land pattern for the TPSM82816 is shown at the end of this data sheet. For best
manufacturing results, create the pads as solder mask defined (SMD), when some pins (such as VIN, VOUT,
and GND) are connected to large copper planes. Using SMD pads keeps each pad the same size and avoids
solder pulling the device during reflow.
9.5.2 Layout Example
GND
R2
GND
Cff
Css
R1
VIN
VIN
GND
VOUT
FB
GND
MODE
/SYNC
COMP
/FSET
SS/TR
GND
PG
VIN
VIN
U1
EN
Cin
GND
Rcf
Cout
VOUT
Figure 9-28. Example Layout
9.5.2.1 Thermal Consideration
The TPSM82816 module temperature must be kept less than the maximum rating of 125°C. The following are
three basic approaches for enhancing thermal performance:
•
•
•
Improve the power dissipation capability of the PCB design.
Improve the thermal coupling of the component to the PCB.
Introduce airflow into the system.
To estimate the approximate module temperature of the TPSM82816, apply the typical efficiency stated in this
data sheet to the desired application condition to compute the power dissipation of the module. Then, calculate
the module temperature rise by multiplying the power dissipation by its thermal resistance. For more details on
how to use the thermal parameters in real applications, see the application notes: Thermal Characteristics of
Linear and Logic Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics.
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The thermal values in Thermal Information used the recommended land pattern, shown at the end of this data
sheet, including the 30 vias as they are shown. The TPSM82816 was simulated on a PCB defined by JEDEC
51-7. The 15 vias on the GND pins were connected to copper on other PCB layers, while the remaining 15 vias
were not connected to other layers.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
Texas Instruments, TPSM8281xEVM-089 Evaluation Module User's Guide
Texas Instruments, Achieving a Clean Start-up by Using a DC/DC Converter with a Precise Enable-pin
Threshold Technical Brief
Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter Technical
Brief
Texas Instruments, AN-1733 Load Transient Testing Simplified Application Report
Texas Instruments, Five Steps to a Great PCB Layout for a Step-Down Converter Technical Brief
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
MicroSiP™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
SIE0014A-C01
uSIP TM - 1.6 mm max height
SCALE 3.000
MICRO SYSTEM IN PACKAGE
3.1
2.9
B
A
PIN 1 INDEX
AREA
(3.2)
4.1
3.9
PICK AREA
NOTE 3
(2.5)
1.6 MAX
C
0.08 C
4X
2X 1.75
1.19
1.11
4X 0.3 0.03
10X (0.05)
6
5
2X 3.1
2X 1.3
12
4X (0.075)
6X
13
0.54
0.46
SYMM
2X 1.15
14
11
4X 0.65
4X 0.8 0.03
6X
10
1
PIN 1 ID
(OPTIONAL)
SYMM
4X
2X 0.9
2.4
0.79
0.71
0.1
0.05
0.28
0.22
0.1
0.05
C A B
C
C A B
C
4228828/B 10/2022
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
SIE0014A-C01
uSIP TM - 1.6 mm max height
MICRO SYSTEM IN PACKAGE
4X (1.45)
4X (0.55)
0.000 PKG
4X (0.55)
3X (0.45)
4X (1.45)
2X (2)
METAL UNDER
SOLDER MASK
TYP
(0.05) TYP
6X (1.925)
6X (1.425)
10
1
6X (0.75)
6X (0.25)
SOLDER MASK
OPENING
TYP
4X (0.45)
2X (0.625)
11
14
12
13
4X (0.575)
2X (3.35)
0.000 PKG
4X (0.65)
2X (0.625)
4X (0.8)
(R0.05) TYP
5
( 0.2) TYP
VIA
6
SEE DETAILS
3X (0.45)
6X (1.425)
4X (1)
6X (1.925)
4X (1.4)
(0.3)
4X (0.3)
(2.65)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK DEFINED
PADS 1, 5, 6, 10 AND 11 - 14
NOT TO SCALE
4228828/B 10/2022
NOTES: (continued)
5. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
SIE0014A-C01
uSIP TM - 1.6 mm max height
MICRO SYSTEM IN PACKAGE
2X (2)
4X (0.45)
(R0.1) TYP
SYMM
1
10
6X (0.75)
6X (0.25)
11
4X (0.575)
14
SYMM
2X (3.35)
13
12
6X (0.65)
4X (0.8)
4X (1)
6
5
4X (1.4)
4X (0.3)
(2.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:25X
4228828/B 10/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
TPSM82816SIER
ACTIVE
uSiP
SIE
14
3000
RoHS & Green
ENEPIG
Level-2-260C-1 YEAR
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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