TPSM82912, TPSM82913, TPSM82913E
SLVSGJ4C – OCTOBER 2022 – REVISED JULY 2023
TPSM8291x 3-V to 17-V, 2-A/3-A Low-Noise and Low-Ripple Buck Power Module with
Integrated Ferrite Bead Filter Compensation
1 Features
3 Description
•
The TPSM8291x devices are a family of highefficiency, low-noise and low-ripple current mode
synchronous buck power modules. The devices are
ideal for noise sensitive applications that would
normally use an LDO for post regulation such as
high-speed ADCs, clock and jitter cleaner, serializer,
de-serializer, and radar applications.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low output noise < 20 µVRMS
(100 Hz to 100 kHz)
Low output voltage ripple < 10 µVRMS after ferrite
bead
High PSRR of > 65 dB (up to 100 kHz)
2.2-MHz or 1-MHz fixed frequency peak current
mode control
Synchronizable with external clock (optional)
Integrated loop compensation supports ferrite
bead for second stage L-C filter with 30-dB
attenuation (optional)
Spread spectrum modulation (optional)
3.0-V to 17-V input voltage range
0.8-V to 5.5-V output voltage range
57-mΩ/20-mΩ RDSon
Output voltage accuracy of ±1%
Precise enable input allows
– User-defined undervoltage lockout
– Exact sequencing
Adjustable soft start
Power-good output
Output discharge (optional)
–40°C to 125°C junction temperature range
– –55°C to 125°C for -ET versions
Create a custom design using the TPSM8291x
with the WEBENCH® Power Designer
2 Applications
To further reduce the output voltage ripple, the device
integrates loop compensation to operate with an
optional second-stage ferrite bead L-C filter. This
feature allows an output voltage ripple below 10
µVRMS.
Low-frequency noise levels, similar to a low-noise
LDO, are achieved by filtering the internal voltage
reference with an integrated capacitor on the NR/SS
pin. An external capacitor can be added to the module
for additional filtering.
The optional spread spectrum modulation scheme
spreads the DC/DC switching frequency over a wider
span, which lowers the mixing spurs.
Device Information
TPSM82912
2A
TPSM82913,
TPSM82913E
3A
(1)
10
5
4.50 mm × 5.50
mm × 1.80 mm
10 nH
VIN
CIN
10 µF
0.2
0.1
0.05
0.002
0.001
0.0005
1x101
RDU (QFN,
28)
BODY SIZE
(NOM)
For all available packages, see the orderable addendum at
the end of the data sheet.
Vin
12 V
2
1
0.5
0.02
0.01
0.005
OUTPUT
(1)
PACKAGE
CURRENT
DEVICE NAME
Telecom infrastructure
Test and measurement
Aerospace and defense (radar, avionics)
Medical
Noise Density (V/Hz)
•
•
•
•
The devices operate at a fixed switching frequency of
2.2 MHz or 1 MHz and can be synchronized to an
external clock.
Vout
3.3 V / 3 A
OUT
3x
22 µF
EN/SYNC
S-CONF
FB
NR/SS
PG
PGND
CNRSS = open, 19.6 VRMS
CNRSS = 220 nF, 17 VRMS
CNRSS = 470 nF, 16.6 VRMS
CNRSS = 2.2 F, 16.3 VRMS
1x102
1x103
1x104
Frequency (Hz)
22 µF
15.4 k
4.87 k
Typical Application
1x105
1x1063x106
Output Noise Versus Frequency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM82912, TPSM82913, TPSM82913E
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SLVSGJ4C – OCTOBER 2022 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 20
8.3 Power Supply Recommendations.............................27
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................30
9.1 Device Support......................................................... 30
9.2 Documentation Support............................................ 30
9.3 Receiving Notification of Documentation Updates....30
9.4 Support Resources................................................... 30
9.5 Trademarks............................................................... 30
9.6 Electrostatic Discharge Caution................................31
9.7 Glossary....................................................................31
10 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2023) to Revision C (July 2023)
Page
• Removed TPSM82912 preview status in the Device Information table..............................................................1
Changes from Revision A (December 2022) to Revision B (May 2023)
Page
• Removed TPSM82912-ET from the Device Information table........................................................................... 1
• Updated TPSM82913-ET to TPSM82913E and removed preview status in the Device Information table........ 1
• Added -ET temp range in the Electrical Characteristics table............................................................................ 4
Changes from Revision * (October 2022) to Revision A (December 2022)
Page
• Changed data sheet status from Advance Information to Production Mix..........................................................1
2
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5 Pin Configuration and Functions
Figure 5-1. 28-Pin QFN RDU Package (Top View)
Table 5-1. Pin Functions
PIN
NO.
18
NAME
VIN
I/O
I
1, 2, 3, 5,
6, 7, 8, 9,
16, 17, PGND
25, 26,
28
DESCRIPTION
Power supply input voltage pin
Power ground connection
10, 11,
12, 13,
14, 15,
VOUT
O
Output connection. Connect recommended output capacitance from VOUT to PGND.
27
4
SW
NC
Switch pin of the power stage. Do not connect, leave floating.
19
PG
O
Open-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. It requires a pull-up
resistor to output a logic high. It can be left open or tied to GND if not used.
20
PSNS
I
Power sense ground. Connect directly to the ground plane.
21
NR/SS
O
A capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.
22
FB
I
Feedback pin of the device
23
S-CONF
O
Smart Configuration pin. This pin configures the operation modes of the device. See Table 7-1.
24
EN/SYNC
I
Enable/Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device.
This pin has an internal pull-down resistor of typically 500 kΩ when the device is disabled. Apply a clock to this pin to
synchronize the device.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
Voltage(2)
MAX
UNIT
VIN, EN/SYNC, PG, S-CONF
–0.3
18
V
SW (DC)
–0.3
VIN + 0.3
V
SW (AC, less than
10ns)(3)
–2.5
21
V
VOUT, FB, NR/SS
–0.3
6
V
PSNS
–0.3
0.3
V
10
mA
Sink Current
PG
TJ
Junction temperature, -ET versions only
–55
125
°C
Tstg
Storage temperature
–65
125
°C
Mechanical
shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
1500
G
Mechanical
vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
20
G
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to the network ground terminal
While switching
(2)
(3)
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input voltage
3.0
VOUT
Output voltage
0.8
CIN
Effective input capacitance
COUT
Effective output capacitance
Lf
Effective filter inductance
Cf
COUT + Cf
IOUT
IOUT
TJ
(1)
TJ (1)
(1)
4
NOM
MAX
17
5.5
UNIT
V
V
5
10
µF
40
47
80
µF
0
10
50
nH
Effective filter capacitance
20
40
160
µF
Effective total output capacitance, including first and second L-C filter
40
200
µF
Output current for TPSM82913
0
3
A
Output current for TPSM82912
0
2
A
Junction temperature
–40
125
°C
Junction temperature, -ET versions only
–55
125
°C
Operating lifetime is derated at junction temperatures above 125°C.
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6.4 Thermal Information
TPSM8291x
THERMAL
METRIC(1)
RDU 30-pin QFN
JEDEC 51-7 PCB
UNIT
TPSM8291xEVM-213
RθJA
Junction-to-ambient thermal resistance
31.3
30.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.4
n/a (2)
°C/W
(2)
°C/W
RθJB
Junction-to-board thermal resistance
7.2
n/a
ΨJT
Junction-to-top characterization parameter
-4.9 (3)
-3.0 (3)
°C/W
YJB
Junction-to-board characterization parameter
7.1
9.0
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM
This is a negative value because the case temperature is higher than the die junction temperature due to the integrated inductor
having the highest power dissipation in the module.
6.5 Electrical Characteristics
Over recommended input voltage range, TJ = -40 ℃ to 125 ℃, (TJ = -55 ℃ to 125 ℃ for -ET parts). Typical values are at Vin
= 12 V andTJ = 25 ℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current
EN = High, no load, device switching, fsw
= 1 MHz
ISD
Shutdown current
EN = GND
VUVLO
Under voltage lockout
VIN rising
VUVLO
Under voltage lockout
VIN rising
VHYS
Under voltage lockout hysteresis
TJSD
5
2.85
mA
0.3
70
µA
2.92
3.0
V
3.04
V
200
mV
Thermal shutdown threshold
TJ rising
170
°C
Thermal shutdown hysteresis
TJ falling
20
°C
CONTROL and INTERFACE
VH_EN
High-level input-threshold voltage at EN/
SYNC
0.97
1.01
1.04
V
VL_EN
Low-level input-threshold voltage at EN/
SYNC
0.87
0.9
0.93
V
VH_SYNC
High-level input-threshold clock signal on
EN/SYNC
EN/SYNC = clock
VL_SYNC
Low-level input-threshold clock signal on
EN/SYNC
EN/SYNC = clock
IEN,LKG
Input leakage current into EN/SYNC
EN/SYNC = GND or VIN
RPD
Pull-down resistor on EN/SYNC
EN/SYNC = Low
tdelay
Enable delay time
Time from EN/SYNC high to device starts
switching, RS-CONF = 80.6 kΩ
INR/SS
NR/SS source current
1.1
0.4
5
330
67.5
RS-CONF tolerance for all settings
according to Table 7-1
V
160
V
nA
500
kΩ
1
ms
75
µA
+4
%
30
pF
RS-CONF
S-CONF resistor step range accuracy
CS-CONF
Maximum capacitance connected to SCONF pin
VPG
Power good threshold
VFB rising, referenced to VFB nominal
93
95
98
%
VPG
Power good threshold
VFB falling, referenced to VFB nominal
88
90
93
%
VPG,OL
Low-level output voltage at PG pin
ISINK = 1 mA
0.4
V
IPG,LKG
Input leakage current into PG pin
VPG = 5 V
5
500
nA
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82.5
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6.5 Electrical Characteristics (continued)
Over recommended input voltage range, TJ = -40 ℃ to 125 ℃, (TJ = -55 ℃ to 125 ℃ for -ET parts). Typical values are at Vin
= 12 V andTJ = 25 ℃ (unless otherwise noted)
PARAMETER
tPG,DLY
TEST CONDITIONS
MIN
TYP
MAX
8
UNIT
Power good delay time
VFB falling
µs
ton
Minimum on-time
VIN ≥ 5 V, Iout = 1 A
toff
Minimum off-time
VIN ≥ 5 V, Iout = 1 A
VFB
Feedback regulation accuracy
–40℃ ≤ TJ ≤ 125℃
IFB,LKG
Input leakage current into FB
VFB = 0.8 V
PSRR
Power supply rejection ratio
VIN = 12 V, 1.2 VOUT, 1 A, CNR/SS = 220
nF, fsw = 1 MHz, CFF = open, COUT = 3 x
22 µF, f ≤ 100 kHz
VNRMS
Output voltage RMS noise
VIN = 12 V, BW = 100 Hz to 100 kHz, CNR/
SS = 220 nF, fSW = 1 MHz, VOUT = 1.2 V,
CFF = open, COUT = 3 x 22 µF
27.4
µVRMS
VNRMS
Output voltage RMS noise
SS =
VIN = 5 V, BW = 100 Hz to 100 kHz, CNR/
220 nF, fSW = 2.2 MHz, VOUT = 1.2 V,
CFF = open, COUT = 3 x 22 µF
13.3
µVRMS
Vopp
Output ripple voltage at fSW
VIN = 12 V, fSW = 1 MHz, VOUT = 1.2 V,
COUT = 3 x 22 µF, Lf = 10 nH, Cf = 2 x 22
µF
9
µVRMS
Vopp
Output ripple voltage at fSW
VIN = 5 V, fSW = 2.2 MHz, VOUT = 1.2V,
COUT = 3 x 22 µF, Lf = 10 nH, Cf = 2 x 22
uF
TJSD
√
Power Supply Removal
VIN < 0.7 V
√
7.3.8 Noise Reduction and Soft-Start Capacitor (NR/SS)
A capacitor connected to this pin reduces the low frequency noise of the converter and sets the soft-start time.
The larger the capacitor, the lower the noise and the longer the start-up time of the converter. The module has
an internal 220-nF capacitor connected to the NR/SS pin. If no external capacitor is connected to the NR/SS
pin, the default start-up time is 2.35 ms, although longer start-up times and additional noise reduction can be
achieved with additional capacitance connected to the NR/SS pin. The maximum NR/SS cap is 3.3 µF for a
start-up time of 35 ms.During soft start with a light load, the device skips switching pulses as needed to not
discharge the output voltage. The device can start into a pre-biased output voltage.
The device achieves low noise by adding an R-C filter to the reference voltage, as shown in Functional Block
Diagram. During start-up, the NR/SS capacitor is charged with a constant current of 75 µA (typical) to 0.8 V.
Larger NR/SS capacitors provide for lower low frequency noise, as shown in Figure 6-29.
7.3.9 Current Limit and Short-Circuit Protection
The device is protected against short circuits and overcurrent. The switch current limit prevents the device from
high inductor current and from drawing excessive current from the input voltage rail. Excessive current can occur
with a shorted, saturated inductor or a heavy load, shorted output circuit condition. If the inductor current reaches
the threshold ISWpeak, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down
the inductor current. The high-side MOSFET is turned on again only when the low-side current is below the
low-side sourcing current limit ISWvalley.
Due to internal propagation delay, the actual current can exceed the static current limit, especially if the input
voltage is high and very small inductances are used. The dynamic current limit is calculated as follows:
Ipeak (typ )
§ VL ·
ISWpeak ¨ ¸ u tPD
©L¹
(1)
where
•
•
•
•
ISWpeak is the static current limit, specified in Electrical Characteristics
L is the inductance (2.2 μH for the TPSM8291x)
VL is the voltage across the inductor (VIN – VOUT)
tPD is the internal propagation delay, typically 50 ns
The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back
through the inductor to the input. This can happen during light load conditions or a pre-biased output condition.
18
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If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off. In this scenario, both
MOSFETs are off until the start of the next cycle.
7.3.10 Thermal Shutdown
The device goes into thermal shutdown after the junction temperature exceeds typically 170°C with a 20°C
hysteresis.
7.4 Device Functional Modes
7.4.1 Fixed Frequency Pulse Width Modulation
To minimize output voltage ripple, the device operates in fixed frequency PWM operation down to no load. The
switching frequency of 1 MHz or 2.2 MHz is selected using the S-CONF pin.
7.4.2 Low Duty Cycle Operation
For high input voltages or low output voltages, the 70-ns minimum on-time limits the maximum input to output
voltage difference and the switching frequency selected. When the minimum on-time is reached, the output
voltage rises above the regulation point. Refer to Table 8-2 for detailed design recommendations.
7.4.3 High Duty Cycle Operation (100% Duty Cycle)
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode,
the high-side MOSFET switch is constantly turned on. The minimum input voltage to maintain output voltage
regulation, depending on the load current and the output voltage level, is calculated as:
VIN (min) VOUT (min) IOUT u (RDS (ON ) RL)
(2)
where
• VOUT(min) is the minimum output voltage the load can accept
• IOUT is the output current
• RDS(ON) is the RDS(ON) of the high-side MOSFET
• RL is the DC resistance of the inductor used,
76 mΩ for the TPSM8291x
To maintain fixed frequency switching, the device requires a minimum off-time of 50 ns (typical), 60 ns
(maximum). If this limit is reached during a switching pulse, the device skips switching pulses to maintain output
voltage regulation. If the input voltage decreases further, the device enters 100% mode.
7.4.4 Second Stage L-C Filter Compensation (Optional)
Most low-noise and low-ripple applications use a ferrite bead and bypass capacitor before the load. Using a
second L-C filter is especially useful for low-noise and low-ripple applications with constant load current such as
ADCs, DACs, and Jitter Cleaner. The second stage L-C filter is optional, and the device can be used without
this filter. Without the filter, the device has a low output voltage noise of typically 16.6 μVRMS shown in Figure
6-29 with an output voltage ripple of 280 μVRMS shown in Figure 6-10. The second stage L-C filter attenuates
the output voltage ripple by another approximately 30 dB shown in Figure 6-12. To improve load regulation, the
device can remote sense the output voltage after the second stage L-C filter and is internally compensated for
the additional double pole generated by the L-C filter.
To keep the second stage L-C filter as small as possible, the internal compensation is optimized for a 10-nH
to 50-nH inductance. A small ferrite bead or even a PCB trace provides sufficient inductance for output voltage
ripple filtering. See Section 8.2.2.2.3 for details.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The family of devices are optimized for low noise and low output voltage ripple.
8.2 Typical Applications
Lf
10 nH
Vin
12 V
VIN
CIN
2 x 10 µF
Vo
1.2 V / 3 A
OUT
COUT
3x
22 µF
EN/SYNC
S-CONF
FB
NR/SS
PG
R1
2.43 k
Cf
2 x 22µF
R2
4.87 k
PGND
Figure 8-1. Typical Schematic
Table 8-1 shows the list of components for the application curves in Section 8.2.3, unless otherwise noted.
Table 8-1. List of Components
REFERENCE
TPSM82913
PART NUMBER
TPSM82913
MANUFACTURER(1)
Low-noise and low-ripple buck
module
Texas Instruments
CIN
C2012X7S1E106K125AC
Ceramic capacitors: 2 × 10 µF ±10%
25-V ceramic capacitor X7S 0805
TDK
COUT
C2012X7S1A226M125AC
Ceramic capacitors: 3 × 22 µF, 10 V,
±20%, X7S, 0805
TDK
Ferrite Bead
MuRata
Ceramic capacitor: 2 × 22 µF, 10 V,
±20%, X7S, 0805
TDK
Ceramic capacitor
Standard
Resistor
Standard
Lf
BLE18PS080SN1
Cf
C2012X7S1A226M125AC
CNR/SS, CFF
Optional, not shown
R1, R2
(1)
DESCRIPTION
See the Third-Party Products Disclaimer
8.2.1 Design Requirements
The external components have to fulfill the needs of the application, but also meet the stability criteria of the
control loop of the device. The device is optimized to work within a range of external components, and can be
optimized for the following:
•
20
Efficiency
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•
•
•
SLVSGJ4C – OCTOBER 2022 – REVISED JULY 2023
Output ripple
Component count
Lowest noise
Typical applications that have input voltages of ≤ 6 V use a 2.2-MHz switching frequency. Applications that have
input voltages > 6 V can be optimized for efficiency using a 1-MHz switching frequency. In this case, the output
voltage ripple doubles, which is typically acceptable when powering high speed ADCs. Optimization for powering
clock and PLL circuits that need a 3.3-V output use a 2.2-MHz switching frequency, minimizing output voltage
ripple and low frequency noise.
For the application cases that are not found in Table 8-2, there are two methods to design the TPSM8291x
circuit. Section 8.2.2.1 uses Webench to design the circuit automatically or the calculations in Section 8.2.2.2
can be used instead.
Table 8-2. Typical Single L-C Filter Design Recommendations
DESIGN GOAL
VIN
VOUT
(1)
Typical
(1)
12 V
≤ 2.0 V
FSW
OUTPUT CAPACITORS
1 MHz
3 × 22 µF, 10 V, 0805
Higher efficiency (with
higher ripple and noise)
12 V
2.0 V < VOUT ≤ 3.3 V
1 MHz
3 × 22 µF, 10 V, 0805
Low ripple, noise PLL and
Clock Supply
12 V
2.6 V ≤ VOUT ≤ 3.3 V
2.2 MHz
3 × 22 µF, 10 V, 0805
Typical
12 V
> 3.3 V
2.2 MHz
Typical
5V
≤ 3.3 V
2.2 MHz
3 × 22 µF, 10 V, 0805
2.2 MHz
1 × 47 µF, 1210 and 2 ×
22 µF, 10 V, 0805
Typical
(1)
(2)
5V
> 3.3 V
3
The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This is especially
important for input voltages above 12 V or output voltages below 1 V. See Section 8.2.2.2.1.
For output capacitor part numbers, see Table 8-4.
The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20-μVRMS
noise typically. A second stage filter is added to provide additional attenuation of the output voltage ripple. The
output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter
capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to
Table 8-3 for second stage L-C filter recommendations based on the output voltage.
Table 8-3. Second Stage L-C (Ferrite Bead) Filter Design Recommendations
VOUT (V)
FERRITE BEAD IMPEDANCE (AT 100 MHZ)
(2)
OUTPUT CAPACITORS (1)
≤ 3.3 V
8 Ω to 20 Ω
2 × 22 µF, 10 V, 0805
> 3.3 V
8 Ω to 20 Ω
3 × 22 µF, 10 V, 0805
(1)
(2)
For output capacitor part numbers, see Table 8-4.
For second stage L-C filter part numbers, see Table 8-5.
8.2.2 Detailed Design Procedure
If the specific design is not found in the Table 8-2 section, TI recommends WEBENCH® to generate the design.
Alternatively, the manual design procedure in External Component Selection can be followed.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM8291x device with the WEBENCH® Power Designer.
1.
2.
3.
4.
Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost.
Open the advanced tab to optimize for output voltage ripple.
After in a TPSM8291x design, enable the second stage L-C filter and change other settings from the
drop-down on the left.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 External Component Selection
8.2.2.2.1 Switching Frequency Selection
The switching frequency can be chosen to optimize efficiency (1 MHz) or ripple, noise (2.2 MHz). Using the 2.2MHz setting increases the gain of the feedback loop and can result in lower output noise. However, additional
considerations for minimum on-time and duty cycle must also be considered. First, calculate the duty cycle
using Equation 3. Higher efficiency results in a shorter on-time, so a conservative approach is to use a higher
efficiency than expected in the application.
D
VOUT
VIN uK
(3)
where
• η is the estimated efficiency (use the value from the efficiency curves or 0.9 as an conservative assumption)
Then, calculate the on-time with both 1 MHz and 2.2 MHz using Equation 4. The on-time must always remain
above the minimum on-time of 70 ns. Use the maximum input voltage and maximum efficiency to determine the
minimum duty cycle, Dmin. Use the maximum switching frequency for fSW.
tON _ min
D min
fSW _ max
(4)
then
• If tON_min min < 70 ns with 2.2 MHz, use 1 MHz.
• If tON_min min < 70 ns with 1 MHz, reduce the maximum input voltage.
• If tON_min min ≥ 70 ns for both cases, use 1 MHz for highest efficiency, or 2.2 MHz for lowest noise and ripple.
8.2.2.2.2 Output Capacitor Selection
The effective output capacitance can range from 40 μF (minimum) up to 200 μF (maximum) for a single L-C
system design. When using a second L-C filter, the first L-C filter must have output capacitance between 40
μF and 80 μF, the second stage L-C filter (if used) must have at least 20 μF of capacitance, and the total
capacitance for both L-C filters must be less than 200 μF. Load transient testing and measuring the bode plot are
good ways to verify stability.
TI recommends ceramic capacitors (X5R or X7R). Ceramic capacitors have a DC-Bias effect, which has a strong
influence on the final effective capacitance. Choose the right capacitor carefully in combination with considering
its package size and voltage rating. The ESR and ESL of the output capacitor are also important considerations
in selecting the output capacitors for low noise applications. Smaller package sizes typically have lower ESL
and ESR. 0805 or smaller packages are recommended, as long as they provide the required capacitance and
voltage rating for stable operation. Table 8-4 lists recommended output capacitors.
Table 8-4. Recommended Output Capacitors
CAPACITOR TYPE
CAPACITOR VALUE
MANUFACTURER
VOLTAGE (V)
PACKAGE
Bulk Capacitor
22 μF, X7S
TDK C2012X7S1A226M125AC
10
0805
Bulk Capacitor
47 μF, X7R
Murata GRM32ER71A476ME15L
10
1210
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8.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
Using a ferrite bead for the second stage L-C filter minimizes the external component count because most of the
noise sensitive circuits use a RF bead for high frequency attenuation as a default component at their inputs.
Select a ferrite bead with sufficiently high inductance at full load, and with low DC resistance (below 10 mΩ) to
keep the converter efficiency as high as possible. The ferrite bead inductance decreases with increased load
current. Therefore, the ferrite bead must have a current rating much higher than the desired load current.
The recommendation is to choose a ferrite bead with an impedance of 8 Ω to 20 Ω at 100 MHz. Refer to Table
8-5 for possible ferrite beads.
Table 8-5. Recommended Ferrite Beads
PART NUMBER
MANUFACTURER
SIZE
INDUCTANCE AT
100 MHz
(CALCULATED)
IMPEDANCE AT
100 MHZ
DC RESISTANCE
CURRENT
RATING
BLE18PS080SN1
MuRata
0603
8.5 Ω
13.5 nH
4 mΩ
5A
74279221100
Wurth Elektronik
1206
10 Ω
15.9 nH
3 mΩ
10.5 A
7427922808
Wurth Electronik
0603
8Ω
12.7 nH
5 mΩ
9.5 A
The internal compensation has been designed to be stable with up to 50 nH of inductance in the second stage
filter. To achieve low ripple, the second L-C filter requires only 5-nH to 10-nH inductance. The inductance can
be estimated from the ferrite bead impedance specification at 100 MHz, with the assumption that the inductance
is similar at the selected converter switching frequency of 1 MHz or 2.2 MHz, and can be verified through tools
available on some manufacturer websites. The inductance of a ferrite bead is calculated using Equation 5:
L
Z
2uS u f
(5)
where
•
•
Z is the impedance of the ferrite bead in ohms at the specified frequency (usually 100 MHz)
f is the specified frequency (usually 100 MHz)
8.2.2.2.4 Input Capacitor Selection
For the best output and input voltage filtering, Ti recommends X5R or X7R ceramic capacitors. The input bulk
capacitor minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for
the device. TI recommends a 10-μF or larger input capacitor. Having two in parallel further improves the input
voltage ripple filtering, minimizing noise coupling into adjacent circuits. The voltage rating of the cap must also
be taken into consideration, and must provide the required 5-μF minimum effective capacitance after DC bias
derating.
In addition to the bulk input cap, a smaller cap must be placed directly from the VIN pin to the PGND pin to
minimize input loop parasitic inductance, thereby minimizing the high frequency noise of the device. The input
cap placement affects the output noise, so care must be taken in placing both the bulk cap and bypass caps.
Table 8-6 lists recommended input capacitors.
Table 8-6. Recommended Input Capacitors
INPUT CAP TYPE
CAPACITOR VALUE
MANUFACTURER
Bulk Cap
10 μF, X7S
TDK
C2012X7S1E106K125AC
Bypass Cap
2.2 nF, X7R
Murata
GRM155R71E222KA01D
VOLTAGE RATING (V)
PACKAGE SIZE
25
0805
25
0402
8.2.2.2.5 Setting the Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.8 V to 5.5 V, according to Equation
6. To keep the feedback network robust from noise, and to reduce the self-generated noise of resistors, set R2
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equal to or lower than 5 kΩ. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter
technical brief.
æV
ö
æV
ö
R1 = R2 ´ ç OUT - 1÷ = R2 ´ ç OUT - 1÷
è 0.8V
ø
è VFB
ø
(6)
A feedforward capacitor (CFF) is not required for proper operation, but can further improve output noise.
However, care must be taken in choosing the CFF, because the power-good (PG) function can not be valid
with a large CFF during start-up, and can cause spurious triggering of the PG pin during a large load transient.
Refer to the Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application report for
a discussion of the pros and cons of using a feedforward capacitor.
8.2.2.2.6 NR/SS Capacitor Selection
As described in Section 7.3.8, the NR/SS cap affects both the total noise and the soft-start time. When no
NR/SS cap is connected, there is a default 2.35-ms soft-start time. The recommended value for a 5-ms soft-start
time and good noise performance is 220 nF, as there is an internal 220 nF capacitor already in the module. The
maximum NR/SS cap is 3.3 μF for a start-up time of 35 ms. Values greater than 1 μF have minimal improvement
in noise performance. Use Equation 7 and Equation 8 to calculate the soft-start time based on desired soft-start
time or the chosen capacitor value. Note that the CNRSS in the equation below is the combination of the internal
220 nF cap and any external cap from the CNRSS pin to GND.
tss s =
CNRSS × 0.8
INRSS
(7)
I
× tss
CNRSS F = NRSS
0.8
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8.2.3 Application Curves
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
VIN=12 V, VOUT=1.2 V, TA=25°C, BOM = Table 8-1, (unless otherwise noted)
80
75
70
65
70
60
5 Vin
12 Vin
55
5 Vin
12 Vin
17 Vin
55
50
50
0
0.3
0.6
0.9
0.8 Vout
1.2 1.5 1.8 2.1
Output Current (A)
2.2 μH, 1 MHz
2.4
2.7
3
0
1st L-C Only
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Output Current (A)
1.2 Vout
Figure 8-2. Efficiency vs Load Current
2.2 μH, 1 MHz
2.4
2.7
3
1st L-C Only
Figure 8-3. Efficiency vs Load Current
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
75
65
60
80
75
70
80
75
70
65
65
60
60
5 Vin
12 Vin
17 Vin
55
0
0.3
0.6
0.9
1.8 Vout
1.2 1.5 1.8 2.1
Output Current (A)
2.2 μH, 1 MHz
2.4
2.7
5 Vin
12 Vin
17 Vin
55
50
50
0
3
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Output Current (A)
3.3 Vout
1st L-C Only
2.2 μH, 2.2 MHz
2.4
2.7
3
1st L-C Only
Figure 8-5. Efficiency vs Load Current
Figure 8-4. Efficiency vs Load Current
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
80
80
75
70
65
80
75
70
65
60
60
12 Vin
17 Vin
55
55
50
5 Vin
50
0
0.3
0.6
5 Vout
0.9
1.2 1.5 1.8 2.1
Output Current (A)
2.2 μH, 2.2 MHz
2.4
2.7
3
1st L-C Only
Figure 8-6. Efficiency vs Load Current
0
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Output Current (A)
1.2 Vout
2.2 μH, 2.2 MHz
2.4
2.7
3
1st L-C Only
Figure 8-7. Efficiency vs Load Current
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100
95
90
Efficiency (%)
85
80
75
70
65
60
55
12 V to 1.2 V
1 MHz
300 mA to 3 A to 300 mA
5 Vin
50
0
0.3
0.6
1.8 Vout
0.9
1.2 1.5 1.8 2.1
Output Current (A)
2.2 μH, 2.2 MHz
2.4
2.7
3
1st L-C Only
Figure 8-9. Load Transient
1st L-C Only
Figure 8-8. Efficiency vs Load Current
12 V to 1.2 V
1 MHz
300 mA to 3 A to 300 mA
After 2nd L-C
Figure 8-10. Load Transient
12 V to 1.8 V
1 MHz
300 mA to 3 A to 300 mA
Figure 8-12. Load Transient
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12 V to 1.8 V
1 MHz
300 mA to 3 A to 300 mA
1st L-C Only
Figure 8-11. Load Transient
After 2nd L-C
12 V to 3.3 V
2.2 MHz
300 mA to 3 A to 300 mA
1st L-C Only
Figure 8-13. Load Transient
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12 V to 3.3 V
2.2 MHz
300 mA to 3 A to 300 mA
After 2nd L-C
Figure 8-14. Load Transient
8.3 Power Supply Recommendations
The power supply to the TPSM8291x must have a current rating according to the supply voltage, output voltage,
and output current of the TPSM8291x.
8.4 Layout
8.4.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. Therefore, the PCB layout of the TPSM8291x demands careful attention to ensure best
performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI
radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter
technical brief for a detailed discussion of general best practices. Specific recommendations for the device are
listed below.
•
•
•
•
•
•
•
•
The TPSM8291x has an integrated input capacitor. However, placement of the input capacitors must be
placed as close as possible to the VIN and PGND pins of the device. Route the input capacitors directly to
the VIN and PGND pins avoiding vias.
Place the output capacitor ground close to the PGND pin and route it directly avoiding vias.
Sensitive traces, such as the connections to the NR/SS and FB pins must be connected with short traces and
be routed away from any noise source.
Connect the PSNS pin directly to the system GND plane with a via.
The SW pin must not be connected and must be left floating. If the pin is soldered to PCB copper, the pour
needs to be as small as possible with no inner layer connections. The pin is provided for probing the internal
SW only, and not to be connected to any external component, as shown on the EVM.
Place the second L-C filter, Lf and Cf, near the load to reduce any radiated coupling around the second L-C
filter
Place the FB resistors, R1 and R2, close to the FB pin and route the VOUT connection from R1 to the load as
a remote sense trace. If a second L-C filter is used, this connection must be made after Lf.
The recommended layout is implemented on the EVM and shown in the EVM user's guide.
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8.4.2 Layout Example
VIN
CNRSS
R2
R1
Cff
RSCONF
Text Here
CIN
GND
COUT VOUT
Text Here
GND
Figure 8-15. Recommended Layout for Single L-C Filter
Note
For a single L-C configuration, the feedback sense is placed near the VOUT capacitors. For a second
L-C filter design, the feedback sense is placed near the load after the VOUT_FILT capacitors.
VIN
CNRSS
R2
R1
Cff
RSCONF
Text Here
CIN
GND
VOUT_FILT
COUT
VOUT
Lf
Text Here
Cf
Text Here
GND
Figure 8-16. Recommended Layout for Design with Second L-C Filter
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Note
The ferrite bead can be placed closer to the device as long as it is placed > 8 mm from the device.
This placement avoids capacitive and electromagnetic coupling to the output of the ferrite bead. If the
ferrite bead is placed < 8 mm, the filtering effect of the ferrite bead is greatly reduced. If the ferrite
bead is routed through a via to the back side of the board, ensure adequate ground plane between the
layers if the ferrite bead is in this area.
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.1.2 Development Support
9.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM8291x device with the WEBENCH® Power Designer.
1.
2.
3.
4.
Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost.
Open the advanced tab to optimize for output voltage ripple.
Once in a TPSM8291x design, you can enable the second stage L-C filter and change other settings from
the drop-down on the left.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter technical
brief
Texas Instruments, Five Steps to a Great PCB Layout for a Step-Down Converter technical brief
Texas Instruments, Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application
report
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PTPSM82913RDUR
ACTIVE
B0QFN
RDU
28
1500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
PTPSM2913
Samples
TPSM82912RDUR
ACTIVE
B0QFN
RDU
28
1500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPSM82912
Samples
TPSM82913RDUR
ACTIVE
B0QFN
RDU
28
1500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPSM82913
Samples
TPSM82913RDUR-ET
ACTIVE
B0QFN
RDU
28
1500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
82913-ET
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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