TS3L301DGGG4

TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 FEATURES • • • • • • • • • • • DGG OR DGV PACKAGE (TOP VIEW) Wide Bandwidth (BW = 900 MHz Typ) Low Crosstalk (XTALK = –41 dB Typ) Low Bit-to-Bit Skew [tsk(o) = 0.2 ns Max] Low and Flat ON-State Resistance (ron = 4 Ω Typ, ron(flat) = 0.7 Ω Typ) Low Input/Output Capacitance (CON = 10 pF Typ) Rail-to-Rail Switching on Data I/O Ports (0 to 5 V) VDD Operating Range From 3 V to 3.6 V Ioff Supports Partial Power-Down-Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Suitable for 10-/100-/1000-Mbit Ethernet Signaling VDD A0 GND A1 GND VDD GND A2 GND A3 GND VDD GND NC A4 GND A5 GND VDD GND A6 GND A7 SEL APPLICATIONS • • • • • 10/100/1000 Base-T Signal Switching Differential (LVDS, LVPECL) Signal Switching Digital Video Signal Routing Notebook Docking Signal Routing Hub and Router Signal Switching 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 0B1 1B1 GND 0B2 1B2 GND 2B1 3B1 GND 2B2 3B2 GND VDD 4B1 5B1 GND 4B2 5B2 GND 6B1 7B1 GND 6B2 7B2 NC − No internal connection DESCRIPTION/ORDERING INFORMATION The TS3L301 is a 16-bit to 8-bit multiplexer/demultiplexer local area network (LAN) switch with a single select (SEL) input. The SEL input controls the data path of the multiplexer/demultiplexer. The device provides a low and flat ON-state resistance (ron) and an excellent ON-state resistance match. Low input/output capacitance, high-bandwidth, low skew, and low crosstalk among channels make this device suitable for various LAN applications, such as 10/100/1000 Base-T. ORDERING INFORMATION TA –40°C to 85°C (1) PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel TS3L301DGGR TS3L301 TVSOP – DGV Tape and reel TS3L301DGVR TK301 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 FUNCTION TABLE INPUT SEL INPUT/OUTPUT An FUNCTION L nB1 An = nB1 H nB2 An = nB2 PIN DESCRIPTION NAME DESCRIPTION An Data I/Os nBm Data I/Os SEL Select input LOGIC DIAGRAM (POSITIVE LOGIC) 2 48 4 47 0B1 A0 1B1 A1 45 0B2 44 1B2 8 42 10 41 2B1 A2 3B1 A3 39 2B2 38 3B2 15 35 17 34 4B1 A4 5B1 A5 32 4B2 31 5B2 21 29 6B1 A6 23 28 7B1 A7 26 6B2 25 7B2 SEL 2 24 Submit Documentation Feedback TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VDD Supply voltage range –0.5 4.6 V VIN Control input voltage range (2) (3) –0.5 7 V VI/O Switch I/O voltage range (2) (3) (4) IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±128 mA ±100 mA II/O ON-state switch –0.5 current (5) Continuous current through VDD or GND θJA Package thermal impedance (6) Tstg Storage temperature range (1) (2) (3) (4) (5) (6) 7 DGG package 70 DGV package 58 –65 150 UNIT V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX UNIT VDD Supply voltage 3 3.6 V VIH High-level control input voltage (SEL) 2 5.5 V VIL Low-level control input voltage (SEL) 0 0.8 V VI/O Input/output voltage 0 5.5 V TA Operating free-air temperature –40 85 °C (1) All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 Electrical Characteristics for 1000 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIK SEL VDD = 3.6 V, IIN = –18 mA IIH SEL VDD = 3.6 V, IIL SEL MIN TYP (2) MAX UNIT –1.2 V VIN = VDD ±1 µA VDD = 3.6 V, VIN = GND ±1 µA Ioff VDD = 0, VO = 0 to 3.6 V, VI = 0 IDD VDD = 3.6 V, II/O = 0, Switch ON or OFF CIN SEL f = 1 MHz, VIN = 0 COFF B port –0.7 1 µA 250 600 µA 2.5 3 pF VI = 0, f = 1 MHz, Outputs open, Switch OFF 3.5 4 pF CON VI = 0, f = 1 MHz, Outputs open, Switch ON 10 10.9 pF ron VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA 4 8 Ω VDD = 3 V, VI = 1.5 V and VDD, IO = –40 mA 0.7 VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA 0.2 ron(flat) (3) ∆ron (4) (1) (2) (3) (4) Ω 1.2 Ω VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs. All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C. ron(flat) is the difference of ron in a given channel at specified voltages. ∆ron is the difference of ron from center (A4, A5) ports to any other port. Electrical Characteristics for 10/100 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER TYP (2) MAX –0.7 –1.2 V UNIT VIK SEL VDD = 3.6 V, IIN = –18 mA IIH SEL VDD = 3.6 V, VIN = VDD ±1 µA IIL SEL VDD = 3.6 V, VIN = GND ±1 µA Ioff VDD = 0, VO = 0 to 3.6 V, VI = 0 IDD VDD = 3.6 V, II/O = 0, Switch ON or OFF CIN SEL f = 1 MHz, VIN = 0 COFF B port 1 µA 250 600 µA 2.5 3 pF VI = 0, f = 1 MHz, Outputs open, Switch OFF 3.5 4 pF CON VI = 0, f = 1 MHz, Outputs open, Switch ON 10 10.9 pF ron VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA 4 8 Ω VDD = 3 V, VI = 1.25 V and VDD, IO = –10 mA to –30 mA 0.7 VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA 0.2 ron(flat) (3) ∆ron (4) (1) (2) (3) (4) 4 MIN VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs. All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C. ron(flat) is the difference of ron in a given channel at specified voltages. ∆ron is the difference of ron from center (A4, A5) ports to any other port. Submit Documentation Feedback Ω 1.2 Ω TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 Switching Characteristics over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF (unless otherwise noted) (see Figures 4 and 5) FROM (INPUT) TO (OUTPUT) A or B B or A SEL A or B 1.5 tPHZ, tPLZ SEL A or B 1 tsk(o) (3) A or B B or A PARAMETER tpd (2) tPZH, tPZL MIN TYP (1) 0.25 tsk(p) (4) (1) (2) (3) (4) MAX UNIT ns 11.5 ns 8.5 ns 0.1 0.2 ns 0.1 0.2 ns All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C. The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). Output skew between center port (A4 to A5) to any other port Skew between opposite transitions of the same output in a given device |tPHL – tPLH| Dynamic Characteristics over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER (1) TYP (1) TEST CONDITIONS UNIT XTALK RL = 100 Ω, f = 250 MHz, See Figure 7 –41 OIRR RL = 100 Ω, f = 250 MHz, See Figure 8 –39 dB BW RL = 100 Ω, See Figure 6 900 MHz dB All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C. Submit Documentation Feedback 5 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 OPERATING CHARACTERISTICS 0 −1 −2 Gain − dB −3 −4 −5 −6 −7 −8 −9 1 10 100 1,000 10,000 Frequency − MHz Gain at 900 MHz, −3 dB Figure 1. Gain vs Frequency 0 −20 Off-Isolation − dB −40 −60 −80 −100 −120 1 10 100 1,000 Frequency − MHz OFF Isolation at 250 MHz, −39 dB Figure 2. OFF Isolation vs Frequency 6 Submit Documentation Feedback 10,000 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 OPERATING CHARACTERISTICS (continued) 0 −20 Crosstalk − dB −40 −60 −80 −100 −120 1 10 100 1,000 10,000 Frequency − MHz Crosstalk at 250 MHz, −41 dB Figure 3. Crosstalk vs Frequency Submit Documentation Feedback 7 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) VDD Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VDD Input Generator RL VO VI S1 Open GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VDD S1 RL VI CL V∆ tPLZ/tPZL 3.3 V ± 0.3 V 2 × VDD 200 Ω GND 10 pF 0.3 V tPHZ/tPZH 3.3 V ± 0.3 V GND 200 Ω VDD 10 pF 0.3 V Output Control (VIN) 2.5 V 1.25 V 1.25 V Output Waveform 1 S1 at 2
VDD tPZL (see Note B) 0V tPLZ VOH VDD/2 VOL +0.3 V tPZH Output Waveform 2 S1 at GND (see Note B) VOL tPHZ VDD/2 VOH −0.3 V VOH VOL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 4. Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (Skew) VDD Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VDD Input Generator RL VO VI S1 Open GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VDD S1 RL VI CL tsk(o) 3.3 V ± 0.3 V Open 200 Ω VDD or GND 10 pF tsk(p) 3.3 V ± 0.3 V Open 200 Ω VDD or GND 10 pF 3.5 V 2.5 V 1.5 V Data In at Ax or Ay tPLHx tPHLx VOH (VOH + VOL)/2 VOL Data Out at XB1 or XB2 tsk(o) 3.5 V tsk(o) tPLH VOH (VOH + VOL)/2 VOL Data Out at YB1 or YB2 tPLHy 2.5 V 1.5 V Input tPHLy tPHL VOH (VOH + VOL)/2 VOL Output tsk(p) =
tPLH − tPLH
tsk(o) =
tPLHy − tPLHx
or
tPHLy − tPHLx
VOLTAGE WAVEFORMS OUTPUT SKEW [tsk(o)] VOLTAGE WAVEFORMS PULSE SKEW [tsk(p)] NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 5. Test Circuit and Voltage Waveforms Submit Documentation Feedback 9 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD A0 SEL 0B1 DUT CL = 10 pF (see Note A) VSEL A. CL includes probe and jig capacitance. Figure 6. Test Circuit for Frequency Response (BW) Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the input, the output is measured at 0B1. All unused analog I/O ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 10 Submit Documentation Feedback TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (continued) EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD A0 0B1 RL = 100 Ω A1 1B1 0B2 DUT A2 1B2 2B1 RL = 100 Ω A3 3B1 2B2 3B2 SEL VSEL A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 7. Test Circuit for Crosstalk (XTALK) Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is the input, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B) ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM Submit Documentation Feedback 11 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE www.ti.com SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (continued) EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD A0 0B1 RL = 100 Ω A1 1B1 DUT 0B2 1B2 SEL VSEL A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 8. Test Circuit for Off Isolation (OIRR) OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1 is the input, the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B) ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 12 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TS3L301DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TS3L301 Samples TS3L301DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TS3L301 Samples TS3L301DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TK301 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of