TSC2014IYZGR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 TSC2014 1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Touch Screen Controller with I2C™ Interface 1 Features 3 Description • • • • • • • The TSC2014 is a very low-power touch screen controller designed to work with power-sensitive, handheld applications that are based on advanced low-voltage processors. It works with a supply voltage as low as 1.2V, which can be supplied by a singlecell battery. It contains a complete, ultralow-power, 12-bit, analog-to-digital (A/D) resistive touch screen converter, including drivers and the control logic to measure touch pressure. • • • • • • (1) 4-Wire Touch Screen Interface Ratiometric Conversion Single 1.2V to 3.6V Supply Preprocessing to Reduce Bus Activity High-Speed I2C-Compatible Interface Internal Detection of Screen Touch Register-Based Programmable: – 10-Bit or 12-Bit Resolution – Sampling Rates – System Timing On-Chip Temperature Measurement Touch Pressure Measurement Auto Power-Down Control Low Power: – 430μW at 1.8V, 50SSPS – 320μW at 1.6V, 50SSPS – 190μW at 1.2V, 50SSPS – 58μW at 1.6V, 8.2kSPS Eq. Rate – 37μW at 1.2V, 8.2kSPS Eq. Rate Enhanced ESD Protection: – ±8kV HBM – ±1kV CDM – ±25kV Air Gap Discharge – ±11kV Contact Discharge 1.5 x 2.0 WCSP-12 Package U.S. Patent No. 6,246,394; other patents pending. In addition to these standard features, the TSC2014 offers preprocessing of the touch screen measurements to reduce bus loading, thus reducing the consumption of host processor resources that can then be redirected to more critical functions. The TSC2014 supports an I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. It offers programmable resolution of 10 or 12 bits to accommodate different screen sizes and performance needs. The TSC2014 is available in a miniature, 12-lead, 3 x 4 array, (1.555 ±0.055)mm x (2.055 ±0.055)mm wafer chip-scale package (WCSP) package. The device is characterized for the –40°C to +85°C industrial temperature range. Device Information(1) PART NUMBER TSC2014 PACKAGE DSBGA (12) (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • Cellular Phones Portable Instruments MP3 Players, Pagers Multiscreen Touch Control BODY SIZE (NOM) (1.555 ±0.055)mm x (2.055 ±0.055)mm Block Diagram PENIRQ VDD/REF X+ XY+ Y- PINTDAV DAV Touch Screen Drivers Interface Mux SAR ADC TEMP AUX Internal Clock Pre-Processing 1 SCL 2 I C Serial Interface and Control SDA AD0 RESET Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Electrical Specifications........................................ 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 Absolute Maximum Ratings ..................................... 4 ESD Ratings.............................................................. 4 Thermal Information .................................................. 4 Recommended Operating Conditions....................... 4 Electrical Characteristics........................................... 5 Timing Requirements for Figure 1: I2C Standard Mode (fSCL = 100 kHz) .............................................. 7 6.7 Timing Requirements for Figure 1: I2C Fast Mode (fSCL = 400 kHz) ........................................................ 7 6.8 Timing Requirements for Figure 2: I2C High-Speed Mode (fSCL = 1.7 MHz)............................................... 8 6.9 Timing Requirements for Figure 2: I2C High-Speed Mode (fSCL = 3.4 MHz) .............................................. 8 6.10 Timing Information .................................................. 9 6.11 Typical Characteristics .......................................... 10 7 Detailed Description ............................................ 13 7.1 7.2 7.3 7.4 7.5 7.6 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ........................................................ 13 13 13 22 33 37 Application and Implementation ........................ 51 8.1 Application Information............................................ 51 8.2 Typical Application ................................................. 51 9 Power Supply Recommendations...................... 53 9.1 Power Supply Decoupling Capacitors .................... 53 10 Layout................................................................... 54 10.1 Layout Guidelines ................................................. 54 10.2 Layout Example .................................................... 55 11 Device and Documentation Support ................. 56 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 56 56 56 56 56 12 Mechanical, Packaging, and Orderable Information ........................................................... 56 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2012) to Revision B Page • Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device Functional Modes section, Application and Implementation sectionPower Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...................................................................................................................... 1 • Deleted the ORDERING INFORMATION table...................................................................................................................... 1 Changes from Original (September 2010) to Revision A Page • Changed notes for 100kHz Timing Requirements table......................................................................................................... 7 • Changed notes for 400kHz Timing Requirements table......................................................................................................... 7 • Changed notes for 1.7MHz Timing Requirements table ........................................................................................................ 8 • Changed Fall Time for SDA Signal from 20ns to 1ns for 1.7MHz Timing Requirements table ............................................. 8 • Changed notes for 3.4MHz Timing Requirements table ........................................................................................................ 8 • Changed Fall Time for SDA Signal from 10ns to 1ns for 3.4MHz Timing Requirements table ............................................. 8 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 5 Pin Configuration and Functions YZG Package WCSP-12 (Top View, Solder Bumps on Bottom Side) X+ Y+ X- Y- VDD/REF AD0 RESET GND AUX PINTDAV SDA SCL A B C D Rows 3 2 1 Columns (FRONT VIEW) Pin Assignments WCSP NAME I/O ANALOG/ DIGITAL A1 AUX I A A2 VDD/REF A3 X+ I A X+ channel input B1 PINTDAV O D Interrupt output. Data available or PENIRQ, depending on setting. Pin polarity is active low. B2 AD0 I D Address input bit 0 B3 Y+ I A Y+ channel input C1 SDA I/O D Serial data I/O C2 RESET I D External hardware-reset input C3 X– I A X– channel input D1 SCL I D Serial clock. D2 GND D3 Y– I A DESCRIPTION Auxiliary channel input Supply voltage and external reference input Ground Y– channel input Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 3 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 6 Electrical Specifications 6.1 Absolute Maximum Ratings (1) Over operating free-air temperature range (unless otherwise noted). MIN MAX UNIT Analog input X+, Y+, AUX to GND –0.4 VDD + 0.1 V Analog input X–, Y– to GND –0.4 VDD + 0.1 V VDD/REF pin to GND –0. 5 V –0. VDD + 0.3 V Digital output voltage to GND –0. VDD + 0.3 V Operating free-air temperature range, TA –40 85 °C Storage temperature range, TSTG –65 150 °C 150 °C Voltage range Digital input voltage to GND Junction temperature, TJ Max (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Thermal Information TSC2014 THERMAL METRIC (1) YZG (DSBGA) UNIT 12 PINS θJA Junction-to-ambient thermal resistance 115 °C/W θJCtop Junction-to-case (top) thermal resistance 30 °C/W θJB Junction-to-board thermal resistance 82 °C/W ψJT Junction-to-top characterization parameter 5 °C/W ψJB Junction-to-board characterization parameter 75 °C/W θJCbot Junction-to-case (bottom) thermal resistance — (1) 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) TA 4 MIN NOM MAX Power Supply, VDD/REF 1.2 3.3 3.6 V Operating free-air temperature –40 85 °C Submit Documentation Feedback UNIT Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 6.5 Electrical Characteristics At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. PARAMETER TEST CONDITIONS TSC2014 MIN TYP MAX UNIT AUXILIARY ANALOG INPUT Input voltage range 0 Input capacitance Input leakage current Full-scale average input current VDD 12 –1 VDD = 1.6V, continuous AUX V pF +1 2 μA μA A/D CONVERTER Resolution Programmable: 10 or 12 bits No missing codes 12-bit resolution 12 11 Bits Bits Integral linearity –3 –0.6 to +0.38 Differential linearity –2 –0.46 to +0.49 +4 LSB +3 LSB (1) Offset error VDD = 1.6V –5 0.53 +5 LSB Gain error VDD = 1.6V –3 0.32 +3 LSB TOUCH SENSORS PENIRQ 50kΩ pull-up resistor, RIRQ X, Y drivers on-resistance TA = +25°C, VDD = 1.6V 50 kΩ Ω Y+, X+ TA = +25°C, VDD = 1.6V 6 Y–, X– TA = +25°C, VDD = 1.6V 4.5 X, Y drivers drive current (2) 100ms duration Ω 50 mA INTERNAL TEMPERATURE SENSOR Temperature range –40 Differential method (3) Resolution TEMP1 (4) Differential method (3) Accuracy TEMP1 (4) +85 °C VDD = 1.6V 0.3 °C/LSB VDD = 3V 1.6 °C/LSB VDD = 1.6V 0.3 °C/LSB VDD = 3V 1.6 °C/LSB VDD = 1.6V ±3 °C/LSB VDD = 3V ±2 °C/LSB VDD = 1.6V ±3 °C/LSB VDD = 3V ±2 °C/LSB 3.3 MHz INTERNAL OSCILLATOR VDD = 1.2V, TA = +25°C Clock frequency, fOSC VDD = 1.6V 3.3 VDD = 3.0V, TA = +25°C Frequency drift (1) (2) (3) (4) 3.82 4.3 MHz 4.1 MHz VDD = 1.2V 0.121 %/°C VDD = 1.6V –0.013 %/°C VDD = 3.0V –0.028 %/°C LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610μV. Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. Difference between TEMP1 and TEMP2 measurement; no calibration necessary. Temperature drift is –2.1mV/°C, TEMP2 drift is –1.7mV/°C. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 5 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Electrical Characteristics (continued) At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. PARAMETER TEST CONDITIONS TSC2014 MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS VIH VIL Logic level 1.2V ≤ VDD < 1.6V 0.7 × VDD VDD + 0.3 V 1.6V ≤ VDD ≤ 3.6V 0.7 × VDD VDD + 0.3 V 1.2V ≤ VDD < 1.6V –0.3 0.2 × VDD V 1.6V ≤ VDD ≤ 3.6V –0.3 0.3 × VDD V –1 1 μA IIL SCL and SDA pins CIN SCL and SDA pins 10 pF VOH IOH = 2 TTL loads VDD – 0.2 VDD V VOL IOL = 2 TTL loads 0 0.2 V ILEAK Floating output –1 1 μA COUT Floating output 10 pF 3.6 V 570 μA Data format Straight Binary POWER-SUPPLY REQUIREMENTS Power-supply voltage VDD Specified performance 1.2 Filter off, M = W = 1, C[3:0] = (1,0,0,0), RM = 1, CL[1:0] = (0,1), cont AUX mode, fADC = 2MHz, without reading data register Quiescent supply current (5) VDD = 1.6V 420 TA = +25°C, filter on, M = 15, W = 7, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, fADC = 2MHz, High-Speed mode, sensor drivers supply included (6) VDD = 1.2V 156 μA VDD = 1.6V 200 μA VDD = 3.0V 400 μA TA = +25°C, filter off, M = W = 1, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, fADC = 2MHz, High-Speed mode, sensor drivers supply included (6) VDD = 1.2V 140 μA VDD = 1.6V 180 μA 370 μA 150 μA 200 μA 390 μA VDD = 1.2V, ~10.3kSPS effective rate 272 μA VDD = 1.6V, ~11.8kSPS effective rate 365 μA VDD = 3.0V, ~12.3kSPS effective rate 683 μA VDD = 1.2V, ~1.17kSPS effective rate 30.9 μA VDD = 1.6V, ~1.17kSPS effective rate 36.2 μA VDD = 3.0V, ~1.17kSPS effective rate 64.9 μA VDD = 1.2V, ~27.2kSPS effective rate TA = +25°C, filter off, M = W = 1, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] VDD = 1.6V, ~28.6kSPS effective = (0,1), non-cont AUX mode, fADC rate = 2MHz, High-Speed mode VDD = 3.0V, ~29.1kSPS effective rate TA = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, fADC = 2MHz, High-Speed mode, full speed TA = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, fADC = 2MHz, High-Speed mode, reduced speed (8.2kSPS equivalent rate) Power-down supply current (5) (6) 6 VDD = 3.0V TA = +25°C, Not addressed, SCL = SDA = 1, VDD = 1.6V, RESET = 1, PINTDAV = 1 0.023 0.8 μA For detailed information on test condition parameter and bit settings, see the Digital Interface section. Touch sensor modeled by: 2kΩ for X-plane and Y-plane, and 1kΩ for Z (touch resistance). Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 6.6 Timing Requirements for Figure 1: I2C Standard Mode (fSCL = 100 kHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE STANDARD MODE PARAMETERS Reset low time (1) tWL(RESET) SCL clock frequency fSCL Bus free time between a STOP and START condition tBUF Hold time (repeated) START condition tHD, Low period of SCL clock tLOW High period of the SCL clock TEST CONDITIONS MIN VDD ≥ 1.6V 10 1.2V ≤ VDD < 1.6V 13 MAX UNIT μs μs 100 kHz 4.7 μs 4.0 μs 4.7 μs tHIGH 4.0 μs Setup time for a repeated START condition tSU, STA 4.7 Data hold time tHD, DAT 0 Data setup time tSU, DAT 250 Rise time of both SDA and SCL signals tR Cb = total bus capacitance 1000 ns Fall time of both SDA and SCL signals tF Cb = total bus capacitance 300 ns Setup time for STOP condition tSU, Capacitive load for each bus line Cb 400 pF Pulse width of spike suppressed tSP N/A N/A ns MIN MAX UNIT (1) STA μs 3.45 ns 4.0 STO Cb = total capacitance of one bus line in pF μs μs Refer to Figure 36. 6.7 Timing Requirements for Figure 1: I2C Fast Mode (fSCL = 400 kHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE FAST MODE PARAMETERS TEST CONDITIONS Reset low time (1) tWL(RESET) SCL clock frequency fSCL Bus free time between a STOP and START condition tBUF Hold time (repeated) START condition tHD, Low period of SCL clock tLOW High period of the SCL clock VDD ≥ 1.6V 10 1.2V ≤ VDD < 1.6V 13 μs μs 400 kHz 1.3 μs 0.6 μs 1.3 μs tHIGH 0.6 μs Setup time for a repeated START condition tSU, STA 0.6 Data hold time tHD, DAT 0 Data setup time tSU, DAT 100 Rise time of both SDA and SCL signals tR Cb = total bus capacitance 20 + 0.1 × Cb 300 ns Fall time of both SDA and SCL signals (2) tF Cb = total bus capacitance 20 + 0.1 × Cb 300 ns Setup time for STOP condition tSU, Capacitive load for each bus line Cb 400 pF Pulse width of spike suppressed tSP 50 ns (1) (2) STA μs 0.9 ns 0.6 STO Cb = total capacitance of one bus line in pF 0 μs μs Refer to Figure 36. Cb = the total capacitance of one bus line in pF. If using both Fast mode and Hs-mode devices, faster fall times according to the 3.4MHz High-Speed Mode table are allowed. Note that the TSC2014 is a Hs-mode device and follows the I2C, 3.4MHz, High-Speed Mode table requirements. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 7 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 6.8 Timing Requirements for Figure 2: I2C High-Speed Mode (fSCL = 1.7 MHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN VDD ≥ 1.6V 10 1.2V ≤ VDD < 1.6V 13 MAX UNIT μs Reset low time (1) tWL(RESET) SCL clock frequency fSCL Hold time (repeated) START condition tHD, 160 ns Low period of SCL clock tLOW 320 ns High period of the SCL clock tHIGH 120 ns Setup time for a repeated START condition tSU, STA 160 Data hold time tHD, DAT 0 Data setup time tSU, DAT 10 Rise time of SCL signal tRCL Cb = total bus capacitance (2) 20 80 ns Rise time of SDA signal tRDA Cb = total bus capacitance (2) 20 160 ns Fall time of SCL signal tFCL Cb = total bus capacitance (2) 20 80 ns Fall time of SDA signal tFDA Cb = total bus capacitance (2) 1 160 ns (2) 20 160 ns 400 pF 10 ns STA Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL1 Setup time for STOP condition tSU, Capacitive load for each bus line Cb Pulse width of spike suppressed tSP (1) (2) 6.9 μs 1.7 Cb = total bus capacitance ns 150 Cb = total capacitance of one bus line in pF 0 ns ns 160 STO MHz ns Refer to Figure 36. For capacitive bus loads between 100pF and 400pF, the rise and fall time values must be linearly interpolated. Timing Requirements for Figure 2: I2C High-Speed Mode (fSCL = 3.4 MHz) All specifications typical at –40°C to +85°C, VDD = +1.2V (1) to +3.6V, unless otherwise noted. TWO-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN VDD ≥ 1.6V 10 1.2V ≤ VDD < 1.6V 13 MAX UNIT μs Reset low time (2) tWL(RESET) SCL clock frequency fSCL Hold time (repeated) START condition tHD, 160 ns Low period of SCL clock tLOW 160 ns High period of the SCL clock tHIGH 60 ns Setup time for a repeated START condition tSU, STA 160 Data hold time tHD, DAT 0 Data setup time tSU, DAT 10 Rise time of SCL signal tRCL Cb = total bus capacitance (3) 10 40 ns Rise time of SDA signal tRDA Cb = total bus capacitance (3) 10 80 ns Fall time of SCL signal tFCL Cb = total bus capacitance (3) 10 40 ns Fall time of SDA signal tFDA Cb = total bus capacitance (3) 1 80 ns Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL1 Cb = total bus capacitance (3) 10 80 ns Setup time for STOP condition tSU, Capacitive load for each bus line Cb 100 pF Pulse width of spike suppressed tSP 10 ns (1) (2) (3) 8 μs 3.4 STA ns 70 Cb = total capacitance of one bus line in pF 0 ns ns 160 STO MHz ns Because of the low supply voltage of 1.2V and the wide temperature range of –40°C to +85°C, the I2C system devices may not reach the maximum specification of I2C High-Speed mode, and fSCL may not reach 3.4MHz. Refer to Figure 36. Capacitive load from 10pF to 100pF. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 6.10 Timing Information S Sr P S SDA tSU, STA tSU, DAT tBUF tHD, STA tHD, DAT tLOW SCL tSU, STO tHIGH tHD, STA tR tF S = START Condition Sr = Repeated START Condition P = STOP Condition = Resistor Pull-Up Figure 1. Detailed I/O Timing for Standard and Fast Modes Sr Sr P tFDA tRDA SDA tHD, DAT tSU, STA tHD, STA tSU, STO tSU, DAT SCL tFCL tRCL1(1) tHIGH tLOW tRCL1(1) tRCL tLOW tHIGH = Current Source Pull-Up = Resistor Pull-Up Sr = Repeated START Condition P = STOP Condition NOTE: (1) First rising edge of the SCL signal after Sr and after each acknowledge bit. Figure 2. Detailed I/O Timing for High-Speed Mode Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 9 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 6.11 Typical Characteristics 1.5 1.5 1 1 Delta from +25°C (LSB) Delta from +25°C (LSB) At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, fADC = fOSC/2,High-Speed mode (fSCL = 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted. 0.5 VDD = 1.6V 0 VDD = 1.2V -0.5 VDD = 3.0V VDD = 1.6V 0.5 VDD = 1.2V 0 VDD = 3.0V -0.5 -1 -1 -1.5 -40 -20 0 20 40 Temperature (°C) 60 80 -1.5 -40 100 -20 Figure 3. Change in Offset vs Temperature 0.6 VDD Supply Current (mA) VDD Supply Current (mA) 60 80 100 TA = +25°C VDD = 3.0V 350 300 250 VDD = 1.6V 200 VDD = 1.2V 150 20 40 Temperature (°C) Figure 4. Change in Gain vs Temperature 450 400 0 0.5 fADC = 1MHz 0.4 fADC = 2MHz 0.3 0.2 0.1 100 (1) 50 -40 M = 1, W = 1 -20 0 20 40 Temperature (°C) 60 0 80 1.2 100 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 6. VDD Supply Current vs VDD Supply Voltage Figure 5. VDD Supply Current vs Temperature VDD Supply Current (mA) 0.6 0.5 TA = +25°C tPVS, tPRE, tSNS = Default Values TSC-initiated Mode Scan X, Y, Z at 50SSPS 0.4 (1) M = 15, W = 7 0.3 (1) M = 1, W = 1 0.2 Touch Sensor Modeled by: 2kW for X-Plane 2kW for Y-Plane (2) 1kW for Z (Touch Resistance ) 0.1 0 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 7. VDD Supply Current vs VDD Supply Voltage 1. See Table 1. 2. See Figure 17. 10 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Typical Characteristics (continued) 100 VDD = 3.6V Power-Down Supply Current (nA) Power-Down Supply Current (nA) 1400 1200 VDD = 3.0V 1000 800 600 400 VDD = 1.6V 200 0 -40 TA = +25°C 80 60 40 20 0 -20 0 20 40 Temperature (°C) 60 80 1.2 100 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 9. Power-down Supply Current vs VDD Figure 8. Power-down Supply Current vs Temperature 8 12 11 7 10 9 6 TA = +85°C 4 TA = +25°C RON (W) RON (W) 8 5 7 TA = +85°C 6 5 3 TA = +25°C 4 TA = -40°C 3 2 2 1 TA = -40°C 1 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 1.2 3.6 Figure 10. Switch-on Resistance (XN, YN) vs VDD Supply Voltage 2.4 VDD (V) 2.8 3.2 3.6 590 TA = +25°C 91mV TEMP1 Diode Voltage (mV) Measurement Includes A/D Converter Offset and Gain Errors 800 TEMP Diode Voltage (mV) 2.0 Figure 11. Switch-on Resistance (XP, YP) vs VDD Supply Voltage 850 750 1.6 700 TEMP2 650 600 TEMP1 550 140.1mV 500 Measurement Includes A/D Converter Offset and Gain Errors 588 586 584 582 450 VDD = 1.6V 400 -40 -20 580 0 20 40 Temperature (°C) 60 80 100 1.2 Figure 12. Temp Diode Voltage vs Temperature 1.6 2.0 2.4 VDD (V) 2.8 3.2 Figure 13. TEMP1 Diode Voltage vs VDD Supply Voltage Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 3.6 11 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) 4.4 708 TA = -40°C Measurement Includes A/D Converter Offset and Gain Errors 706 Internal Clock Frequency (MHz) TEMP2 Diode Voltage (mV) TA = +25°C 704 702 700 4 TA = +85°C 3.8 3.6 3.4 TA = +25°C 3.2 3 2.8 698 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 Figure 14. TEMP2 Diode Voltage vs VDD Supply Voltage 12 4.2 3.6 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 15. Internal Oscillator Clock Frequency vs VDD Supply Voltage Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7 Detailed Description 7.1 Overview The TSC2014 is an analog interface circuit for a human interface touch screen device. A register-based architecture eases integration with microprocessor-based systems through a standard I2C bus. All peripheral functions are controlled through the registers and onboard state machines. The TSC2014 features include: • Very low-power touch screen controller • Very small onboard footprint • Relieves host from tedious routine tasks by flexible preprocessing, saving resources for more critical tasks • Ability to work on very low supply voltage • Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required • Miniature, yet complete; requires no external supporting component. • Enhanced ESD protection The TSC2014 consists of the following blocks (refer to the block diagram. • Touch Screen Interface • Auxiliary Input (AUX) • Temperature Sensor • Acquisition Activity Preprocessing • Internal Conversion Clock • I2C Interface 7.2 Functional Block Diagram PENIRQ VDD/REF Touch Screen Drivers Interface Mux SAR ADC Pre-Processing X+ XY+ Y- PINTDAV DAV TEMP AUX Internal Clock SCL 2 I C Serial Interface and Control SDA AD0 RESET Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Touch Screen Operation A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The change in the resistance ratio marks the location on the touch screen. The TSC2014 supports the resistive 4-wire configurations, as shown in Figure 16. The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 13 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.2 4-Wire Touch Screen Coordinate Pair Measurement A 4-wire touch screen is typically constructed as shown in Figure 16. It consists of two transparent resistive layers separated by insulating spacers. Conductive Bar Transparent Conductor (ITO) Bottom Side Y+ X+ Silver Ink Transparent Conductor (ITO) Top Side XY- Insulating Material (Glass) ITO = Indium Tin Oxide Figure 16. 4-Wire Touch Screen Construction The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network. The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+ and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion because of the high input impedance of the A/D converter. Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position on the screen. This process provides the X and Y coordinates to the associated processor. Measuring touch pressure (Z) can also be done with the TSC2014. To determine pen or finger touch, the pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this test; therefore, 10-bit resolution mode is recommended (however, data sheet calculations are shown using the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2014 supports two methods. The first method requires knowing the X-plate resistance, the measurement of the XPosition, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 17). Equation 1 calculates the touch resistance: R TOUCH RX plate ˜ X Position § Z 2 ¨ 4096 ¨© Z 1 · 1¸ ¸ ¹ (1) The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 2 also calculates the touch resistance: R TOUCH 14 RX plate ˜ X Position 4096 § 4096 · 1¸ R Y ¨ ¨ Z1 ¸ © ¹ § plate ˜ ¨ ¨1 © YPOSITION · ¸ 4096 ¸¹ Submit Documentation Feedback (2) Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Feature Description (continued) Measure X-Position X+ Y+ Touch X-Position Y- X- Measure Z1-Position Y+ X+ Touch Z1-Position X- Y- Y+ X+ Touch Z2-Position X- YMeasure Z2-Position Copyright © 2016, Texas Instruments Incorporated Figure 17. Pressure Measurement When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the touch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed. This settling time must be accounted for, or else the converted value will be in error. Therefore, a delay must be introduced between the time the driver for a particular measurement is turned on, and the time a measurement is made. In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these capacitors provides a low-pass filter to reduce the noise, but will cause an additional settling time requirement when the panel is touched. The TSC2014 offers several solutions to this problem. A programmable delay time is available that sets the delay between turning the drivers on and making a conversion. This delay is referred to as the panel voltage stabilization time, and is used in some of the TSC2014 modes. In other modes, the TSC2014 can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the command is issued to perform a conversion. The TSC2014 touch screen interface can measure position (X,Y) and pressure (Z). Determination of these coordinates is possible under three different modes of the A/D converter: • TSMode1 — conversion controlled by the TSC2014 initiated by the TSC; • TSMode2 — conversion controlled by the TSC2014 initiated by the host responding to the PENIRQ signal; or • TSMode3 — conversion completely controlled by the host processor. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 15 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.3 Internal Temperature Sensor In some applications, such as battery recharging, an ambient temperature measurement is required. The temperature measurement technique used in the TSC2014 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2014 offers two modes of temperature measurement. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in Figure 18, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10μA current. The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage is stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3°C/LSB (1LSB = 610μV with VREF = 2.5V). VDD TEMP2 TEMP1 +IN Converter -IN GND Copyright © 2016, Texas Instruments Incorporated Figure 18. Functional Block Diagram of Temperature Measurement Mode The second mode does not require a test temperature calibration, but uses a two-measurement (differential) method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is represented by: 'V kT ˜ In(N) q (3) Where: N = the resistance ratio = 91. k = Boltzmann's constant = 1.3807 × 10-23 J/K (joules/kelvins). q = the electron charge = 1.6022 × 10-19 C (coulombs). T = the temperature in kelvins (K). This method can provide much improved absolute temperature measurement, but a lower resolution of 1.6°C/LSB. The resulting equation to solve for T is: T q ˜ 'V k ˜ ln(N) (4) Where: ΔV = VBE (TEMP2) – VBE(TEMP1) (in mV). ∴ T = 2.573 ⋅ ΔV (in K), or T = 2.573 ⋅ ΔV – 273 (in °C). Temperature 1 and/or temperature 2 measurements have the same timing as Figure 46. 16 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Feature Description (continued) 7.3.4 Analog-to-Digital Converter Figure 19 shows the analog inputs of the TSC2014. The analog inputs (X, Y, and Z touch panel coordinates, chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture, which inherently includes a sample-and-hold function. VDD/REF PINTDAV Level Shift RIRQ(1) 50kW Data Available Pen Touch Control Logic Preprocessing Zone Detect TEMP2 TEMP1 MAV C3-C0 GND X+ X- VDD Y+ +IN Y- +REF Converter -IN -REF GND AUX GND Copyright © 2016, Texas Instruments Incorporated (1) Untrimmed resistor; see the typical value in the Electrical Characteristics Figure 19. Simplified Diagram of the Analog Input Section A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch on-resistances. The A/D converter is controlled by two A/D Converter Control registers. Several modes of operation are possible, depending on the bits set in the control registers. Channel selection, scan operation, preprocessing, resolution, and conversion rate may all be programmed through these registers. These modes are outlined in the sections that follow for each type of analog input. The conversion results are stored in the appropriate result register. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 17 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.4.1 Data Format The TSC2014 output data are in Straight Binary format as shown in Figure 20. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 1LSB 11...111 Output Code 11...110 11...101 00...010 00...001 00...000 0V Input Voltage (2) FS - 1LSB (V) (1) Reference voltage at converter: +REF – (–REF). See Figure 19. (2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 19. Figure 20. Ideal Input Voltages and Output Codes 7.3.4.2 Reference The TSC2014 uses an external voltage reference that applied to the VREF pin. It is possible to use VDD as the reference voltage because the upper reference voltage range is the same as the supply voltage range. 7.3.4.3 Variable Resolution The TSC2014 provides either 10-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers power consumption. 7.3.4.4 Conversion Clock and Conversion Time The TSC2014 contains an internal clock (oscillator) that drives the internal state machines that perform the many functions of the part. This clock is divided down to provide a conversion clock for the A/D converter. The division ratio for this clock is set in the A/D Converter Control register (see Table 14). The ability to change the conversion clock rate allows the user to choose the optimal values for resolution, speed, and power dissipation. If the 4MHz (oscillator) clock is used directly as the A/D converter clock (when CL[1:0] = (0,0)), the A/D converter resolution is limited to 10 bits. Using higher resolutions at this speed does not result in more accurate conversions. 12-bit resolution requires that CL[1:0] is set to (0,1) or (1,0). Regardless of the conversion clock speed, the internal clock runs nominally at 3.8MHz at a 3V supply (VDD) and slows down to 3.6MHz at a 1.6V supply. The conversion time of the TSC2014 depends on several functions. While the conversion clock speed plays an important role in the time it takes for a conversion to complete, a certain number of internal clock cycles are needed for proper sampling of the signal. Moreover, additional times (such as the panel voltage stabilization time), can add significantly to the time it takes to perform a conversion. Conversion time can vary depending on the mode in which the TSC2014 is used. Throughout this data sheet, internal and conversion clock cycles are used to describe the amount of time that many functions take. These times must be taken into account when considering the total system design. 18 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Feature Description (continued) 7.3.4.5 Touch Detect PINTDAV can be programmed to generate an interrupt to the host. Figure 21 details an example for the Yposition measurement. While in the power-down mode, the Y– driver is on and connected to GND. The internal pen-touch signal depends on whether or not the X+ input is driven low. When the panel is touched, the X+ input is pulled to ground through the touch screen and the internal pen-touch output is set to low because of the detection on the current path through the panel to GND, which initiates an interrupt to the processor. During the measurement cycles for X- and Y-Position, the X+ input is disconnected, which eliminates any leakage current from the pull-up resistor to flow through the touch screen, thus causing no errors. Analog VDD Plane VDD/REF PINTDAV VDD Level Shifter Y+ Pen Touch Control Logic TEMP1 High when the X+ or Y+ driver is on. X+ Data Available TEMP2 RIRQ(1) 50kW Sense GND Y- ON High when the X+ or Y+ driver is on, or when any sensor connection/short circuit tests are activated. GND (1) Vias go to system analog ground plane. GND Copyright © 2016, Texas Instruments Incorporated Untrimmed resistor; see the typical value in the Electrical Characteristics Figure 21. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin In modes where the TSC2014 must detect whether or not the screen is still being touched (for example, when doing a pen-touch initiated X, Y, and Z conversion), the TSC2014 must reset the drivers so that the RIRQ resistor is connected again. Because of the high value of this pull-up resistor, any capacitance on the touch screen inputs causes a long delay time, and may prevent the detection from occurring correctly. To prevent this possible delay, the TSC2014 has a circuit that allows any screen capacitance to be precharged, so that the pull-up resistor does not have to be the only source for the charging current. The time allowed for this precharge, as well as the time needed to sense if the screen is still touched, can be set in the configuration register. This configuration underscores the need to use the minimum possible capacitor values on the touch screen inputs. These capacitors may be needed to reduce noise, but too large a value will increase the needed precharge and sense times, as well as the panel voltage stabilization time. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 19 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.4.6 Preprocessing The TSC2014 offers an array of powerful preprocessing operations that reduce unnecessary traffic on the bus and reduce the host processor loading. This reduction is especially critical for the serial interface, where limited bandwidth is a tradeoff, keeping the connection lines to a minimum. All data acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into a predefined range, while other tasks may be looking for a value in a noisy environment. If these data are all to be retrieved by host processor for processing, the limited bus bandwidth quickly saturates, along with the host processor processing capability. In any case, the host processor must always be reserved for more critical tasks, not for routine work. The preprocessing unit consists of two main functions: the combined MAV filter (median value filter and averaging filter), followed by the zone detection. 7.3.4.6.1 Preprocessing—Median Value Filter and Averaging Value Filter The first preprocessing function, a combined MAV filter, can be operated independently as a median value filter (MVF), an averaging value filter (AVF), and a combined filter (MAVF). If the acquired signal source is noisy because of the digital switching circuit, it may be necessary to evaluate the data without noise. In this case, the median value filter (MVF) operation helps to discard the noise. The array of N converted results is first sorted. The return value is either the middle (median value) of an array of M converted results, or the average value of a window size of W of converted results: • N = the total number of converted results used by the MAV filter • M = the median value filter size programmed • W = the averaging window size programmed If M = 1, then N = W. A special case is W = 1, which means the MAVF is bypassed. Otherwise, if W > 1, only averaging is performed on these converted results. In either case, the return value is the averaged value of window size W of converted results. If M > 1 and W = 1, then N = M, meaning only the median value filter is operating. The return value is the middle position converted result from the array of M converted results. If M > 1 and W > 1, then N = M. In this case, W < M. The return value is the averaged value of middle portion W of converted results out of the array of M converted results. Since the value of W is an odd number in this case, the averaging value is calculated with the middle position converted result counted twice (so a total of W + 1 converted results are averaged). Table 1. Median Value Filter Size Selection M1 M0 MEDIAN VALUE FILTER M= POSSIBLE AVERAGING WINDOW SIZE W= 0 0 1 1, 4, 8, 16 0 1 3 1 1 0 7 1, 3 1 1 15 1, 3, 7 Table 2. Averaging Value Filter Size Selection AVERAGING VALUE FILTER SIZE SELECTION W= 20 W1 W0 M = 1 (Averaging Only) M>1 0 0 1 1 0 1 4 3 1 0 8 7 1 1 16 Reserved Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 NOTE The default setting for MAVF is MVF (median value filter with averaging bypassed) for any invalid configuration. For example, if (M1, M0, W1, W0) = (1,0,1,0), the MAVF performs as it was configured for (1,0,0,0), median filter only with filter size = 7 and no averaging. The only exception is M > 1 and (W1, W0) = (1,1). This setting is reserved and should not be used. Table 3. Combined MAV Filter Setting M W INTERPRETATION N= OUTPUT =1 =1 Bypass both MAF and AVF W The converted result =1 >1 Bypass MVF only W Average of W converted results >1 =1 Bypass AVF only M Median of M converted results M Average of middle W of M converted results with the median counted twice >1 >1 M>W The MAV filter is available for all analog inputs including the touch screen inputs, temperature measurements TEMP1 and TEMP2, and the AUX measurement. N measurements input into temporary array N Acquired Data N M=1 N W Averaging output from window W M > 1 and W = 1 N M Median value from array M M > 1 and W > 1 N M Averaging output from window W Sort by descending order W Figure 22. MAV Filter Operation (patent pending) 7.3.4.7 Zone Detection The Zone Detection unit is capable of screening all processed data from the MAVF and retaining only the data of interest (data that fit the prerequisite). This unit can be programmed to send an alert if a predefined condition set by two threshold value registers is met. Three different zones may be set: 1. Above the upper limit (X ≥ Threshold High) 2. Between the two thresholds (Threshold Low < X < Threshold High) 3. Below the lower limit (X ≤ Threshold Low) The AUX and temperatures TEMP1 and TEMP2 have separate threshold value registers that can be enabled or disabled. This function is not available to the touch screen inputs. Once the preset condition is met, the DAV output to the PINTDAV pin is pulled low and the corresponding DAV bit is set. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 21 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.4 Device Functional Modes 7.4.1 I2C Interface The TSC2014 supports the I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. Devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2014 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL. The following bus protocol has been defined (see Figure 23): • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a high-speed mode (3.4MHz clock rate) are each defined. The TSC2014 works in all three modes. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 22 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Device Functional Modes (continued) Figure 23 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends with a STOP condition or a repeated START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The TSC2014 may operate in the following two modes: 1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data are transmitted on SDA by the TSC2014 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. 7.4.1.1 I2C Fast or Standard Mode (F/S Mode) In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information section. In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high, as shown in Figure 23. The bus is free for another transmission after a stop condition has occurred. Figure 23 shows the complete F/S mode transfer on the I2C, two-wire serial interface. The address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in 8bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus acknowledge bit). Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 23 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) P or Sr S SDA MSB Slave Address R/W Direction Bit Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL 1 2 6 7 8 9 1 2 3-8 8 ACK 9 ACK Repeated If More Bytes Are Transferred = Resistor Pull-Up S = START Condition Sr = Repeated START Condition P = STOP Condition Figure 23. Complete Fast- or Standard-Mode Transfer 24 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Device Functional Modes (continued) 7.4.1.2 I2C High-Speed Mode (Hs Mode) Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist: 1. START condition (S) 2. 8-bit master code (00001xxx) 3. not-acknowledge bit (N) Figure 24 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge bit (N). After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to Hs-mode and enables (at time tH; shown in Figure 24) the current-source pull-up circuit for SCL. Because other devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables its currentsource pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus speeding up the last part of the rise time of the SCL. The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up circuit. This disabling enables other devices to delay the serial transfer by stretching the LOW period of SCL. The master re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches a HIGH level, which speeds up the last part of the SCL signal rise time. Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, it is possible that a master links a number of Hs mode transfers, separated by repeated START conditions (Sr). 8-Bit Master Code 00001xxx S N tH SDA SCL 1 2 to 5 6 7 8 9 Fast or Standard Mode R/W 7-Bit Slave Address Sr A n x (8-Bit DATA + A/N) Sr P SDA SCL 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then Fast or Standard Mode High-Speed Mode tH = Current Source Pull-Up = Resistor Pull-Up If Sr (dotted lines) then High-Speed Mode A = Acknowledge (SDA LOW) N = Not Acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = Repeated START Condition tFS Figure 24. Complete High-Speed Mode Transfer Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 25 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) 7.4.2 Touch Screen Measurements As noted previously in the discussion of the A/D converter, several operating modes can be used that allow great flexibility for the host processor. This section examines these different modes. 7.4.2.1 Conversion Controlled by TSC2014 Initiated by TSC2014 (TSMode 1) In TSMode 1, before a pen touch can be detected, the TSC2014 must be programmed with PSM = 1 and one of two scan modes: 1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or 2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001). See Table 9 for more information on the converter function select bits. When the touch panel is touched, and the internal pen-touch signal activates, the PINTDAV output is lowered if it is programmed as PENIRQ. The TSC2014 then executes the preprogrammed scan function without a host intervention. At the same time, the TSC2014 starts up its internal clock. It then turns on the Y-drivers, and after a programmed panel voltage stabilization time, powers up the A/D converter and converts the Y coordinate. If preprocessing is selected, several conversions may take place. When data preprocessing is complete, the Y coordinate result is stored in a temporary register. If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measures the X coordinate instead, and stores the result in a temporary register. If only X and Y coordinates are to be measured, then the conversion process is complete. A set of X and Y coordinates are stored in the X and Y registers. Figure 25 shows a flowchart for this process. The time it takes to go through this process depends upon the selected resolution, internal conversion clock rate, panel voltage stabilization time, precharge and sense times, and whether preprocessing is selected. The time needed to get a complete X and Y coordinate (sample set) reading can be calculated by: t COORDINATE § OH1 2 ˜ ¨ tPVS ¨ f OSC © tPRE tSNS OH DLY1 · ¸ f OSC ¸¹ § § 2 ˜ ¨N ˜ ¨ B ¨ ¨ © © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · · ¨ ¸¸ ¨ f OSC ¸ ¸ © ¹¹ (5) Where: tCOORDINATE = time to complete X/Y coordinate reading. tPVS = panel voltage stabilization time, as given in Table 15. tPRE = precharge time, as given in Table 16. tSNS = sense time, as given in Table 17. N = number of measurements for MAV filter input, as given in Table 3 as N. (For no MAV: M1-0[1:0] = '00', W1-0[1:0] = '00', N = 1.) B = number of bits of resolution. fOSC = TSC onboard OSC clock frequency. See Electrical Characteristics for supply frequency (VDD). fADC = A/D converter clock frequency, as given in Table 14. OH1 = overhead time #1 = 2.5 internal clock cycles. OHDLY1 = total overhead time for tPVS, tPRE, and tSNS = 10 internal clock cycles. OHCONV = total overhead time for A/D conversion = 3 internal clock cycles. LPPRO = preprocessor preprocessing time as given in Table 4. 26 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Device Functional Modes (continued) Table 4. Preprocessing Delay LPPRO = M= W= FOR B = 12 BIT FOR B = 10 BIT 1 1, 4, 8, 16 2 2 3, 7 1 28 24 7 3 31 27 15 1 31 29 15 3 34 32 15 7 38 36 Programmed for Self-Control (PSM = 1) X-Y Scan Mode (Control Byte1 D[6:3] = 0001) TSC Not Addressed Reading X-Data Register Reading Y-Data Register tCOORDINATE Detecting Touch PINTDAV Programmed: Sample, Conversion, and Preprocessing for Y Coordinate Detecting Touch Touch is Detected Sample, Conversion, and Preprocessing for X Coordinate Detecting Touch Sample, Conversion, and Preprocessing for Y Coordinate Detecting Touch Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 Touch is Detected As PENIRQ and DAV, CFR2, D[15:14] = 00 Figure 25. Example of an X and Y Coordinate Touch Screen Scan Using TSMode 1 If the pressure of the touch is also to be measured, the process continues in the same way, but measuring the Z1 and Z2 values instead, and storing the results in temporary registers. Once the complete sample set of data (X, Y, Z1, and Z2) are available, they are loaded in the X, Y, Z1, and Z2 registers. This process is illustrated in Figure 26. As before, this process time depends upon the settings described above. The time for a complete X, Y, Z1, and Z2 coordinate reading is given by: t COORDINATE § OH2 3 ˜ ¨ tPVS ¨ f OSC © tPRE tSNS OH DLY1 · ¸ f OSC ¸¹ § § 4 ˜ ¨N ˜ ¨ B ¨ ¨ © © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · · ¨ ¸¸ ¨ f OSC ¸ ¸ © ¹¹ (6) Where: OH2 = overhead time #2 = 3.5 internal clock cycles. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 27 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Programmed for Self-Control (PSM = 1) X-Y-Z1-Z2 Scan Mode (Control Byte1 D[6:3] = 0000) www.ti.com TSC Not Addressed Reading X-Data Register Reading Reading Y-Data Z1-Data Register Register Reading Z2-Data Register tCOORDINATE Detecting Touch Sample, Conversion, Sample, Conversion, Detecting Detecting and Preprocessing for and Preprocessing for Touch Touch Y Coordinate X Coordinate PINTDAV Programmed: Touch is Detected Touch is Detected Sample, Conversion, Sample, Conversion, Detecting and Preprocessing for and Preprocessing for Touch Y Coordinate Z1 Coordinate and Z2 Coordinate Detecting Touch Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 Touch is Detected As PENIRQ and DAV, CFR2, D[15:14] = 00 Figure 26. Example of an X, Y, and Z Coordinate Touch Screen Scan Using TSMode 1 28 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.4.2.2 Conversion Controlled by TSC2014 Initiated by Host (TSMode 2) In TSMode 2, the TSC2014 detects when the touch panel is touched and causes the internal Pen-Touch signal to activate, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interrupt request, and then writes to the A/D Converter Control register to select one of the two touch screen scan functions: 1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or 2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001). See Table 9 for more information on the converter function select bits. The conversion process then proceeds as shown in Figure 27; see the previous sections for more details. The main difference between this mode and the previous mode is that the host, not the TSC2014, decides when the touch screen scan begins. The time needed to convert both X and Y coordinates under host control (not including the time needed to send the command over the I2C bus) is given by: t COORDINATE § 2 ˜ ¨ tPVS ¨ © OH1 f OSC tPRE tSNS OH DLY1 · ¸ f OSC ¸¹ § § 2 ˜¨N ˜¨ B ¨ ¨ © © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · · ¨ ¸¸ ¨ f OSC ¸ ¸ © ¹¹ (7) Programmed for HostControlled Mode (PSM = 0) TSC Not Programmed Addressed for TSC Not Addressed X-Y Scan Mode Reading X-Data Register Reading Y-Data Register TSC Not Addressed tCOORDINATE Detecting Touch PINTDAV Programmed: Waiting for Host to Write Into Control Byte 1 D[6:3] Sample, Conversion, and Preprocessing for Y Coordinate Detecting Sample, Conversion, Detecting Sample, Conversion, Detecting and Preprocessing for and Preprocessing for Touch Touch Touch X Coordinate Y Coordinate Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 Touch is Detected As DAV, CFR2, D[15:14] = 11 or 01 Touch is Still Here As PENIRQ and DAV, CFR2, D[15:14] = 00 Figure 27. Example of an X and Y Coordinate Touch Screen Scan Using TSMode 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 29 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.4.2.3 Conversion Controlled by Host (TSMode 3) In TSMode 3, the TSC2014 detects when the touch panel is touched and causes the internal Pen-Touch signal to be active, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interrupt request. Instead of starting a sequence in the TSC2014, which then reads each coordinate in turn, the host must now control all aspects of the conversion. Generally, upon receiving the interrupt request, the host turns on the X drivers. NOTE If drivers are not turned on, the device detects this condition and turns them on before the scan starts. This situation is why the event of Turn On Drivers is shown as optional in Figure 28 and Figure 29. After waiting for the settling time, the host then addresses the TSC2014 again, this time requesting an X coordinate conversion. The process is then repeated for the Y and Z coordinates. The processes are outlined in Figure 28 and Table 5. Figure 28 shows two consecutive scans on X and Y. Figure 29 shows a single Z scan. The time needed to convert any single coordinate X or Y under host control (not including the time needed to send the command over the I2C bus) is given by: t COORDINATE OH1 f OSC § ¨ tPRE ¨ © t SNS OH DLY2 · ¸ f OSC ¸¹ § N˜¨ B ¨ © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ (8) Where: OHDLY2 = total overhead time for tPRE and tSNS = 6 internal clock cycles. Programmed for HostControlled Mode (PSM = 0) TSC Not Addressed Programmed for: Turn On X+ and XDrivers (1) X Scan Mode Programmed for: TSC Not Addressed Reading X-Data Register Turn On Y+ and YDrivers (1) Y Scan Mode tCOORDINATE Detecting Touch PINTDAV Programmed: Waiting for Host to Write Into Control Byte 1 D[6:3] Touch is Detected Sample, Conversion, and Preprocessing for X Coordinate TSC Not Reading Addressed Y-Data Register TSC Not Addressed tCOORDINATE Detecting Waiting for Host to Write Into Control Byte 1 D[6:3] Touch Sample, Conversion, and Preprocessing for Y Coordinate Detecting Touch Touch is Detected Waiting for Host to Write Into Control Byte 1 D[6:3] Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 As PENIRQ and DAV, CFR2, D[15:14] = 00 NOTE: (1) Optional. If not turned on, it will be turned on by the Scan mode, once detected. Figure 28. Example of X and Y Coordinate Touch Screen Scan Using TSMode 3 30 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 The time needed to convert any Z1 and Z2 coordinate under host control (not including the time needed to send the command over the I2C bus) is given by: t COORDINATE OH2 f OSC § ¨ tPRE ¨ © OH DLY2 · ¸ f OSC ¸¹ tSNS § N˜¨ B ¨ © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ (9) Programmed for: TSC Not Addressed Programmed for Host-Controlled Mode (PSM = 0) Turn On Y+ and XDrivers(1) TSC Not Addressed Z Scan Mode Reading Z1-Data Register TSC Not Addressed Reading Z2-Data Register tCOORDINATE Detecting Touch Sample, Conversion, Sample, Conversion, and Preprocessing and Preprocessing for Z1 Coordinate for Z2 Coordinate Waiting for Host to Write Into Control Byte 1 D[6:3] PINTDAV Programmed: Detecting Touch Touch is Detected Waiting for Host to Write Into Control Byte 1 D[6:3] Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 As PENIRQ and DAV, CFR2D[15:14] = 00 NOTE: (1) Optional. If not turned on, it will be turned on by the Scan mode, once detected. Figure 29. Example of Z1 and Z2 Coordinate Touch Screen Scan (without Panel Stabilization Time) Using TSMode 3 If the drivers are not turned on before the touch screen scan mode is programmed, the panel stabilization time should be included. In this case, the time needed to convert any single X or Y under host control (not including the time needed to send the command over the I2C bus) is given by: t COORDINATE OH2 f OSC § ¨ tPVS ¨ © tPRE tSNS OH DLY1 · ¸ f OSC ¸¹ § N˜¨ B ¨ © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ (10) Programmed for Host-Controlled Mode (PSM = 0) TSC Programmed Not Addressed for TSC Not Addressed Z1-Z2 Scan Mode Reading Z1-Data Register Reading Z2-Data Register TSC Not Addressed tCOORDINATE Detecting Touch Waiting for Host to Write Into Control Byte 1 D[6:3] PINTDAV Programmed: Sample, Conversion, and Preprocessing for Z1, Z2 Coordinates Detecting Touch Waiting for Host to Write Into Control Byte 1 D[6:3] Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 Touch is Still Here As PENIRQ and DAV, CFR2D[15:14] = 00 Figure 30. Example of a Z1 and Z2 Coordinate Touch Screen Scan (with Panel Stabilization Time) Using TSMode 3 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 31 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com The time needed to convert any single coordinate (either X or Y) under host control (not including the time needed to send the command over the I2C bus) is given by: t COORDINATE § ¨ tPVS ¨ © OH1 f OSC tPRE OH DLY1 · ¸ f OSC ¸¹ tSNS TSC Programmed Not Addressed for Programmed for Host-Controlled Mode (PSM = 0) § N˜¨ B ¨ © 2 ˜ TSC Not Addressed X Scan Mode f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ (11) TSC Not Addressed Reading X-Data Register tCOORDINATE Detecting Touch Waiting for Host to Write Into Control Byte 1 D[6:3] Sample, Conversion, and Preprocessing for X Coordinate Detecting Touch Waiting for Host to Write Into Control Byte 1 D[6:3] PINTDAV Programmed: Touch is Detected As PENIRQ, CFR2, D[15:14] = 10 As DAV, CFR2, D[15:14] = 11 or 01 Touch is Still Here As PENIRQ and DAV, CFR2, D[15:14] = 00 Figure 31. Example of a Single X Coordinate Touch Screen Scan (with Panel Stabilization Time) using TSMode 3 32 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.5 Programming 7.5.1 Digital Interface 7.5.1.1 Address Byte The TSC2014 has a 7-bit slave address word. The first six bits (MSBs) of the slave address are factory-preset to comply with the I2C standard for A/D converters and are always set at '100100'. The logic state of the address input pin determines the LSB of the device address to activate communication. Therefore, a maximum of two devices with the same preset code can be connected on the same bus at one time. The AD0 address input is only read during a power-up of the device, and should be connected to supply (VDD/REF) or ground (GND). The slave address is latched into the TSC2014 on the falling edge of SCL after the read/write bit has been received by the slave. The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2014 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. Table 5. I2C Slave Address Byte MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 1 0 0 1 0 0 AD0 R/W 7.5.1.1.1 Bit D0: R/W 1: I2C master read from TSC (I2C read addressing). 0: I2C master write to TSC (I2C write addressing). I2C Write-Addressing Byte S/Sr 1 0 0 1 0 0 AD0 0 START or Repeated START A From Master to Slave A = Acknowledge (SDA LOW) S = START Condition ACK From Slave to Master Sr = Repeated START Condition I2C Read-Addressing Byte S/Sr 1 0 0 1 0 0 AD0 START or Repeated START 1 A ACK Figure 32. I2C Bus Addressing (Slave Address Byte Format) Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 33 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.5.2 Start A Write Cycle A write cycle begins when the master issues the slave address to the TSC2014. The slave address consists of seven address bits and a write bit (R/W = 0; see Table 5). When the eighth bit has been received and the address matches the AD0 address input pin setting, the TSC2014 issues an acknowledge bit by pulling SDA low for one additional clock cycle (ACK = 0); see Figure 32. When the master receives the acknowledge bit from the TSC2014, the master writes the input control byte to the slave; see Table 5. After the control byte is received by the slave, the slave issues another acknowledge bit by pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or repeated START condition; see Figure 33. Write Cycle START I C Slave Address 2 I C WriteAddressing Byte 0 A 8 Control Byte 1 ACK 1 C3 C2 C1 C0 RM A P STS S 1 SWRST 7 2 STOP(1) Converter Function Select START I C Slave Address 2 I C WriteAddressing Byte 0 A 8 8 Control Byte 0 ACK 0 A3 A2 A1 A0 Rsvd S 1 Data Byte 1/2 (HIGH Byte) A PND0 7 2 8 A Data Byte 2/2 (LOW Byte) A P STOP(1) 0 TSC Internal Register Address for Write Data START I2C Slave Address 2 I C WriteAddressing Byte 0 A 8 Control Byte 0 ACK 0 A3 A2 A1 A0 Rsvd S 1 A P PND0 7 STOP(1) 1 TSC Internal Register Starting Address mh(2) (M + N x 3) x 8 7 S START I2C Slave Address 1 0 A I2C WriteAddressing Byte From Master to Slave From Slave to Master A A A P Mixed M (Control Byte 1 or Control Byte 0 with Read Bit) Plus N (Control Byte 0 with Data Bytes), Separated by TSC ACKs STOP(1) A = Acknowledge (SDA LOW) N = Not Acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = Repeated START Condition NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed mode, the mode will revert to the previous mode: Fast or Standard. (2) mh is a hexadecimal number. Figure 33. Write Cycle 34 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.5.3 Register Access Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit address and a read bit (R/W = 1; see Table 5). When the eighth bit has been received and the address matches, the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial data then follows. After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the acknowledgment from the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends the read cycle, as shown in Figure 34 and Figure 35. If the master issues a not-acknowledge (ACK = 1) after receipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master is not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should stretch the clock. Upon restart of the clock, the second byte of data can be received by the master. Read Cycle: Sequential, from Register Address mh(2) to (m + n)h(3) 7 S START I2C Slave Address 1 8 8 1 Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) A I2C Read-Addressing Byte A A Register (Address = mh) Content 8 Data Byte 1/2 (HIGH Byte) 8 A Data Byte 2/2 (LOW Byte) A Register (Address = (m + 1)h) Content 8 8 NACK Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A Register (Address = (m + n)h) Content P STOP(1) A = Acknowledge (SDA LOW) N = Not Acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = Repeated START Condition From Master to Slave From Slave to Master NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed mode, the mode will revert to the previous mode: Fast or Standard. (2) mh is a hexadecimal number. (3) If (m+n)h is greater than Fh, then (m + n)h is modulo 16. Figure 34. Sequential Read Cycle Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 35 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Read Cycle: Repeated, Register Address mh(2) 7 S START I2C Slave Address START 8 8 NACK 1 Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A I2C Read-Addressing Byte 7 S 1 I2C Slave Address 1 8 8 NACK 1 Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A START I C Slave Address 1 A A P STOP(1) Register (Address = mh) Content 7 S P STOP(1) Register (Address = mh) Content I2C Read-Addressing Byte 2 A 8 8 NACK Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N I2C Read-Addressing Byte A P STOP(1) Register (Address = mh) Content Or... 7 Sr I2C Slave Address 1 8 8 NACK 1 Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A Repeated I2C Read-Addressing Byte START 7 Sr I2C Slave Address Register (Address = mh) Content 1 8 8 NACK 1 Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A Repeated I2C Read-Addressing Byte START I2C Slave Address 1 Repeated I2C Read-Addressing Byte START From Master to Slave From Slave to Master A Register (Address = mh) Content 7 Sr A A 8 8 NACK Data Byte 1/2 (HIGH Byte) Data Byte 2/2 (LOW Byte) N A Register (Address = mh) Content P STOP(1) A = Acknowledge (SDA LOW) N = Not Acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = Repeated START Condition NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed mode, the mode will revert to the previous mode: Fast or Standard. (2) mh is a hexadecimal number. Figure 35. Repeated Read Cycle 36 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.5.4 Register Reset There are three way to reset the TSC2014. • First: At power-on, a power good signal generates a prolonged reset pulse internally to all registers. • Second: An external pin, RESET, is available to perform a system reset or allow other peripherals (such as a display) to reset the device if the pulse meets the timing requirement (at least 10μs wide). Any RESET pulse less than 5μs will be rejected. To accommodate the timing drift between devices because of process variation, a RESET pulse width between 5μs to 10μs falls into the gray area that is not recognized, and the result is undetermined; this situation should be avoided. Refer to Figure 36 for details. A good reset pulse must be low for at least 10 μs. There is an internal spike filter to reject spikes up to 20ns wide. tR tWL(RESET) < 5ms tR tWL(RESET) ³ 10ms RESET State Normal Operation Resetting Initial Condition NOTE: See Timing Requirements for more information. Figure 36. External Reset Timing • Third: A software reset can be activated by writing a '1' to CB1.1 (bit 1 of control byte 1). It should be noted this reset is not self-clearing so the user must write a '0' to remove the software reset. A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take precedence over a software reset. If a software reset is not cleared by the user, it is cleared by either a power-on reset or an external (hardware) reset. NOTE It is required to have the host issue a hardware reset to the TSC2014 after the device power is good and stable to ensure all the registers initialized properly. 7.6 Register Maps 7.6.1 R/W Register read and write control. A '1' indicates that the value of the internal register address bits A3-A0 is stored internally as the starting address for a register read (see Figure 33). The content of the addressed register is sent to SDA by using I2C read addressing (see Figure 34 and Figure 35). A '0' indicates that the data following Control Byte 0 on SDA are written into the internal register addressed by bits A3-A0 (see Figure 33). Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 37 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Register Maps (continued) 7.6.2 Control Byte 0 Figure 37. Control Byte Format: Start a Conversion and Mode Setting MSB D7 D6 D5 D4 D3 (Control Byte 0) A3 A2 A1 A0 D2 Reserved (Write '0') D1 LSB D0 PND0 R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. Control Byte 0 Bit Register Description (D7 = 0) Bit Field Type Reset Description D7 Control Byte ID R/W 0000h 1: Control Byte 1 (start conversion and channel select and conversion-related configuration). 0: Control Byte 0 (read/write data registers and non-conversionrelated controls). D6 A3 R 0000h D5 A2 R 0000h D4 A1 R 0000h D3 A0 R 0000h D2 RESERVED R 0000h A '0' must be set in this bit for normal operation Register Address Bits as detailed in Table 7 D1 PND0 R/W 0000h Power Not Down Control 1: A/D converter biasing circuitry is always on between conversions but is shut down after the converter function stops. 0: A/D converter biasing circuitry is shut down either between conversions or after the converter function stops D0 R/W R/W 0000h TSC Internal Register Data Flow Control 1: Set the starting address of the TSC internal registers for a register read (see Figure 33) 0: Write to TSC internal registers Table 7. Internal Register Map REGISTER ADDRESS 38 REGISTER CONTENT READ/WRITE A3 A2 A1 A0 0 0 0 0 X measurement result R 0 0 0 1 Y measurement result R 0 0 1 0 Z1 measurement result R 0 0 1 1 Z2 measurement result R 0 1 0 0 AUX measurement result R 0 1 0 1 Temp1 measurement result R 0 1 1 0 Temp2 measurement result R 0 1 1 1 Status R 1 0 0 0 AUX high threshold R/W 1 0 0 1 AUX low threshold R/W 1 0 1 0 Temp high threshold (apply to both TEMP1 and TEMP2) R/W 1 0 1 1 Temp low threshold (apply to both TEMP1 and TEMP2) R/W 1 1 0 0 CFR0 R/W 1 1 0 1 CFR1 R/W 1 1 1 0 CFR2 R/W 1 1 1 1 Converter function select status Submit Documentation Feedback R Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.6.3 Control Byte 1 Figure 38. Control Byte Format: Start a Conversion and Mode Setting MSB D7 (Control Byte 1) D6 C3 D5 C2 D4 C1 D3 C0 D2 RM D1 SWRST LSB D0 STS LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. Control Byte 1 Bit Register Description (D7 = 1) Bit Field Type Reset Description D7 Control Byte ID R/W 0000h 1: Control Byte 1 (start conversion and channel select and conversion-related configuration). 0: Control Byte 0 (read/write data registers and non-conversionrelated controls). D6 C3 R 0000h D5 C2 R 0000h D4 C1 R 0000h D3 C0 R 0000h D2 RM R/W 0000h 0: 10 Bit 1: 12 Bit D1 SWRST R/W 0000h Software Reset. This bit is self-clearing. 1: Reset all register values to default D0 STS R/W 0000h Stop bit for all converter functions. This bit is self-clearing. Converter function select bits. These bits select the input to be converted, and the converter function to be executed. Table 9 lists the possible converter functions. Table 9. Converter Function Select C3 C2 C1 C0 FUNCTION 0 0 0 0 Touch screen scan function: X, Y, Z1, and Z2 coordinates converted and the results returned to X, Y, Z1, and Z2 data registers. Scan continues until either the pen is lifted or a stop bit is sent. 0 0 0 1 Touch screen scan function: X and Y coordinates converted and the results returned to X and Y data registers. Scan continues until either the pen is lifted or a stop bit is sent. 0 0 1 0 Touch screen scan function: X coordinate converted and the results returned to X data register. 0 0 1 1 Touch screen scan function: Y coordinate converted and the results returned to Y data register. 0 1 0 0 Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 data registers. 0 1 0 1 Auxiliary input converted and the results returned to the AUX data register. 0 1 1 0 A temperature measurement is made and the results returned to the Temperature Measurement 1 data register. 0 1 1 1 A differential temperature measurement is made and the results returned to the Temperature Measurement 2 data register. 1 0 0 0 Auxiliary input is converted continuously and the results returned to the AUX data register. 1 0 0 1 Touch screen panel connection to X-axis drivers is tested. The test result is output to PINTDAV and shown in STATUS register. 1 0 1 0 Touch screen panel connection to Y-axis drivers is tested. The test result is output to PINTDAV and shown in STATUS register. 1 0 1 1 RESERVED (Note: any condition caused by this command can be cleared by setting the STS bit to 1). 1 1 0 0 Touch screen panel short-circuit (between X and Y plates) is tested through Y-axis. The test result is output to PINTDAV and shown in the STATUS register. 1 1 0 1 X+, X– drivers status 1 1 1 0 Y+, Y– drivers status 1 1 1 1 Y+, X– drivers status Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 39 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.6.3.1 Touch Screen Scan Function for XYZ or XY 7.6.3.1.1 C3-C0 = 0000 or 0001 These scan functions can collaborate with the PSM bit that defines the control mode of converter functions. If the PSM bit is set to '1', these scan function select commands are recommended to be issued before a pen touch is detected in order to allow the TSC2014 to initiate and control the scan processes immediately after the screen is touched. If these functions are not issued before a pen touch is detected, the TSC2014 waits for the host to write these functions before starting a scan process. If PSM stays as '1' after a TSC-initiated scan function is complete, the host is not required to write these function select bits again for each of the following pen touches after the detected touch. In the host-controlled converter function mode (PSM = 0), the host must send these functions select bits repeatedly for each scan function after a detected pen touch. Note that the data registers may be updated while a host reading is in progress. Using the sequential read cycle (see Figure 34) prevents the TSC from updating registers while a host reading is in progress. To ensure that the XYZ or XY coordinates are correctly read, use the sequential read cycle to read the coordinates after the scan. 7.6.3.2 Touch Screen Sensor Connection Tests for X-Axis and Y-Axis Range of resistances of different touch screen panels can be selected by setting the TBM bits in CFR1; see Table 18. Once the resistance of the sensor panel is selected, two continuity tests are run separately for the Xaxis and Y-axis. The unit under test must pass both connection tests to ensure that a proper connection is secured. 7.6.3.2.1 C3-C0 = 1001 PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the X-axis drivers are wellconnected to the sensor; otherwise, X-axis drivers are poorly connected. If drivers fail to connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued. 7.6.3.2.2 C3-C0 = 1010 PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the Y-axis drivers are wellconnected to the sensor; otherwise, Y-axis drivers are poorly connected. If the drivers are fail to connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued. 7.6.3.3 Touch Sensor Short-Circuit Test If the TBM bits of CFR1 detailed in Table 18 are all set to '1', a short-circuit in the touch sensor can be detected. 7.6.3.3.1 C3-C0 = 1011 Reserved. 7.6.3.3.2 C3-C0 = 1100 PINTDAV = 0 during this short-circuit test. A '1' shown at end of the test indicates there is no short-circuit detected (through Y-axis) between the flex and stable layers. If there is a short-circuit detected, PINTDAV stays low until a stop bit (STS set to '1') is issued. 7.6.3.3.3 RM Resolution select. If RM = 1, the conversion result resolution is 12-bit; otherwise, the resolution is 10-bit. This bit is the same RM bit shown in CFR0. 7.6.3.3.4 SWRST Software reset input. All register values are set to default value if a '1' is written to this bit. This bit is automatically set to '0' in order to cancel the software reset and resume normal operation. 40 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com 7.6.3.3.5 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 STS Stop bit for all converter functions. When writing a '1' to this register, this bit aborts the converter function currently running in the TSC2014. A '0' is automatically written to this register in order to end the stop bit. This bit can only stop converter functions; it does not reset any data, status, or configuration registers. This bit is the same STS bit shown in CFR0, but can only be read through the CFR0 register with different interpretations. Table 10. STS Bit Operation OPERATION VALUE Write 0 DESCRIPTION Normal operation Write 1 Stop converter functions and power down Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 41 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.6.4 Communication Protocol The TSC2014 is controlled entirely by registers. Reading and writing to these registers are accomplished by the use of Control Byte 0, which includes a 4-bit address plus one read/write TSC register control bit. The data registers defined in Table 7 are all 16-bit, right-adjusted. NOTE Except for some configuration registers and the Status register that are full 16-bit registers, the rest of the value registers are 12-bit (or 10-bit) data preceded by four (or six) zeros. 7.6.4.1 Configuration Register 0 Figure 39. Configuration Register 0 (Reset Value = 4000h for Read; 0000h for Write) MSB D15 PSM D14 STS D13 RM D12 CL1 D11 CL0 D10 PV2 D9 PV1 D8 PV0 D7 PR2 D6 PR1 D5 PR0 D4 SN2 D3 SN1 D2 SN0 D1 DTW LSB D0 LSM 7.6.4.1.1 PSM Pen status/control mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit selects the mode used to control the flow of converter functions that are either initiated and/or controlled by host or under control of the TSC2014 responding to a pen touch. When reading, the PSM bit indicates if the pen is down or not. When writing to this register, this bit determines if the TSC2014 controls the converter functions, or if the converter functions are host-controlled. The default state is the host-controlled converter function mode (0). The other state (1) is the TSC-initiated scan function mode that must only collaborate with C3-C0 = 0000 or 0001 in order to allow the TSC2014 to initiate and control the scan function for XYZ or XY when a pen touch is detected. Table 11. PSM Bit Operation OPERATION VALUE Read 0 DESCRIPTION No screen touch detected Read 1 Screen touch detected Write 0 Converter functions initiated and/or controlled by host Write 1 Converter functions initiated and controlled by the TSC2014 7.6.4.1.2 STS A/D converter status. When reading, this bit indicates if the converter is busy or not busy. Continuous scans or conversions can be stopped by writing a '1' to this bit, immediately aborting the running converter function (even if the pen is still down) and causing the A/D converter to power down. The default state for write is 0 (normal operation), and the default state for read is 1 (converter is not busy). NOTE: The same bit can be written through Control Byte 1. This bit is self-clearing. Table 12. STS Bit Operation 42 OPERATION VALUE Read 0 DESCRIPTION Converter is busy Read 1 Converter is not busy Write 0 Normal operation Write 1 Stop converter function and power down Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.6.4.1.3 RM Resolution control. The A/D converter resolution is specified with this bit. See Table 13 for a description of these bits. This bit is the same whether reading or writing, and defaults to 0. Note that the same bit can be written through Control Byte 1. Table 13. A/D Converter Resolution Control RM FUNCTION 0 10-bit resolution. Power-up and reset default. 1 12-bit resolution 7.6.4.1.4 CL1, CL0 Conversion clock control. These two bits specify the clock rate that the A/D converter uses to perform conversion, as shown in Table 14. Table 14. A/D Converter Conversion Clock Control (1) CL1 CL0 0 0 FUNCTION fADC = fOSC/1. This is referred to as the 4MHz A/D converter clock rate, 10-bit resolution only (1). 0 1 fADC = fOSC/2. This is referred to as the 2MHz A/D converter clock rate. 1 0 fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate. 1 1 fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate. For VDD = 1.2V at –40°C, a lower A/D converter clock rate should be used to allow enough time for conversion settling. 7.6.4.1.5 PV2-PV0 Panel voltage stabilization time control. These bits specify a delay time from the moment the touch screen drivers are enabled to the time the voltage is sampled and a conversion is started. These bits allow the user to adjust the appropriate settling time for the touch panel and external capacitances. See Table 15 for settings of these bits. The default state is 000, indicating a 0μs stabilization time. These bits are the same whether reading or writing. Table 15. Panel Voltage Stabilization Time Control PV2 PV1 PV0 STABILIZATION TIME (tPVS) 0 0 0 0μs 0 0 1 100μs 0 1 0 500μs 0 1 1 1ms 1 0 0 5ms 1 0 1 10ms 1 1 0 50ms 1 1 1 100ms Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 43 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.6.4.1.6 PR2-PR0 Precharge time selection. These bits set the amount of time allowed for precharging any pin capacitance on the touch screen prior to sensing if a pen touch is happening. Table 16. Precharge Time Selection PR2 PR1 PR0 PRECHARGE TIME(tPRE) 0 0 0 20μs 0 0 1 84μs 0 1 0 276μs 0 1 1 340μs 1 0 0 1.044ms 1 0 1 1.108ms 1 1 0 1.300ms 1 1 1 1.364ms 7.6.4.1.7 SNS2-SNS0 Sense time selection. These bits set the amount of time the TSC2014 waits to sense whether the screen is touched after converting a coordinate. Table 17. Sense Time Selection SNS2 SNS1 SNS0 SENSE TIME (tSNS) 0 0 0 32μs 0 0 1 96μs 0 1 0 544μs 0 1 1 608μs 1 0 0 2.080ms 1 0 1 2.144ms 1 1 0 2.592ms 1 1 1 2.656ms 7.6.4.1.8 DTW Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection in the background while waiting for the host to issue the converter function in host-initiated/controlled modes. This background detection allows the TSC2014 to pull high at PINTDAV to indicate no pen touch detected while waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode until the next pen touch is detected. 7.6.4.1.9 LSM Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normal sampling cycles of each conversion. This additional time is represented as approximately two internal oscillator clock cycles. For VDD = 1.2V at –40°C, the LSM bit should be set to '1' so that the sampled signal has enough time to settle. 44 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.6.4.2 Configuration Register 1 Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection. Figure 40. Configuration Register 1 (Reset Value = 0000h) MSB D15 Resrv d D14 Resrv d D13 Resrv d D12 Resrv d D11 D10 D9 D8 TBM3 TBM2 TBM1 TBM0 D7 D6 D5 D4 D3 D2 D1 LSB D0 Resrvd Resrvd Resrvd Resrvd Resrvd BTD2 BTD1 BTD0 7.6.4.2.1 TBM3-TBM0 Connection test-bit modes (patent pending). These bits specify the mode of test bits used for the predefined range of the combined X-axis and Y-axis touch screen panel resistance (RTS). Table 18. Touch Screen Resistance Range and Test-Bit Modes TEST-BIT MODES TBM3 TBM2 TBM1 TBM0 RTS (kΩ) 0 0 0 0 0.17 0 0 0 1 0.17 < RTS ≤ 0.52 0 0 1 0 0.52 < RTS ≤ 0.86 0 0 1 1 0.86 < RTS ≤ 1.6 0 1 0 0 1.6 < RTS ≤ 2.2 0 1 0 1 2.2 < RTS ≤ 3.6 0 1 1 0 3.6 < RTS ≤ 5.0 0 1 1 1 5.0 < RTS ≤ 7.8 1 0 0 0 7.8 < RTS ≤ 10.5 1 0 0 1 10.5 < RTS ≤ 16.0 1 0 1 0 16.0 < RTS ≤ 21.6 1 0 1 1 21.6 < RTS ≤ 32.6 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Only for short-circuit panel test 7.6.4.2.2 BTD2-BTD0 Batch Time Delay mode. These are the selection bits that specify the delay before a sample/conversion scan cycle is triggered. When it is set, Batch Time Delay mode uses a set of timers to automatically trigger a sequence of sample-and-conversion events. The mode works for both TSC-initiated scans (XYZ or XY) and hostinitiated scans (XYZ or XY). A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. In the case of a TSC-initiated scan (XYZ or XY), the sequence begins with the TSC responding to a pen touch. After the first processed sample set completes during the batch delay, the scan enters a wait mode until the end of the batch delay is reached. If a pen touch is still detected at that moment, the scan continues to process the next sample set, and the batch delay is resumed. The throughput of the processed sample sets (shown in Table 19 as sample sets per second, or SSPS) is regulated by the selected batch delay during the time of the detected pen touch. A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. Note that the throughput of the processed sample set also depends on the settings of stabilization, precharge, and sense times, and the total number of samples to be processed per coordinates. If the accrual time of these factors exceeds the batch delay time, the accrual time dominates. Batch delay time starts when the pen touch initiates the scan function that converts coordinates. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 45 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com A host-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '0' and C[3:0] in Control Byte 1 to '0000' or '0001'. For the host-initiated scan (XYZ or XY), the host must set TSC internal register C[3:0] in Control Byte 1 to '0000' or '0001' initially after a pen touch is detected; see Conversion Controlled by TSC2014 Initiated by Host (TSMode 2) , in the Theory of Operation section. After the scan (XYZ or XY) is engaged, the throughput of the processed sample sets is regulated by the selected batch delay timer, as long as the initial detected touch is not interrupted. Table 19. Touch Screen Throughput and Batch Selection Bits BATCH DELAY SELECTION THROUGHPUT FOR TSC-INITIATED OR HOST-INITIATED SCAN, XYZ OR XY (SSPS) BTD2 BTD1 BTD0 DELAY TIME (ms) 0 0 0 0 Normal operation throughput depends on settings. 0 0 1 1 1000 0 1 0 2 500 0 1 1 4 250 1 0 0 10 100 1 0 1 20 50 1 1 0 40 25 1 1 1 100 10 For example, if stabilization time, precharge time, and sense time are selected as 100μs, 84μs, and 96μs, respectively, and the batch delay time is 2ms, then the scan function enters wait mode after the first processed sample set until the 2ms of batch delay time is reached. When the scan function starts to process the second sample set (if the screen is still touched), the batch delay restarts at 2ms (in this example). This procedure remains regulated by 2ms until the pen touch is not detected or the scan function is stopped by a stop bit or any reset form. 46 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.6.5 Configuration Register 2 Configuration register 2 (CFR2) defines the preprocessor configuration. Figure 41. Configuration Register 2 (Reset Value = 0000h) MSB D15 PINT S1 D14 PINT S0 D13 D12 D11 D10 D9 D8 D7 D6 D5 M1 M0 W1 W0 TZ1 TZ0 AZ1 AZ0 Resrvd D4 MAVE X D3 MAVE Y D2 MAVE Z D1 MAVE AUX LSB D0 MAVE TEMP 7.6.5.1 PINTS1 (default 0) This bit controls the output format of the PINTDAV pin. When this bit is set to '0', the output format is shown as the AND-form of internal signals of PENIRQ and DAV). When this bit is set to '1', PINTDAV outputs PENIRQ only. 7.6.5.2 PINTS0 (default 0) This bit selects what is output on the PINTDAV pin. If this bit set to '0', the output format of PINTDAV depends on the selection made on the PINTS1 bit. If this bit set to '1', the internal signal of DAV is output on PINTDAV. Table 20. PINTSx Selection PINTS1 PINTS0 0 0 PINTDAV PIN OUTPUT = AND combination of PENIRQ (active low) and DAV (active high). 0 1 Data available, DAV (active low). 1 0 Interrupt, PENIRQ (active low) generated by pen-touch. 1 1 Data available, DAV (active low). 7.6.5.3 M1, M0, W1, W0 (default 0000) Preprocessing MAV filter control. Note that when the MAV filter is processing data, the STS bit and the corresponding DAV bits in the status register indicate that the converter is busy until all conversions necessary for the preprocessing are complete. The default state for these bits is 0000, which bypasses the preprocessor. These bits are the same whether reading or writing. 7.6.5.4 TZ1 and TZ0, or AZ1 and AZ0 (default 00) Zone detection bit definition (for TEMP or AUX measurements). TZ1 and TZ0 are for the TEMP measurement. AZ1 and AZ0 are for the AUX measurement. The action taken in zone detection is to store the processed data in the corresponding data registers and to update the corresponding DAV bits in status register. If the processed data do not meet the selected criteria, these data are ignored and the corresponding DAV bits are not updated. When zone detection is disabled, the processed data are simply stored in the corresponding data registers and the corresponding DAV bits are updated without any comparison of criteria. Note that the converted samples are always processed according to the setting of the MAVE bits for AUX/TEMP before zone detection takes effect. See Table 24 for thresholds. Table 21. Zone Detection Bit Definition TZ1/AZ1 TZ0/AZ0 0 0 FUNCTION Zone detection is disabled. 0 1 When the processed data are below low threshold 1 0 When the processed data are between low and high thresholds 1 1 When the processed data are above high threshold 7.6.5.5 MAVE (default is 00000) MAV filter function enable bit. When the corresponding bit is set to '1', the MAV filter setup is applied to the corresponding measurement. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 47 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.6.6 Converter Function Select Register The Converter Function Select (CFN) register reflects the converter function select status. Figure 42. Converter Function Select Status Register (Reset Value = 0000h) MSB D15 CFN1 5 D14 CFN1 4 D13 CFN1 3 D12 CFN1 2 D11 CFN1 1 D10 CFN1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 CFN9 CFN8 CFN7 CFN6 CFN5 CFN4 CFN3 CFN2 CFN1 CFN0 7.6.6.1 CFN15-CFN13 Touch screen drivers status. These bits represent the current status of the touch screen drivers that are turned on. CFN13 is set to '1' if both X+ and X- drivers are turned on. CFN14 is set to '1' if both Y+ and Y- drivers are turned on. CFN15 is set to '1' if Y+ and X- drivers are turned on. Otherwise, these bits are set to '0'. These bits are reset to 0h whenever the converter function is either complete, stopped by the STS bit, or reset (by a hardware reset from the RESET pin or a software reset from SWRST bit in Control Byte 1). 7.6.6.2 CFN12-CFN0 Converter function select status. These bits represent the converter function currently running, which is set in bits C3-C0 of Control Byte 1. When the CFNx bit shows '1', where x is the decimal value of converter function select bits C3-C0, it indicates that the converter function that is set in bits C3-C0 is running. For example, when CFN2 shows '1', it indicates the converter function set in bits C3-C0 ('0010') is running. The CFNx bits are reset to 0000h whenever the converter function is complete, stopped by STS bit, or reset (by the hardware reset from the RESET pin or the software reset from SWRST bit in Control Byte 1). However, if the TSC-initiated scan function mode is issued (by setting the PSM bit in the CFR0 register to '1'), the CFN0 or CFN1 bit will not be reset when the corresponding converter function is complete because there is no pen touch. This event allows the TSC2014 to immediately initiate the scan process (corresponding to CFN0 or CFN1 set to '1') when the next pen touch is detected. Figure 43. STATUS Register (Reset Value = 0004h) MSB D15 D14 D13 D12 D11 DAV Due X DAV Due Y DAV Due Z1 DAV Due Z2 DAV Due AUX D10 D9 D8 D7 DAV DAV RESR Due Due VD RESET TEMP TEMP (read Flag 1 2 '0') D6 D5 X CON Y CON D4 RESRV D (read '0') D3 D2 D1 LSB D0 Y SHR PDST ID1 ID0 7.6.6.3 DAV Bits Data available bits. These seven bits mirror the operation of the internal signals of DAV. When any processed data are stored in data registers, the corresponding DAV bit is set to '1'. It stays at '1' until the register(s) updated to the processed data have been read out by the host. Table 22. DAV Function DAV DESCRIPTION 0 No new processed data are available. 1 Processed data are available. This will stay at 1 until the host has read out all updated registers. 7.6.6.4 RESET Flag See Table 23 for the interpretation of the RESET flag bits. Table 23. RESET Flag Bits RESET Flag 48 DESCRIPTION 0 Device was reset since last status poll (hardware or software reset). 1 Device has not been reset since last status poll. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 7.6.6.5 X CON This bit is '1' if the X axis of the touch screen panel is properly connected to the X drivers. This bit is the connection test result. 7.6.6.6 Y CON This bit is '1' if the Y axis of the touch screen panel is properly connected to the Y drivers. This bit is the connection test result. 7.6.6.7 Y SHR This bit is '1' if there is no short-circuit tested at the Y axis of the touch screen panel. This bit is the short-circuit test result. 7.6.6.8 PDST Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows '0', it indicates A/D converter bias circuitry is still powered on after each conversion and before the next sampling; otherwise, it indicates A/D converter bias circuitry is powered down after each conversion and before the next sampling. However, it is powered down between conversion sets. Because this status bit is synchronized with the internal clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converter function is running. 7.6.6.9 ID[1:0] Device ID bits: These bits represent the version ID of TSC2014. This version defaults to '00'. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 49 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 7.6.7 Data Registers The data registers of the TSC2014 hold data results from conversions. All of these registers default to 0000h upon reset. 7.6.7.1 X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 Registers The results of all A/D conversions are placed in the appropriate data registers, as described in Table 7. The data format of the result word (R) of these registers is right-justified, as shown in Figure 44. The data registers of the TSC2014 hold data results from conversions. All of these registers default to 0000h upon reset. Figure 44. Internal Register Format MSB D15 0 D14 0 D13 0 D12 0 D11 R11 D10 R10 D9 R9 D8 R8 D7 R7 D6 R6 D5 R5 D4 R4 D3 R3 D2 R2 D1 R1 LSB D0 R0 The TSC2014 has several 16-bit registers that allow control of the device, as well as providing a location to store results from the TSC2014 until read out by the host microprocessor. Table 24 shows the memory map. Table 24. Register Content and Reset Values (1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET VALUE (HEX) 0 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 1 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 2 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 3 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 4 AUX 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 5 Temp1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 6 Temp2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 (2) S3 S2 S1 S0 0004 A3-A0 (HEX) (1) (2) 50 REGISTER NAME 7 Status 8 9 Rsvd S15 S14 S13 S12 S11 S10 S9 0 S7 S6 S5 AUX High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF AUX Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 A Temp High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF B Temp Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 C CFR0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 4000 D CFR1 0 0 0 0 R11 R10 R9 R8 0 0 0 0 0 R2 R1 R0 0000 E CFR2 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 0 R4 R3 R2 R1 R0 0000 F Converter Function Select Status R15 R14 R13 R12 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000 Rsvd (2) For all combination bits, the pattern marked as Rsvd (reserved) must not be used. The default pattern is read back after reset. This bit is reserved. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information Communication with the TSC2014 is done via an I2C serial interface. The TSC2014 is an I2C slave device; therefore, data are shifted into or out of the TSC2014 under the control of the host microprocessor, which also provides the serial data clock. Control of the TSC2014 and its functions is accomplished by writing to different registers in the TSC2014. A simple command protocol (compatible with I2C) is used to address these registers. This protocol can be an I2C write-addressing followed by multiple control bytes, or multiple combinations of control/data bytes to be written into different registers (two bytes each). Reading from registers is performed by writing an I2C read-addressing to the TSC, followed by one or multiple sequential reads from the registers. The address of the register to be read can be written in TSC Control Byte 0 with the register address and readbit (as described in the previous paragraph), and serves as a pointer to the register map where the first read starts. This designated register address is static; there is no need to write a register address again unless it is overwritten by a new register address, or if the TSC is reset (by a software reset or by the RESET pin). The measurement result is placed in the TSC2014 registers and may be read by the host at any time. This preprocessing frees up the host so that resources can be redirected for more critical tasks. Two optional signals are also available from the TSC2014 to indicate that data are available for the host to read. PINTDAV is a programmable interrupt/status output pin. When PINTDAV is programmed as a DAV output, it indicates that an A/D conversion has completed and that data are available. When this pin is programmed as a PENIRQ output, it indicates that a touch has been detected on the touch screen. The status register of the TSC2014 provides an extended status reading including the state of DAV and PENIRQ without the cost of any dedicated pin. Figure 45 shows a typical application of the TSC2014. 8.2 Typical Application 1.6VDC 1mF 0.1mF 1.2kW X+ VDD/REF GND Y+ TSC2014 X- Host Processor PENIRQ GPIO RESET GPIO SDA SDA SCL SCL A0 AUX Auxiliary Input GND Y- Touch Screen 1.2kW GND Copyright © 2016, Texas Instruments Incorporated Figure 45. Typical Circuit Configuration Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 51 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Typical Application (continued) 8.2.1 Design Requirements For this design example, use the parameters shown in Table 25. Table 25. Design Parameters PARAMETER VALUE Power Supply 1.6 V VIH ≥ 1.12 Reset VIL ≤ 0.48 Touch Panel 4 Wire 8.2.2 Detailed Design Procedure 8.2.2.1 Auxiliary and Temperature Measurement The TSC2014 can measure the voltage from the auxiliary input (AUX) and from the internal temperature sensor. Applications for the AUX can include external temperature sensing, ambient light monitoring for controlling backlighting, or sensing the current drawn from batteries. There are two converter functions that can be used for the measurement of the AUX: 1. Non-continuous AUX measurement shown in Figure 46 (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0101); or 2. Continuous AUX Measurement shown in Figure 47 (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 1000). See Table 9 for more information on the converter function select bits. There are also two converter functions for the measurement of the internal temperature sensor: 1. TEMP1 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0110); or 2. TEMP2 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0111). See Table 9 for more information on the converter function select bits. For the detailed calculation of the internal temperature sensor, see the Internal Temperature Sensor section. These two converter functions have the same timing as the non-continuous AUX measurement operation as shown in Figure 46; therefore, Equation 12 can also be used for internal temperature sensor measurement. The time needed to make a non-continuous auxiliary measurement or an internal temperature sensor measurement is given by: t COORDINATE OH3 f OSC § N˜¨ B ¨ © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ (12) Where: OH3 = overhead time #3 = 3.5 internal clock cycles. TSC Not Addressed Programmed for Non-Continuous AUX Measurement TSC Not Addressed Reading AUX-Data Register TSC Not Addressed tCOORDINATE No Touch Detected Host Write to Control Byte 1 D[6:3] Sample, Conversion, and Averaging for AUX Measurement Waiting for Host to Read AUX Data No Touch Detected As DAV Figure 46. Non-Touch Screen, Non-Continuous AUX Measurement 52 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 The time needed to make continuous auxiliary measurement is given by: t COORDINATE OH3 f OSC TSC Not Addressed No Touch Detected § N˜¨ B ¨ © 2 ˜ f OSC f ADC · § 1 · OH CONV ¸ ˜ ¨ ¸ ¸ ¨ f OSC ¸ ¹ © ¹ Host to Write to Control Byte 1 D[6:3] (13) TSC TSC Not Reading Not Addressed Reading Addressed AUX-Data AUX-Data Register Register TSC Not Addressed Programmed for Continuous AUX Measurement § L PPRO · ¨ ¸ ¨ f OSC ¸ © ¹ tCOORDINATE tCOORDINATE tCOORDINATE Sample, Conversion, and Averaging for AUX Measurement Sample, Conversion, and Averaging for AUX Measurement Sample, Conversion, and Averaging for AUX Measurement As DAV Figure 47. Non-Touch Screen, Continuous AUX Measurement 8.2.3 Application Curves For application curves, see the figures listed in Table 26. Table 26. Table of Graphs DESCRIPTION FIGURE NUMBER VDD Supply current vs Temperature Figure 5 VDD Supply current vs VDD Figure 6 Power-Down Supply Current vs Temperature Figure 8 RON vs VDD Figure 10 9 Power Supply Recommendations 9.1 Power Supply Decoupling Capacitors TSC2014 should be clean and well-bypassed. A 0.1-μF ceramic bypass capacitor should be added between (VDD/REF and GND). This capacitor must be placed as close to the device as possible. A 1-μF to 10-μF capacitor may also be needed if the impedance of the connection between VDD/REF and the power supply is high. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 53 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 10 Layout 10.1 Layout Guidelines The following layout suggestions should obtain optimum performance from the TSC2014. However, many portable applications have conflicting requirements for power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter power and less concern regarding grounding. Still, each application is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2014 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCL input. With this in mind, power to the TSC2014 should be clean and well-bypassed. A 0.1-μF ceramic bypass capacitor should be added between (VDD/REF and GND). This capacitor must be placed as close to the device as possible. A 1-μF to 10-μF capacitor may also be needed if the impedance of the connection between VDD/REF and the power supply is high. The A/D converter architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input, which is of particular concern when the reference input is tied to the power supply for auxiliary input and temperature measurements. Any noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered out by the built-in MAV filter, voltage variation as a result of line frequency (50Hz or 60Hz) can be difficult to remove. Some package options have pins labeled as NC (no connection). It is recommended that these NC pins be connected to the ground plane. Avoid any active trace going under the analog pins listed in the Pin Assignments table, unless they are shielded by a ground or power plane. The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch-screen applications (for example, applications that require a back-lit LCD panel). This electromagnetic inference (EMI) noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Several things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground, which couples the majority of noise to ground. Another way to filter out this type of noise is by using the TSC2014 built-in MAV filter (see the Preprocessing section). Filtering capacitors, from Y+, Y–, X+, and X– to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and requires longer panel voltage stabilization times, and also increases precharge and sense times for the PINTDAV circuitry of the TSC2014. The resistor value varies depending on the touch screen sensor used. The internal 50kΩ pull-up resistor (RIRQ) may be adequate for most of sensors. 54 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 10.2 Layout Example Decoupling capacitor placed as close as possible to the device AUX 1µF 0.1µF A1 A2 A3 PINTDAV B1 B2 B3 SDA C1 C2 C3 SCL D1 D2 D3 Touch Screen TSC2014 RST Top Layer Ground Plane Top Layer Traces Pad to Top Layer Ground Plane Bottom Layer Traces Via to Bottom Ground Plane Via to Bottom Layer Via to Power Supply plane Figure 48. Example Layout Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 55 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 56 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TSC2014 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TSC2014IYZGR ACTIVE DSBGA YZG 12 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TSC2014I TSC2014IYZGT ACTIVE DSBGA YZG 12 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TSC2014I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of