TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
Analog Channels
– -6 dB to 6 dB Analog Gain
– Analog Input MUXs
– Auto Video Clamp
– Three Digitizing Channels, Each With
Independently Controllable Clamp, PGA,
and ADC
– Clamping: Selectable Clamping Between
Bottom Level and Mid-level
– Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
– PGA: 8-Bit Programmable Gain Amplifier
– ADC: 8/10-Bit 150/110 MSPS A/D Converter
– Automatic Level Control Circuit
– Composite Sync: Integrated Sync-on-Green
Extraction From GreenLuminance Channel
– Support for DC and AC-Coupled Input
Signals
PLL
– Fully Integrated Analog PLL for Pixel Clock
Generation
– 12-150 MHz Pixel Clock Generation From
HSYNC Input
– Adjustable PLL Loop Bandwidth for
Minimum Jitter
– 5-Bit Programmable Subpixel Accurate
Positioning of Sampling Phase
Output Formatter
– Support for RGB/YCbCr 4:4:4 and YCbCr
4:2:2 Output Modes to Reduce Board Traces
– Dedicated DATACLK Output for Easy
Latching of Output Data
System
– Industry-Standard Normal/Fast I2C Interface
With Register Readback Capability
– Space-Saving TQFP-100 Pin Package
– Thermally-Enhanced PowerPAD™ Package
for Better Heat Dissipation
LCD TV/Monitors/Projectors
DLP TV/Projectors
PDP TV/Monitors
PCTV Set-Top Boxes
Digital Image Processing
Video Capture/Video Editing
Scan Rate/Image Resolution Converters
Video Conferencing
Video/Graphics Digitizing Equipment
DESCRIPTION
TVP7000 is a complete solution for digitizing video
and graphic signals in RGB or YPbPr color spaces.
The device supports pixel rates up to 150 MHz.
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of SXGA (1280 × 1024)
resolution at 75 Hz screen refresh rate, and in video
environments for the digitizing of digital TV formats,
including HDTV up to 1080p. TVP7000 can be used
to digitize CVBS and S-Video signal with 10-bit
ADCs.
The TVP7000 is powered from 3.3-V and 1.8-V
supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,
independently programmable for each channel. The
clamping timing window is provided by an external
pulse or can be generated internally. The TVP7000
includes analog slicing circuitry on the Y or G input to
support sync-on-luminance or sync-on-green extraction. In addition, TVP7000 can extract discrete
HSYNC and VSYNC from composite sync using a
sync slicer.
TVP7000 also contains a complete analog PLL block
to generate a pixel clock from the HSYNC input. Pixel
clock output frequencies range from 12 MHz to 150
MHz.
All programming of the part is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7000 is
available in a space-saving TQFP 100-pin PowerPAD
package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
ORDERING INFORMATION
PACKAGED DEVICES
TA
100-PIN PLASTIC FLATPACK PowerPAD™
0°C to 70°C
TVP7000PZP
FUNCTIONAL BLOCK DIAGRAM
RIN_1
RIN_2
RIN_3
Clamp
PGA
10−bit
ADC
ROUT[9:0]
GIN_1
GIN_2
GIN_3
Clamp
PGA
10−bit
ADC
GOUT[9:0]
GIN_4
BIN_1
BIN_2
BIN_3
Output
Formatter
Clamp
PGA
10−bit
ADC
BOUT[9:0]
SOGIN_1
SOGIN_2
DATACLK
SOGOUT
SOGIN_3
HSYNC_A
HSOUT
VSOUT
HSYNC_B
VSYNC_A
VSYNC_B
Timing Processor
and Clock generation
COAST
CLAMP
EXT_CLK
FILT1
FILT2
PWDN
RESETB
SCL
SDA
I2CA
2
Host
Interface
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GIN_2
SOGIN_2
GIN_3
SOGIN_3
GIN_4
A33GND
A33VDD
A33VDD
A33GND
NSUB
PLL_A18GND
PLL_F
FILT2
FILT1
PLL_A18GND
PLL_A18VDD
PLL_A18VDD
PLL_A18GND
HSYNC_B
HSYNC_A
EXT_CLK
VSYNC_B
VSYNC_A
COAST
CLAMP
TERMINAL ASSIGNMENTS
TVP7000
100−Pin TQFP Package
(Top View)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SDA
SCL
I2CA
TMS
RESETB
PWDN
DVDD
GND
IOGND
IOVDD
R_0
R_1
R_2
R_3
R_4
IOGND
R_5
R_6
R_7
R_8
R_9
IOGND
IOVDD
G_0
G_1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IOVDD
IOGND
DATACLK
B_9
B_8
B_7
B_6
B_5
B_4
B_3
B_2
B_1
B_0
DVDD
GND
IOVDD
IOGND
G_9
G_8
G_7
G_6
G_5
G_4
G_3
G_2
SOGIN_1
GIN_1
A18GND
A18VDD
A18GND
A18VDD
A18VDD
A18GND
RIN_3
RIN_2
RIN_1
A33GND
A33VDD
A33VDD
A33GND
BIN_3
BIN_2
BIN_1
A18VDD
A18GND
NSUB
TEST
VSOUT
HSOUT
SOGOUT
3
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
11
10
9
2
100
98
96
18
17
16
I
I
I
I
I
I
I
I
I
I
Analog video input for R/Pr 1
Analog video input for R/Pr 2
Analog video input for R/Pr 3
Analog video input for G/Y 1
Analog video input for G/Y 2
Analog video input for G/Y 3
Analog video input for G/Y 4
Analog video input for B/Pb 1
Analog video input for B/Pb 2
Analog video input for B/Pb 3
The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µF. Unused analog
inputs should be connected to ground using a 10 nF capacitor.
DATACLK
28
O
Data clock output
EXT_CLK
80
I
External clock input for free running mode
TEST
22
O
Internal 5 MHz clock output, coast output, high-Z, or SOG output
55–59, 61–65
43-52
29-38
O
O
O
Digital video output of R/Cr, ROUT [9] is MSB.
Digital video output of G/Y, GOUT [9] is MSB.
Digital video output of B/Cb, BOUT [9] is MSB. For a 4:2:2 mode BOUT outputs CbCr data.
NAME
NO.
ANALOG VIDEO
RIN_1
RIN_2
RIN_3
GIN_1
GIN_2
GIN_3
GIN_4
BIN_1
BIN_2
BIN_3
CLOCK SIGNALS
DIGITAL VIDEO
ROUT [9:0]
GOUT [9:0]
BOUT [9:0]
Unused outputs can be left unconnected.
MISCELLANEOUS SIGNALS
PWDN
70
I
Power down input. 1: Power down 0: Normal mode
RESETB
71
I
Reset input, active low
TMS
72
I
Test Mode Select input. Used to enable JTAG test mode. Active high. Normal mode, this terminal
should be connected to a ground.
FILT1
87
O
External filter connection for PLL. The recommended capacitor is 0.1 µF. see Figure 4
FILT2
88
O
External filter connection for PLL. The recommended capacitor is 4.7 nF. See Figure 4
I2C A
73
I
I2C Address input
SCL
74
I
I2C Clock input
SDA
75
I/O
21, 91
I
Substrate ground. Connect to analog ground.
A33VDD
13, 14, 93, 94
I
Analog power. Connect to 3.3 V.
A33GND
12, 15, 92, 95
I
Analog 3.3 V return. Connect to Ground.
A18GND
3, 5, 8, 20
I
Analog 1.8V return. Connect to Ground
A18VDD
4, 6, 7, 19
I
Analog power. Connect to 1.8 V.
84, 85
I
PLL analog power. Connect to 1.8 V.
89
I
PLL filter internal supply connection
83, 86, 90
I
PLL analog power return. Connect to Ground.
GND
40, 68
I
Digital return. Connect to Ground.
DVDD
39, 69
I
Digital power. Connect to 1.8 V
IOGND
27, 42, 54, 60,
67
I
IOVDD
26, 41, 53, 66
I
Digital power. Connect to 3.3 V or less for reduced noise.
CLAMP
76
I
External Clamp input. Unused inputs can be connected to ground.
COAST
77
I
External PLL COAST signal input. Unused inputs can be connected to ground
HOST INTERFACE
I2C Data bus
POWER SUPPLIES
NSUB
PLL_A18VDD
PLL_F
PLL_A18GND
Digital power return. Connect to Ground.
SYNC SIGNALS
4
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VSYNC_A
VSYNC_B
78
79
I
I
Vertical sync input A
Vertical sync input B. Unused inputs can be connected to ground.
HSYNC_A
HSYNC_B
81
82
I
I
Horizontal Sync input A
Horizontal Sync input B. Unused inputs can be connected to ground.
SOGIN1
SOGIN2
SOGIN3
1
99
97
I
I
i
Sync-on-green input 1
Sync-on-green input 2
Sync-on-green input 3. Unused inputs should be connected to ground using a 10 nF capacitor.
VSOUT
23
O
Vertical sync output
HSOUT
24
O
Horizontal sync output
SOGOUT
25
O
Sync-on-green slicer output
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range
–0.5 V to 4.5 V
DVDD to GND
–0.5 V to 2.3 V
PLL_A18VDD to PLL_A18GND and A18VDD to A18GND
–0.5 V to 2.3 V
A33VDD to A33GND
– 0.5 V to 4.5 V
Digital input voltage range
VI to GND
–0.5 V to 4.5 V
Analog input voltage range
AI to A33GND
–0.2 V to 2.3 V
Digital output voltage range
VO to GND
–0.5 V to 4.5 V
TA
Operating free-air temperature
Tstg
Storage temperature
(1)
IOVDD to IOGND
0°C to 70°C
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, TA = 0°C to 70°C (unless otherwise noted)
MIN
NOM
MAX
3.0
3.3
3.6
V
Digital supply voltage
1.70
1.8
1.9
V
PLL_A18VDD
Analog PLL supply voltage
1.70
1.8
1.9
V
A18VDD
Analog supply voltage
1.70
1.8
1.9
V
A33VDD
Analog supply voltage
3.0
3.3
3.6
V
VI(P–P)
Analog input voltage (ac–coupling necessary)
2.0
V
VIH
Digital input voltage high
VIL
Digital input voltage low
IOH
High–level output current
2
mA
IOL
Low–level output current
–2
mA
IOH_DATACLK
DATACLK high–level output current
4
mA
IOL_DATACLK
DATACLK low–level output current
–4
mA
TA
Operating free–air temperature
70
°C
IOVDD
Digital I/O supply voltage
DVDD
0.5
0.7 IOVDD
V
0.3 IOVDD
0
UNIT
V
5
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
IOVDD = 3.3 V, DVDD = 1.8 V, PLL_A18VDD = 1.8 V, A18VDD = 1.8 V, A33VDD = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX (2)
UNIT
POWER SUPPLY
IIOVDDD
3.3-V supply current
78.75 MHz
80
130
IDVDD
1.8-V supply current
78.75 MHz
253
260
mA
PTOT
Total power dissipation, normal mode
78.75 MHz
719
897
mW
IIOVDDD
3.3-V supply current
108 MHz
101
160
mA
IDVDD
1.8-V supply current
108 MHz
261
275
mA
PTOT
Total power dissipation, normal mode
108 MHz
803
1023
mW
IIOVDDD
3.3-V supply current
148.5 MHz
128
240
mA
IDVDD
1.8-V supply current
148.5 MHz
250
280
mA
PTOT
Total power dissipation, normal mode
148.5 MHz
872
1296
mW
PDOWN
Total power dissipation, power–down mode
(1)
(2)
6
SMPTE color bar RGB input pattern used.
Worst case vertical line RGB input pattern used.
1
mA
mW
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
IOVDD = 3.3 V, DVDD = 1.8 V±0.1, PLL_A18VDD = 1.8 V±0.1, A18VDD = 1.8 V±0.1, A33VDD = 3.3 V, TA = 0°C to 70°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.0
2.0
Vpp
ANALOG INTERFACE
ZI
Input voltage range
By design
Input impedance, analog video inputs
By design
0.5
500
kΩ
DIGITAL LOGIC INTERFACE
Ci
Input capacitance
By design
10
pF
Zi
Input impedance
By design
500
kΩ
VOH
Output voltage high
IOH = 2 mA
VOL
Output voltage low
IOL = –2 mA
VOH_SCLK
DATACLK output voltage high
IOH = 4 mA
VOL_SCLK
DATACLK output voltage low
IOH = –2 mA
VIH
High-level input voltage
By design
VIL
Low-level input voltage
By design
0.8 IOVDD
V
0.2 IOVDD
0.8 IOVDD
V
V
0.2 IOVDD
0.7 IOVDD
V
V
0.3 IOVDD
V
A/D CONVERTERS
Conversion rate
DNL
DC differential nonlinearity
INL
DC integral nonlinearity
SNR
12
150
10 bit, 110 MHz
-1
±0.5
+1
8 bit, 150 MHz
-1
±0.5
+1
10 bit, 110 MHz
-4
±1
+4
8 bit, 150 MHz
-4
±1
+4
Missing code
8 bit, 150 MHz
Signal-to-noise ratio
10 MHz, 1.0 VP–P at 110
MSPS
Analog bandwidth
By design
MSPS
LSB
LSB
none
52
dB
500
MHz
PLL
Clock jitter
500
ps
Phase adjustment
11.6
degree
VCO frequency range
12
150
MHz
7
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
TIMING REQUIREMENTS
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
CLOCKS, VIDEO DATA, SYNC TIMING
Duty cycle DATACLK
50%
t1
DATACLK rise time
10% to 90%
t2
DATACLK fall time
90% to 10%
t3
Output delay time
(1)
1
1
1.5
Measured with a load of 15 pF.
t1
DATACLK
t2
R, R, B, HSOUT
Valid Data
Valid Data
t3
Figure 1. Clock, Video Data, and Sync Timing
8
ns
ns
3.5
ns
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
TIMING REQUIREMENTS
PARAMETER
I2C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HOST PORT TIMING
t1
Bus free time between STOP and START
Specified by design
1.3
µs
t2
Setup time for a (repeated) START condition
Specified by design
0.6
µs
t3
Hold time (repeated) START condition
Specified by design
0.6
µs
t4
Setup time for a STOP condition
Specified by design
0.6
ns
t5
Data setup time
Specified by design
100
ns
t6
Data hold time
Specified by design
0
0.9
µs
t7
Rise time SDA and SCL signal
Specified by design
250
ns
t8
Fall time SDA and SCL signal
Specified by design
250
ns
Cb
Capacitive load for each bus line
Specified by design
400
pF
f12C
I2C clock frequency
Specified by design
400
kHz
Stop Start
Stop
SDA
Data
t1
t6
t6
t3
t2
t7
t8
t4
t5
SCL
Figure 2. I2C Host Port Timing
9
TVP7000
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SLES143 – SEPTEMBER 2005
FUNCTIONAL DESCRIPTION
Analog Channel
The TVP7000 contains three identical analog channels that are independently programmable. Each channel
consists of a clamping circuit, a programmable gain amplifier, automatic offset control and an A/D converter.
Analog Input Switch Control
TVP7000 has 3 analog channels that accept up to 10 video inputs. The user can configure the internal analog
video switches via the I2C interface. The 10 analog video inputs can be used for different input configurations
some of which are:
• Up to 10 selectable individual composite video inputs
• Up to 2 selectable RGB graphics inputs
• Up to 3 selectable YPbPr video HD/SD inputs
The input selection is performed by the input select register at I2C subaddress 0×19 and 0×1A (see Input Mux
Select 1 and Input Mux Select 2)
Analog Input Clamping
An internal clamping circuit restores the AC-coupled video/graphic signal to a fixed DC level. The clamping circuit
provides line-by-line restoration of the signal black level to a fixed DC reference voltage. The selection between
bottom and mid level clamping is performed by I2C subaddress 0×10 (see Sync On_Green Threshold)
The internal clamping time can be adjusted by I2C clamp start and width registers at subaddress 0×05 and 0×06
(see Clamp Start and Clamp Width)
Programmable Gain Amplifier (PGA)
The TVP7000 PGA can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit
A/D output code range. A 4-bit code sets the coarse gain (Red Coarse Gain, Green Coarse Gain, Blue Coarse
Gain) with individual adjustment per channel. Minimum gain corresponds to a code 0×0 (2-Vpp full-scale input,
–6 dB gain) while maximum gain corresponds to code 0×F (0.5-Vpp full-scale, +6 dB gain). TVP7000 also has
8-bit fine gain control (Red Fine Gain, Green Fine Gain, Blue Fine Gain) for RGB independently ranging from 1
to 2. For a normal PC graphics input, the fine gain will be used mostly.
Programmable Offset Control and Automatic Level Control (ALC)
The TVP7000 supports a programmable offset control for RGB independently. A 6-bit code sets the coarse offset
(Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The
coarse offset ranges from –32 LSB to +31 LSB. The coarse offset registers apply before the ADC. A 10-bit fine
offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges
from –512 LSB to +511 LSB.
ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I2C register. It
consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by I2C register
address at 0×26. ALC circuit needs a timing pulse generated internally but user should program the position
properly. The ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by
ALC placement I2C register at address 0×31. This is available only for internal ALC pulse timing. For external
clamp, the timing control of clamp is not applicable so the ALC pulse control is also not applicable. Therefore it is
suggested to keep the external clamp pulse as long as possible. ALC is applied as same position of external
clamp pulse.
A/D Converters
All ADCs have a resolution of 10-bits and can operate up to 150 MSPS. All A/D channels receive an identical
clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 150 MHz. All ADC
reference voltages are generated internally. Also the external sampling clock can be used.
10
TVP7000
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SLES143 – SEPTEMBER 2005
Analog PLL
The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to
derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal
sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded
sync signals. The analog PLL consisted of phase detector, loop filter, voltage controlled oscillator (VCO), divider
and phase select. The analog block diagram is shown at Figure 3.
PLL Control
Register 0x03
Bit [5:3]
PLL Control
Register 0x03
Bit [7:6]
Phase Select
Register 0x04
Bit [7:3]
VCO
Phase
Select
COAST
HSYNC
Phase
Detector
Charge
Pump
Loop
Filter
÷N
N = 1 or 2
ADC
Sampling
CLK
Divider
External
Clock
PLL Divide
Register 0x01
and 0x02
Bit [11:0]
Figure 3. PLL Block Diagram
The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the
incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other
time that the HSYNC is not available.
There are several PLL controls to produce the correct sampling clock. The 12-bit divider register is
programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to 150
MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass
loop filter. The applicable current values are listed in the Table 1.
The 2-bit VCO range control is to improve the noise performance of the TVP7000. The frequency ranges for the
VCO are shown in Table 1. The phase of the PLL generated clock can be programmed in 32 uniform steps over
a single clock period (360/32=11.25 degrees phase resolution) so that the sampling phase of the ADC can be
accurately controlled.
In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from pin 80).
The PLL characteristics are determined by the loop filter design, by the PLL charge pump current, and by the
VCO range setting. The loop filter design is shown in Figure 4. Supported settings of VCO range and charge
pump current for VESA standard display modes are listed in Table 1.
11
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
89
PLL_F
4.7 nF
88
1.5 kΩ
87
0.1 µF
FILT2
FILT1
TVP7000
Figure 4. PLL Loop Filter
Table 1. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display
Formats
STANDARD
RESOLUTION
REFRESH
RATE
HORIZONTAL
FREQUENCY
(kHz)
PIXEL RATE
(MHz)
PLL Divider
Total
pix/line
PLLDIV
MSB Reg
01h
PLLDIV LSB
Reg 02h
[11:4]
Reg 03h
Output Divider Reg
04h [0]
VCO
RANGE Reg
03h [7:6]
CP CURRENT Reg
03h [5:3]
VGA
640 × 480
60 Hz
31.5
25.175
1600(2×)
64h
00h
68h
1
Low (01b)
101b
72 Hz
37.9
31.5
1664(2×)
68h
00h
58h
1
Low (01b)
011b
75 Hz
37.5
31.5
1680(2×)
69h
00h
58h
1
Low (01b)
011b
85 Hz
43.3
36
832
34h
00h
68h
0
Low (01b)
101b
56 Hz
35.1
36
1024
40h
00h
68h
0
Low (01b)
101b
60 Hz
37.9
40
1056
42h
00h
68h
0
Low (01b)
101b
72 Hz
48.1
50
1040
41h
00h
68h
0
Low (01b)
101b
75 Hz
46.9
49.5
1056
42h
00h
68h
0
Low (01b)
101b
85 Hz
53.7
56.25
1048
41h
80h
68h
0
Low (01b)
101b
60 Hz
48.4
65
1344
54h
00h
58h
0
Low (01b)
011b
70 Hz
56.5
75
1328
53h
00h
A8h
0
Med (10b)
101b
75 Hz
60
78.75
1312
52h
00h
A8h
0
Med (10b)
101b
85 Hz
68.7
94.5
1376
56h
00h
A8h
0
Med (10b)
101b
60 Hz
64
108
1688
69h
80h
A8h
0
Med (10b)
101b
75 Hz
80
135
1688
69h
80h
98h
0
Med (10b)
011b
720 × 480p
60 Hz
31.468
27
1716(2×)
6Bh
40h
68h
1
Low (01b)
101b
720 × 576p
50 Hz
31.25
27
1728(2×)
6Ch
00h
68h
1
Low (01b)
101b
1280 × 720p
60 Hz
45
74.25
1650
67h
20h
A8h
0
Med (10b)
101b
1280 × 720p
50 Hz
37.5
74.25
1980
7Bh
C0h
A8h
0
Med (10b)
101b
1920 × 1080i
60 Hz
33.75
74.25
2200
89h
80h
A8h
0
Med (10b)
101b
1920 × 1080i
50 Hz
28.125
74.25
2640
A5h
00h
A8h
0
Med (10b)
101b
1920 ×
1080p
60 Hz
67.5
148.5
2200
89h
80h
D8h
0
High (11b)
011b
1920 ×
1080p
50 Hz
56.25
148.5
2640
A5h
00h
D8h
0
High (11b)
011b
SVGA
XGA
SXGA
Video
800 × 600
1024 × 768
1280 × 1024
Sync Slicer
TVP7000 includes a circuit that compares the input signal on Green channel to a level 150mV (typical value)
above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 0x10. The
digital output of the composite sync slicer is available on the SOGOUT pin.
Sync Separator
The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at
the SOG input. The G or Y input containing the composite sync must be AC coupled to the SOG input pin using
a 10-nF capacitor. Support for PC graphics, SDTV, and HDTV up to 1080p is provided.
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Activity
Detect
SOGOUT
SYNC
Slicer
SOG
SYNC
Separator
Activity
Detect
5MHz
CLK
HSYNC
Activity
Detect
VSYNC
VSOUT
Polarity
Detect
COAST
HSYNC
Clock
Generation
HSOUT
COAST
DATACLK
Phase
Select
DIV
ADC
Figure 5. Sync Processing
Timing
The TVP7000 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing
diagrams are shown for operation with internal PLL clock at phase 0. For a 4:2:2 mode, CbCr data outputs at
BOUT[9:0] pins.
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RGBin
P0
P1
P3
P10
P11
P12
HSYNC
DATACLK
13 clocks latency
D0
RGBout
D1
D3
D4
D5
Programmable Width
HSOUT
4:4:4: RGB/YCbCr Output Timing
RGBin
P0
P1
P3
P10
P11
P12
HSYNC
DATACLK
13 clocks latency
GOUT
Y0
Y1
Y2
Y3
Y4
BOUT
Cb0
Cr0
Cb2
Cr2
Cb4
HSOUT
Programmable Width
4:2:2 YCbCr Output Timing
Figure 6. Output Timing Diagram
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2
I C Host Interface
Communication with the TVP7000 device is via an I2C host interface. The I2C standard consists of two signals,
serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices
connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be
multi-mastered, the TVP7000 can function as a slave device only.
Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven, the user should
connect SDA and SCL to a positive supply voltage via a pull up resistor on the board. SDA is implemented
bi-directional. The slave addresses select, terminal 73 (I2CA), enables the use of two TVP7000 devices tied to
the same I2C bus since it controls the least significant bit of the I2C device address
Table 2. I2C Host Interface Terminal Description
SIGNAL
TYPE
I2C A
I
Slave address selection
DESCRIPTION
SCL
I
Input clock line
SDA
I/O
Input/output data line
Reset and I2C Bus Address Selection
TVP7000 can respond to two possible chip addresses. The address selection is made at reset by an externally
supplied level on the I2C A pin. The TVP7000 device samples the level of terminal 73 at power- up or at the
trailing edge of RESETB and configures the I2C bus address bit A0. The I2C A terminal has an internal pull-down
resistor to pull the terminal low to set a zero.
Table 3. I2C Host Interface Device Addresses
A6
A5
A4
A3
A2
A1
A0 (I2C A)
R/W
HEX
1
0
1
1
1
0
0 (default)
1/0
B9/B8
1
0
1
1
1
0
1 (1)
1/0
BB/BA
If terminal 73 strapped to DVDD via a 2.2 kΩ resistor, I2C device address A0 is set to 1.
(1)
I2C Operation
Data transfers occur utilizing the following illustrated formats.
S
10111000
ACK
subaddress
ACK
send data
ACK
P
Read from I2C control registers
S
10111000
ACK
subaddress
ACK
S
10111001
ACK
receive data
NAK
S=
I2C Bus Start condition
P=
I2C Bus Stop condition
ACK =
Acknowledge generated by the slave
NAK =
Acknowledge generated by the master, for multiple byte read master with ACK each byte except last byte
Subaddress =
Subaddress byte
Data =
Data byte, if more than one byte of DATA is transmitted (read and write), the subaddress pointer is automatically
incremented
I2C bus address =
Example shown that I2C A is in default mode. Write (B8h), Read (B9h)
P
Power-up, Reset, and Initialization
No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of
each other. Reset may be low during power-up, but must remain low for at least 1 µs after the power supplies
become stable. Alternately reset may be asserted any time with minimum 5 ms delay after power-up and must
remain asserted for at least 1 µs. Reset timing is shown in Figure 7. It is also recommended that any I2C
operation starts 1 µs after reset ended. Table 4 describes the status of the TVP7000 terminals during and
immediately after reset.
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Table 4. Reset Sequence
SIGNAL NAME
DURING RESET
RESET COMPLETED
ROUT[9:0], BOUT[9:0], BOUT[9:0]
High impedence
Output
HSOUT, VSOUT, SOGOUT
High impedence
Output
DATACLK
High impedence
Output
5 ms
1 µs
1 µs
Power
Reset
I2C
Figure 7. Reset Timing
Control Registers
The TVP7000 is initialized and controlled by a set of internal registers that define the operating parameters of the
entire device. Communication between the external controller and the TVP7000 is through a standard I2C host
port interface, as described earlier.
Table 5 shows the summary of these registers. Detailed programming information for each register is described
in the following sections.
Table 5. Control Registers Summary (1) (2)
Register Name
I2C Subaddress
Default
R/W
Chip Revision
00h
PLL Divide MSB
01h
69h
R/W
PLL Divide LSB
02h
D0h
R/W
PLL Control
03h
48h
R/W
Phase Select
04h
80h
R/W
Clamp Start
05h
80h
R/W
Clamp Width
06h
80h
R/W
HSYNC Output Width
07h
20h
R/W
Blue Fine Gain
08h
80h
R/W
Green Fine Gain
09h
80h
R/W
Red Fine Gain
0Ah
80h
R/W
Blue Fine Offset
0Bh
80h
R/W
Green Fine Offset
0Ch
80h
R/W
Red Fine Offset
0Dh
80h
R/W
Sync Control 1
0Eh
40h
R/W
PLL and Clamp Control
0Fh
4Eh
R/W
(1)
(2)
16
R
Register addresses not shown in the register map summary are reserved and must not be written to.
Writing to or reading from any value labeled “Reserved” register may cause erroneous operation of the TVP7000. For registers with
reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.
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Table 5. Control Registers Summary (continued)
I2C Subaddress
Default
R/W
Sync On Green Threshold
10h
B8h
R/W
Sync Separator Threshold
11h
20h
R/W
Pre-Coast
12h
00h
R/W
Post-Coast
13h
00h
R/W
Sync Detect Status
14h
Output Formatter
15h
00h
R/W
16h
00h
R/W
Register Name
Test Register
Reserved
R
17h–18h
Input Mux Select 1
19h
00h
R/W
Input Mux Select 2
1Ah
00h
R/W
Blue and Green Coarse Gain
1Bh
55h
R/W
Red Coarse Gain
1Ch
05h
R/W
Fine Offset LSB
1Dh
00h
R/W
Blue Coarse Offset
1Eh
20h
R/W
Green Coarse Offset
1Fh
20h
R/W
Red Coarse Offset
20h
20h
R/W
HSOUT Output Start
21h
09h
R/W
MISC Control
22h
00h
R/W
00h
R/W
00h
R/W
00h
R/W
Reserved
23h–25h
Automatic Level Control Enable
26h
Reserved
27h
Automatic Level Control Filter
28h
Reserved
29h
Fine Clamp Control
2Ah
Power Control
2Bh
ADC Setup
2Ch
00h
R/W
Coarse Clamp Control 1
2Dh
00h
R/W
SOG Clamp
2Eh
00h
R/W
00h
R/W
Reserved
2Fh–30h
ALC Placement
31h
R = Read only
W = Write only
R/W = Read Write
Register Definitions
Chip Revision
Subaddress
7
00h
Read Only
6
5
4
3
2
1
0
Chip revision [7:0]
Chip revision [7:0]: Chip revision number
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PLL Divide
Subaddress
01h–02h
7
Default (69D0h)
6
5
4
3
2
1
0
PLL divide MSB [11:4]
PLL divide LSB [3:0]
Reserved
PLL divide [11:0]: PLL divide number sets the number of pixels per line. Controls the PLL feedback divider. MSB [11:4] bits should be
loaded first whenever a change is required
PLL Control
Subaddress
03h
7
Default (48h)
6
5
VCO[1:0]
4
3
Charge Pump Current [3:1]
2
1
0
Reserved
Reserved
Reserved
VCO [1:0]: Selects VCO frequency range
00 = Ultra low
01 = Low (default)
10 = Medium
11 = High
Charge Pump Current [3:0]: Selects charge current of PLL LPF
000 = Small (default)
111 = Large
Phase Select
Subaddress
04h
7
Default (80h)
6
5
4
3
2
Phase Select [4:0]
1
Reserved
0
DIV2
Phase Select [4:0]: ADC Sampling clock phase select. (1 LSB = 360/32 = 11.25°)
DATACLK Divide-by-2
0 = DATACLK/1
1 = DATACLK/2
Clamp Start
Subaddress
05h
7
Default (80h)
6
5
4
3
2
1
0
Clamp Start [7:0]
Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected
this value has no meaning
Clamp Width
Subaddress
7
06h
Default (80h)
6
5
4
3
Clamp Width [7:0]
Clamp Width [7:0]: Sets the width in pixels for clamp. See register Clamp Start.
18
2
1
0
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Table 6. Recommended Fine Clamp Settings
VIDEO STANDARD
CLAMP START
CLAMP WIDTH
HDTV (tri-level)
50 (32h)
32 (20h)
SDTV (bi-level)
6 (06h)
16 (10h)
PC Graphics
6 (06h)
16 (10h)
HSYNC Output Width
Subaddress
07h
7
Default (20h)
6
5
4
3
2
1
0
HSOUT Width [7:0]
HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.
Blue Fine Gain
Subaddress
08h
7
Default (80h)
6
5
4
3
2
1
0
Blue Gain [7:0]
Blue Gain [7:0]: PGA digital gain (contrast) for Blue channel applied after the ADC. Gain = 1 + Blue Gain[7:0]/256
80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).
Green Fine Gain
Subaddress
09h
7
Default (80h)
6
5
4
3
2
1
0
Green Gain [7:0]
Green Gain [7:0]: PGA digital gain (contrast) for Green channel applied after the ADC. Gain = 1 + Green Gain[7:0]/256
80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).
Red Fine Gain
Subaddress
7
0Ah
Default (80h)
6
5
4
3
2
1
0
Red Gain [7:0]
Red Gain [7:0]: Sets PGA digital gain (contrast) for Red channel applied after the ADC. Gain = 1 + Red Gain[7:0]/256
80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).
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Blue Fine Offset
Subaddress
0Bh
7
Default (80h)
6
5
4
3
2
1
0
Blue Offset [9:2]
Blue Offset [9:2]: DC digital offset (brightness) for Blue channel applied after the ADC.
The default setting of 80h will place the bottom-level (YRGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank
levels at 512.
Blue Offset
Description
11111111
maximum
100000001
1 LSB
10000000
0 (default)
01111111
–1 LSB
00000000
minimum
Green Fine Offset
Subaddress
0Ch
7
Default (80h)
6
5
4
3
2
1
0
Green Offset [9:2]
Green Offset [9:2]: DC digital offset (brightness) for Green channel applied after the ADC. See Red Fine Offset register at I2C address 0x0B
Red Fine Offset
Subaddress
7
0Dh
Default (80h)
6
5
4
3
2
1
0
Red Offset [9:2]
Red Offset [9:2]: DC digital offset (brightness) for Red channel applied after the ADC. See Blue Fine Offset register at I2C address 0x0B.
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Sync Control 1
Subaddress
0Eh
Default (40h)
7
6
5
4
3
2
1
0
HSPO
HSIP
HSOP
AHSO
AHSS
VSOI
AVSO
AVS
HSPO: HSYNC Polarity Override
0 = Polarity determined by chip (default)
1 = Polarity set by Bit 6 in register 0Eh
HSIP: HSYNC Input Polarity
0 = Indicates input HSYNC polarity active low
1 = Indicates input HSYNC polarity active high (default)
HSOP: HSYNC Output Polarity
0 = Active low (default)
1 = Active high
AHSO: Active HSYNC Override
0 = The active interface is selected via Bit 6 in register 14h, selected by chip (default)
1 = The user can select HSYNC to be used via Bit 3
AHSS: Active HSYNC Select. The indicated HSYNC will be used only if Bit 4 is set to 1 or both syncs are active (Bits 1,7 =1 in 14h)
0 = Select HSYNC as the active sync (default)
1 = Select Sync-on-green as the active sync
VSOI: VSYNC Output Invert (relative to VSYNC IN polarity)
0 = No invert (default)
1 = Invert
AVSO: Active VSYNC Override
0 = The active interface is selected via Bit3 in register 14h, selected by chip (default)
1 = The user can select the VSYNC to be used via Bit 0
AVS: Active VSYNC select, This bit is effective when AVSO Bit 1 is set to 1.
0 = Raw VSYNC (default)
1 = Sync separated VSYNC
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PLL and Clamp Control
Subaddress
0Fh
Default (4Eh)
7
6
5
4
3
2
1
0
CF
CP
Coast Sel
CPO
CPC
Reserved
FCPD
Free run
Clamp Function:
0 = Internal Clamp(default)
1 = External Clamp
Clamp Polarity:
0 = Active high
1 = Active low (default)
Coast Select:
0 = External coast (default)
1 = Internal Coast
Coast Polarity Override:
0 = Polarity determined by chip (default)
1 = Polarity set be Bit 3 in register 0Fh
Coast Polarity Change:
0 = Active low
1 = Active high (default)
Full Chip Power-Down:
0 = Power-down mode
1 = Normal operation (default)
Free run: Also ADC test mode, ADC uses external clock
0 = PLL normal operation (default)
1 = Enabled
Sync On_Green Threshold
Subaddress
7
10h
Default (B8h)
6
5
4
SOG Threshold [4:0]
3
2
1
0
Blue CS
Green CS
Red CS
SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator. The minimum setting is 0 mV and the maximum is 350 mV. The
step is 11 mV. (default 17h, 10h recommended)
Blue Clamp Select: When free running mode this bit is no effect
0 = Bottom level clamp (default)
1 = Mid level clamp
Green Clamp Select: When free running mode this bit is no effect
0 = Bottom level clamp (default)
1 = Mid level clamp
Red Clamp Select: When free running mode this bit is no effect.
0 = Bottom level clamp (default)
1 = Mid level clamp
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Sync Separator Threshold
Subaddress
11h
7
Default (20h)
6
5
4
3
2
1
0
Sync Separator Threshold [7:0]
Sync Separator Threshold [7:0]: Sets how many internal 5 MHz clock periods the sync separator will count to before toggling high or low.
The selection of this register affects the VSYNC out position relative to HSYNC out.
Pre-Coast
Subaddress
12h
7
Default (00h)
6
5
4
3
2
1
0
Pre-Coast [7:0]
Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC.
Post-Coast
Subaddress
13h
7
Default (00h)
6
5
4
3
2
1
0
Post-Coast [7:0]
Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC.
Table 7. Recommended Pre and Post-Coast Settings
STANDARD
PRE_COAST
POST-COAST
480i/p with Macrovision
3
0Ch
576i/p with Macrovision
3
0Ch
1080i
3
0
1080p
0
0
720p
0
0
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Sync Detect Status
Subaddress
14h
Read Only
7
6
5
4
3
2
1
0
HSD
AHS
IHSPD
VSD
AVS
VSPD
SOGD
ICPD
HSYNC Detect:
0 = No HSYNC detected
1 = HSYNC detected
Active HSYNC:
0 = HSYNC input pin
1 = HSYNC from SOG
Input HSYNC Polarity Detect:
0 = Active low
1 = Active high
VSYNC Detect:
0 = No VSYNC detected
1 = VSYNC detected
AVS:
0 = VSYNC input pin
1 = VSYNC from Sync separator
VSYNC Polarity Detect:
0 = Active low
1 = Active high
SOG Detect:
0 = No SOG detected
1 = SOG is present on the SOG interface
Input Coast Polarity Detect:
0 = Active low
1 = Active high
Output Formater
Subaddress
15h
7
Default (00h)
6
5
Reserved
4
3
2
1
0
Clamp REF
CbCr order
422/444
Reserved
Clamp REF:
0 = Clamp pulse placement respect to the trailing edge of HSYNC (default)
1 = Clamp pulse placement respect to the leading edge of HSYNC
CbCr order: This bit is effective when Bit 1 is set to 1.
0 = CrCb (default)
1 = CbCr
422/444:
0 = Output is in 4:4:4 format (default)
1 = Output is in 4:2:2 format
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Test Register
Subaddress
16h
7
Default (00h)
6
5
4
Pixel tolerance [2:0]
3
Reserved
2
Test ouptut
1
0
PLL PD
STRTB
Pixel tolerance:
000 = No tolerance (default)
001 = 1 pixel tolerance (recommended setting for best SOG performance)
111 = 7 pixel tolerance (maximum)
Test output: Controls TEST 1 pin output
00 = 5 MHz clock (default)
01 = Coast output
10 = Clamp
11 = High impedance
PLL PD: PLL power-down
0 = Normal operation (default)
1 = PLL powered down
STRTB: PLL start-up circuit enable
0 = Disabled (default)
1 = Enabled
Input Mux Select 1
Subaddress
19h
7
Default (00h)
6
SOG Select [1:0]
5
4
Red Select [1:0]
3
2
Green Select [1:0]
1
0
Blue Select [1:0]
SOG Select [1:0]:
00 = CH1 selected (default)
01 = CH2 selected
10 = CH3 selected
11 = Reserved
Red Select [1:0]:
00 = CH1 selected (default)
01 = CH2 selected
10 = CH3 selected
11 = Reserved
Green Select [1:0]:
00 = CH1 selected (default)
01 = CH2 selected
10 = CH3 selected
11 = CH4 selected
Blue Select [1:0]:
00 = CH1 selected (default)
01 = CH2 selected
10 = CH3 selected
11 = Reserved
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Input Mux Select 2
Subaddress
1Ah
7
Default (00h)
6
5
1
4
3
Reserved
2
1
0
VSYNC Select
Reserved
HSYNC Select
Bit 7: It must be written to 1.
VSYNC Select:
0 = VSYNC_A selected (default)
1 = VSYNC_B selected
HSYNC Select [1:0]:
0 = HSYNC_A selected (default)
1 = HSYNC_B selected
Blue and Green Coarse Gain
Subaddress
1Bh
7
Default (55h)
6
5
4
3
2
Green Gain [3:0]
1
0
Blue Gain [3:0]
Green Coarse Gain [3:0]: Coarse analog gain for Green channel applied before the ADC.
Gain [3:0] Description
0000 = 0.5
0001 = 0.6
0010 = 0.7
0011 = 0.8
0100 = 0.9
0101 = 1.0
0110 = 1.1
0111 = 1.2
1000 = 1.3
Maximum recommended gain for 700mVp-p input.
1001 = 1.4
1010 = 1.5
1011 = 1.6
1100 = 1.7
1101 = 1.8
1110 = 1.9
1111 = 2.0
Blue Coarse Gain [3:0]: Coarse gain for Blue channel
Red Coarse Gain
Subaddress
7
1Ch
Default (05h)
6
5
4
3
Reserved
Red Coarse Gain [3:0]: Coarse analog gain for Red channel applied before the ADC.
26
2
1
Red Gain [3:0]
0
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
Fine Offset LSB
Subaddress
1Dh
7
Default (00h)
6
5
Reserved
4
3
Red Offset [1:0]
2
1
Green Offset [1:0]
0
Blue Offset [1:0]
Red Offset [1:0] : Offset LSB for red channel. This is LSB of register 0x0D
Green Offset [1:0] : Offset LSB for green channel. This is LSB of register 0x0C
Blue Offset [1:0] : Offset LSB for blue channel. This is LSB of register 0x0B
Blue Coarse Offset
Subaddress
1Eh
7
Default (20h)
6
5
4
3
Reserved
2
1
0
Blue offset [5:0]
Blue Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC.
1Fh = +31 LSB (Recommended for optimum ALC performance)
00h = 0 LSB
20h = -1 LSB (default)
3Fh = -32 LSB
Green Coarse Offset
Subaddress
1Fh
7
Default (20h)
6
5
4
Reserved
3
2
1
0
Coarse Green offset [5:0]
Green Coarse offset [5:0]: Coarse analog offset for green channel applied before the ADC.
1Fh = +31 LSB (Recommended for optimum ALC performance)
Red Coarse Offset
Subaddress
20h
7
Default (20h)
6
5
4
Reserved
3
2
1
0
Coarse Red offset [5:0]
Red Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC.
1Fh = +31 LSB (Recommended for optimum ALC performance)
HSOUT Output Start
Subaddress
7
21h
Default (09h)
6
5
4
3
2
1
0
HSOUT Start [7:0]
HSOUT Start [7:0]: HSYNC output Start pixel number.
27
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
MISC Control
Subaddress
22h
7
Default (00h)
6
5
4
Reserved
3
2
1
0
MAC_EN
Reserved
VS_ALIGN
Reserved
MAC_EN:
0 = Macrovision compatibility disabled (default)
1 = Macrovision compatibility enabled
VS_ALIGN
0 = VSOUT alignment relative to HSOUT varies with SyncSep Threshold
1 = VSOUT alignment not affected by SyncSep Threshold
Automatic Level Control Enable
Subaddress
7
26h
Default (00h)
6
5
ALC enable
ALC enable: Automatic level control enable
0 = Disabled (default)
1 = Enabled
28
4
3
Reserved
2
1
0
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
Automatic Level Control Filter
Subaddress
28h
7
Default (00h)
6
Reserved
5
4
3
2
NSV[3:0]
1
0
NSH [2:0]
The horizonal ALC coefficient (NSH) specifies the number of the horizonal samples (N) used to calculate the average blank level per
horizonal line. Offset error correction is applied immediately based on the vertical (NSV) coefficient.
The vertical coefficient (NSV) specifies the amount of offset error correction (derived from NSH) that is applied to each line update.
NSV [3:0]: ALC vertical filter coefficient
NSV [3:0]
Description
0000 =
1 (default)
0001 =
1/2
0010 =
1/4
0011 =
1/8
0100 =
1/16
0101 =
1/32
0110 =
1/64
0111 =
1/128
1000 =
1/256
1001 =
1/512
1010 =
1/1024
1011 =
1/2048
1100 =
1/4096
1101 =
1/8192
1110 =
1/16384
1111 =
1/32768
Maximum error correction applied per line update
Minimum error correction applied per line update
NSH [2:0]: ALC horizontal sample filter coefficient
NSH [2:0]
Description
000 =
1 (default)
001 =
1/2
010 =
1/4
011 =
1/8
100 =
1/16
101 =
1/32
110 =
1/64
111 =
1/128
Minimum number of pixels used in horizonal filter
Maximum number of pixels used in horizonal filter
29
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
Fine Clamp Control
Subaddress
2Ah
Default (00h)
7
6
5
4
Reserved
3
Fine swsel[1:0]
2
1
0
Fine B
Fine G
Fine R
Fine swsel: Fine clamp time constant adjustment
00 = Highest (default)
01 =
10 =
11 = Lowest
Fine B:
0 = Blue channel fine clamp is off (default)
1 = Blue channel fine clamp is on
Fine G:
0 = Green channel fine clamp is off (default)
1 = Green channel fine clamp is on
Fine R:
0 = Red channel fine clamp is off (default)
1 = Red channel fine clamp is on
Power Control
Subaddress
7
2Bh
(Default 00h)
6
5
4
3
2
1
0
SOG
SLICER
REF
CURRENT
PW ADC B
PW ADC G
PW ADC R
SOG:
0 = Normal operation (default)
1 = SOG power-down
Slicer:
0 = Normal operation (default)
1 = Slicer power-down
Reference:
0 = Normal operation (default)
1 = Reference block power-down
Current control:
0 = Normal operation (default)
1 = Current control block power-down
PW ADC B: Power-down ADC blue channel
0 = PW ADC R: Power-down ADC red channel
1 = ADC channel 1 power-down
PW ADC G: Power-down ADC green channel
0 = PW ADC R: Power-down ADC red channel
1 = ADC channel 2 power-down
PW ADC R: Power-down ADC red channel
0 = PW ADC R: Power-down ADC red channel
1 = ADC channel 3 power-down
30
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
ADC Setup
Subaddress
2Ch
(Default 00h)
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
50h = Recommended setting
Coarse Clamp Control
Subaddress
2Dh
7
Default (00h)
6
5
CCCLP_cur_CH1
4
3
Reserved
2
1
0
Coarse B
Coarse G
Coarse R
Coarse clamp charge current switch selection:
00 = Highest (default)
01 =
10 =
11 = Lowest
Course B:
0 = Coarse clamp off at BLUE channel (default)
1 = Coarse clamp on at BLUE channel
Coarse G :
0 = Coarse clamp off at GREEN channel (default)
1 = Coarse clamp on at GREEN channel
Coarse R :
0 = Coarse clamp off at RED channel (default)
1 = Coarse clamp on at RED channel
SOG Clamp
Subaddress
2Eh
7
(Default 00h)
6
5
4
SOG_CE
3
2
1
0
Reserved
SOG_CE:
0 = SOG Clamp disabled (default)
1 = SOG Clamp enabled. Set to 1 for SOG operation.
ALC Placement
Subaddress
31h
7
(Default 00h)
6
5
4
3
2
1
0
ALC placement [7:0]
ALC placement [7:0]:
0 = Default
18h = PC graphics and SDTV with
bi-level syncs
5Ah = HDTV with tri-level syncs
Positions the ALC signal an integer number of clock periods after the HSYNC signal. ALC must be applied after the clamp end.
31
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
32
TVP7000
www.ti.com
SLES143 – SEPTEMBER 2005
APPLICATION INFORMATION
1.5 kΩ
4.7 nF
10 nF
GIN1
FILT1
G/Y
FILT2
SOG1
0.1 µF
PLL_F
0.1 µF
75 Ω
GOUT[9:0]
0.1 µF
B/Pb
BOUT[9:0]
BIN1
75 Ω
ROUT[9:0]
0.1 µF
R/Pr
DATACLK
RIN1
75 Ω
SOGOUT
HSYNC
HSYNC_A
VSOUT
VSYNC
VSYNC_A
HSOUT
TMS
CLAMP
I2C
SCL
SDA
+3.3 V
PWDN
COAST
RESETB
2.2 kΩ x 2
2.2 kΩ x 3
Figure 8. TVP7000 Application Example
Schematic
33
1
2
3
A3.3V
4
5
6
A1.8V
I2C ADDRESS SELECTION
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF 0.1uF
0.1uF
2-3: Base Addr 0xBA
0.1uF
1-2: Base Addr 0xB8 - Default
D
1.5k
D3.3V
D1.8V
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10k
0.1uF
FILT1
FILT2
PLL_F
3
0.1uF
D
D3.3V
PLLA1.8V
I2CA
2
1
JMP3
VSYNC_A
VSYNC_B
10k
HSYNC_A
HSYNC_B
PLL_F
FILT2
FILT1
0.1uF
EXT_CLK
TP
GIN_4
10nF
0.1uF
1
GIN_3
A3.3V
PLLA1.8V
10nF
GIN_2
0.1uF
D1.8V D3.3V
2.2k (2)
D3.3V
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A3.3V
A1.8V
2.2k (2)
GIN_2
SOGIN_2
GIN_3
SOGIN_3
GIN_4
A33GND
A33VDD
A33VDD
A33GND
NSUB
PLL_A18GND
PLL_F
FILT2
FILT1
PLL_A18GND
PLL_A18VDD
PLL_A18VDD
PLL_A18GND
HSYNC_B
HSYNC_A
EXT_CLK
VSYNC_B
VSYNC_A
COAST
CLAMP
U1
C
10nF
0.1uF
RIN_3
0.1uF
RIN_2
0.1uF
RIN_1
0.1uF
BIN_3
0.1uF
BIN_2
0.1uF
BIN_1
0.1uF
TVP7000
SDA
SCL
I2CA
TMS
RESETB
PWDN
DVDD
GND
IOGND
IOVDD
R_0
R_1
R_2
R_3
R_4
IOGND
R_5
R_6
R_7
R_8
R_9
IOGND
IOVDD
G_0
G_1
C
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SDA
SCL
I2CA
RESETB
PWDN
R[9..0]
49.9
R[9..0]
49.9
G[9..0]
G[9..0]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PwrPad
1
TP
TEST
SOGIN_1
GIN_1
A18GND
A18VDD
A18GND
A18VDD
A18VDD
A18GND
RIN_3
RIN_2
RIN_1
A33GND
A33VDD
A33VDD
A33GND
BIN_3
BIN_2
BIN_1
A18VDD
A18GND
NSUB
TEST
VSOUT
HSOUT
SOGOUT
IOVDD
IOGND
DATACLK
B_9
B_8
B_7
B_6
B_5
B_4
B_3
B_2
B_1
B_0
DVDD
GND
IOVDD
IOGND
G_9
G_8
G_7
G_6
G_5
G_4
G_3
G_2
GIN_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
B
B
49.9
B[9..0]
B[9..0]
49.9
DCLK
SOGOUT
HSOUT
VSOUT
49.9 (3)
A
A
Title
TVP7000
Size
Number
Revision
REV 1.1
C
Date:
File:
1
2
3
4
5
31-Aug-2005
Sheet of
C:\Documents and Settings\a0214685.ENT\Desktop\TVP7000_EVM_MODULE_REV1.0.ddb
Drawn By:
6
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
TVP7000PZP
NRND
HTQFP
PZP
100
TVP7000PZPR
NRND
HTQFP
PZP
100
90
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TVP7000
TBD
Call TI
Call TI
0 to 70
TVP7000
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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