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UC1525A, UC1527A, UC2525A
UC2527A, UC3525A, UC3527A
SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
UCx52xA Regulating Pulse Width Modulators
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The UC1525A/1527A series of pulse width modulator
integrated circuits are designed to offer improved
performance and lowered external parts count when
used in designing all types of switching power
supplies. The on-chip 5.1-V reference is trimmed to
1% and the input common-mode range of the error
amplifier includes the reference voltage, eliminating
external resistors. A sync input to the oscillator allows
multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between CT and the discharge terminals
provides a wide range of dead-time adjustment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circuitry
and the output stages, providing instantaneous turn
off through the PWM latch with pulsed shutdown, as
well as soft-start recycle with longer shutdown
commands.
1
8-V to 35-V Operation
5.1-V Reference Trimmed to 1%
100-Hz to 500-kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Dead-Time Control
Internal Soft Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout With Hysteresis
Latching PWM to Prevent Multiple Pulses
Dual Source and Sink Output Drivers
2 Applications
•
•
•
•
•
•
•
Off-Line and DC/DC Power Supplies
Converters Using Voltage Mode
Single-Ended or Two-Switch Topology Designs
Solar Inverters
Welding Inverters
Motor Control
Battery Chargers
OSC
VREF OUT
4
Reference
Regulator
+VIN 15
13
VC
11
OUTPUT A
14
OUTPUT B
13
VC
11
OUTPUT A
14
OUTPUT B
NOR
UVLO
Lockout
PART NUMBER
UCx52xA
Block Diagram
16
Device Information(1)
PACKAGE
BODY SIZE (NOM)
LCCC (20)
8.89 mm × 8.89 mm
CDIP (16)
19.56 mm × 6.67 mm
SOIC (16)
10.30 mm × 7.50 mm
PDIP (16)
19.30 mm × 6.35 mm
PLCC (20)
8.96 mm × 8.96 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
GROUND 12
To Internal
Circutry
SYNC 3
RT
6
CT
5
Flip
Flop
OSC
NOR
DISCHARGE 7
UC1525A
Output Stage
S
PWM
Latch
COMPENSATION 9
INV INPUT
1
NI INPUT
2
SOFTSTART
8
Error
Amp
R
VREF
OR
S
50 µA
OR
3 kŸ
SHUTDOWN 10
5 kŸ
UC1527A
Output Stage
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1525A, UC1527A, UC2525A
UC2527A, UC3525A, UC3527A
SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision C (January 2008) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added Thermal Information table ........................................................................................................................................... 5
•
Changed RθJA values in the Thermal Information table: from 80-120 to N/A for J; from 90 to 47.6 for N; from 45-90 to
72.6 for DW; from 43-75 to 55.8 for FN; and from 70-80 to N/A for FK ................................................................................ 5
•
Changed RθJC values in the Thermal Information table: from 28 to 37.4 (top) and 10.1 (bottom) for J; from 45 to 37.3
(top) for N; from 25 to 34 (top) for DW; from 34 to 33.7 (top) for FN; and from 20 to 32.9 (top) to 3.5 (bottom) for FK ...... 5
2
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
5 Pin Configuration and Functions
J and N Package
16-Pin CDIP and PDIP
Top View
SYNC
3
14
Output B
OSC Output
4
13
VC
CT
5
12
Ground
10
8
9
17
VC
Shutdown
NC
6
16
NC
Compensation
CT
7
15
Ground
RT
8
14
Output A
9 10 11 12 13
18
Shutdown
7
Soft Start
Output A
5
Discharge
Discharge
Output B
OSC Output
NC
11
1 20 19
4
Compensation
6
2
SYNC
Soft Start
RT
3
VREF
+VIN
+VIN
VREF
15
NC
16
2
NI Input
1
NI Input
INV Input
INV Input
FN and FK Packages
20-Pin PLCC or LCCC
Top View
Pin Functions
PIN
CDIP,
PDIP
PLCC,
LCCC
I/O
INV Input
1
2
I
Inverting input to the error amplifier
NI Input
2
3
I
Noninverting input to the error amplifier
SYNC
3
4
I
Oscillator sync terminal
OSC Output
4
5
O
Oscillator frequency output
CT
5
7
I
Timing capacitor connection pin for oscillator frequency programming. The
timing capacitor should be connected to the device ground using minimal trace
length.
RT
6
8
I
Timing resistor connection pin for oscillator frequency programming
Discharge
7
9
I
A single resistor between CT and the discharge terminals provides dead-time
adjustment
Soft Start
8
10
I
Soft-start input pin.
Compensati
on
9
12
O
Output of the error amplifier for compensation
Shutdown
10
13
I
Pull this pin high to shut down PWM output
Output A
11
14
O
output A of the on-chip drive stage
Ground
12
15
—
Ground return pin
VC
13
17
—
Power supply pin for the output stage. This pin should be bypassed with a
0.1-µF monolithic ceramic low ESL capacitor with minimal trace lengths.
Output B
14
18
O
Output B of the on-chip drive stage.
+VIN
15
19
—
Input voltage
VREF
16
20
O
5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF
monolithic ceramic low ESL capacitor and minimal trace length to the ground
plane.
NC
—
1, 6, 11, 16
—
No internal connection
NAME
Copyright © 1997–2017, Texas Instruments Incorporated
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
+VIN
Supply voltage
VC
Collector supply voltage
V
40
V
–0.3
5.5
V
Analog inputs
–0.3
+VIN
V
Output current, source or sink
500
mA
Reference output current
50
mA
Oscillator charging current
5
mA
Power dissipation at TA = +25°C(2)
1000
mW
Power dissipation at TC = +25°C(2)
2000
mW
150
°C
300
°C
150
°C
–55
Lead temperature (soldering, 10 seconds)
(1)
UNIT
40
Logic inputs
Operating junction temperature
Tstg
MAX
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
+VIN
Input voltage
VC
Collector supply voltage
MAX
8
35
UNIT
V
4.5
35
V
Sink/source load current (steady state)
0
100
mA
Sink/source load current (peak)
0
400
mA
mA
Reference load current
0
20
100
400
Hz
2
150
kΩ
0.001
0.01
µF
0
500
Ω
UC1525A, UC1527A
–55
125
UC2525A, UC2527A
–25
85
UC3525A, UC3527A
0
70
Oscillator frequency range
Oscillator timing resistor
Oscillator timing capacitor
Dead time resistor range
Operating ambient temperature
4
MIN
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°C
Copyright © 1997–2017, Texas Instruments Incorporated
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UC2527A, UC3525A, UC3527A
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
6.4 Thermal Information
UCx52xA
THERMAL METRIC
(1)
FK
(LCCC)
J
(CDIP)
DW
(SOIC)
N
(PDIP)
FN
(PLCC)
20 PINS
16 PINS
16 PINS
16 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
N/A
N/A
72.6
47.6
55.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.9
37.4
34
37.3
33.7
°C/W
RθJB
Junction-to-board thermal resistance
32.1
54.2
37.3
27.7
21.1
°C/W
ψJT
Junction-to-top characterization parameter
N/A
N/A
8.9
17.3
9.7
°C/W
ψJB
Junction-to-board characterization parameter
N/A
N/A
36.8
27.5
20.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
10.1
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UC152xA,
UC252xA
5.05
5.1
5.15
UC352xA
5
5.1
5.2
UNIT
REFERENCE
Output voltage
TJ = 25°C
V
Line regulation
VIN = 8 V to 35 V
10
20
mV
Load regulation
IL = 0 mA to 20 mA
20
50
mV
Temperature stability (1)
Over operating
20
50
mV
Total output variation (1)
Line, load, and temperature
Shorter circuit current
Output noise Voltage
(1)
Long-term stability (1)
UC152xA,
UC252xA
5
5.2
UC352xA
4.95
5.25
V
VREF = 0, TJ = 25°C
80
100
mA
10 Hz ≤ 10 kHz, TJ = 25°C
40
200 µVrms
TJ = 125°C
20
50
mV
OSCILLATOR SECTION (2)
Initial accuracy (1) (2)
TJ = 25°C
2%
6%
UC152xA,
UC252xA
0.3%
1%
UC352xA
1%
2%
Voltage stability (1) (2)
VIN = 8 V to 35 V
Temperature stability (1)
Over operating
Minimum frequency
RT = 200 kΩ, CT = 0.1 mF
Maximum frequency
RT = 2 kΩ, CT = 470 pF
400
Current mirror
IRT = 2 mA
1.7
2
3
3.5
0.3
1.2
Clock amplitude (1) (2)
Clock width (1) (2)
TJ = 25°C
Syncronization threshold (1) (2)
Sync input current
3%
6%
120
Sync voltage = 3.5 V
Hz
kHz
2.2
mA
0.5
1
µs
2
2.8
V
1
2.5
mA
0.5
5
mV
2
10
V
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
UC152xA, UC252xA
Input offset voltage
(1)
(2)
UC352xA
These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Tested at fOSC = 40 kHz (RT = 3.6 kΩ, CT = 0.01 mF, RD = 0. Approximate oscillator frequency is defined by
f =
1
CT (0.7 RT + 3RD ) .
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Input bias current
TYP
MAX
1
10
Input offset current
1
RL ≥ 10 MΩ
DC open loop gain
Gain-bandwidth product
(1)
AV = 0 dB, TJ = 25°C
DC transconductance (1) (3)
TJ = 25°C, 30 kΩ ≤ RL ≤ 1 MΩ
60
µA
75
dB
1
2
MHz
1.1
1.5
Low-level output voltage
0.2
High-level output voltage
UNIT
3.8
5.6
Common mode rejection
VCM = 1.5 V to 5.2 V
60
75
Supply voltage rejection
VIN = 8 V to 35 V
50
60
45%
49%
0.7
0.9
mS
0.5
V
dB
PWM COMPARATOR
Minimum duty-cycle
0%
Maximum duty-cycle
Zero duty-cycle
Input threshold (4)
Maximum duty-cycle
Input bias current (4)
V
3.3
3.6
0.05
1
µA
50
80
µA
0.4
0.7
0.8
1
SHUTDOWN
Soft-start current
VSD = 0 V, VSS = 0 V
Soft-start low level
VSD = 2.5 V
Shutdown threshold
To outputs, VSS = 5.1 V, TJ = 25°C
Shutdown input current
VSD = 2.5 V
0.4
1
mA
VSD = 2.5 V, TJ = 25°C
0.2
0.5
µS
0.2
0.4
1
2
Shutdown Delay
(5)
25
0.6
V
OUTPUT DRIVERS (EACH OUTPUT) (VC = 20 V)
ISINK = 20 mA
Low-level output voltage
ISINK = 100 mA
High-level output voltage
Undervoltage lockout
VC OFF current
ISOURCE = 20 mA
18
19
ISOURCE = 100 mA
17
18
6
7
VCOMP and VSS = High
(6)
VC = 35 V
V
V
8
V
200
µA
Rise time (5)
CL = 1 nF, TJ = 25°C
100
600
Fall time (5)
CL = 1 nF, TJ = 25°C
50
300
VIN = 35 V
14
20
ns
TOTAL STANDBY CURRENT
Supply current
(3)
(4)
(5)
(6)
6
mA
DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL where RL is the
resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum AV when the error amplifier output is
loaded.
Tested at fOSC = 40 kHz (RT = 3.6 kΩ, CT = 0.01 mF, RD = 0 Ω.
These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
200
100
500
10
400
Dead Time Resistance (:)
1
0.1
CT = 0.01 PF
CT = 0.05 PF
CT = 0.02 PF
CT = 0.1 PF
CT = 5 nF
CT = 2 nF
CT = 1 nF
0.01
0.001
0.0002
1P
10P
100P
1m
Charge Time (s)
10m
300
200
100
0
0.1
100m
1
D002
Figure 1. Oscillator Charge Time vs RT and CT
10
Charge Time (Ps)
Open-Loop Voltage Gain (dB)
100
400
300
200
100
-55 qC
25 qC
125 qC
0
2
4
6
8
10
Minimum Recommended (RT - k:)
12
D004
Figure 3. Maximum Value RD vs Minimum Value RT
Copyright © 1997–2017, Texas Instruments Incorporated
100 200
D003
Figure 2. Oscillator Discharge Time vs RT CT
500
Maximum Recommended RD
CT = 0.1 PF
CT = .05 PF
CT = .02 PF
CT = .01 PF
CT = 5 nF
CT = 2 nF
CT = 1 nF
800
Voltage Gain
RL = 30 k:
600
RL = 100 k:
RL = 300 k:
RL = 1 M:
400
RL = f
Voltage Phase
Phase
200
80
60
40
20
0
0
-20
10
Open-Loop Phase (q)
Timing Resistance (k:)
6.6 Typical Characteristics
-200
100
1k
10k
100k
Frequency (Hz)
1M
-400
10M
D005
Figure 4. Error Amplifier Voltage Gain and Phase vs
Frequency
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7 Detailed Description
7.1 Overview
The UCx52xA series of pulse width modulator integrated circuits are designed to offer improved performance
and lowered external parts count when used in designing all types of switching power supplies. The on-chip
5.1-V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference
voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single
unit to be synchronized to an external system clock. A single resistor between CT and the discharge terminals
provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an
external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output
stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start
recycle with longer shutdown commands.
These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start
capacitor discharged for subnormal input voltages. This lockout circuitry includes approximately 500 mV of
hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator.
Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period.
The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking
in excess of 200 mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The
UC1527A uses OR logic, which results in a HIGH output level when OFF.
7.2 Functional Block Diagram
OSC
VREF OUT
16
4
Reference
Regulator
+VIN 15
13
VC
11
OUTPUT A
14
OUTPUT B
13
VC
11
OUTPUT A
14
OUTPUT B
NOR
UVLO
Lockout
GROUND 12
To Internal
Circutry
SYNC 3
RT
6
CT
5
Flip
Flop
OSC
NOR
DISCHARGE 7
UC1525A
Output Stage
S
INV INPUT
1
NI INPUT
2
SOFTSTART
8
Error
Amp
R
PWM
Latch
COMPENSATION 9
VREF
OR
S
50 µA
OR
3 kŸ
SHUTDOWN 10
5 kŸ
UC1527A
Output Stage
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7.3 Feature Description
7.3.1 Adjustable Dead-Time Control
A single resistor between CT and the discharge terminals provides a wide range of dead-time adjustment.
7.3.2 Soft Start
Soft start is achieved by connecting the soft-start pin to ground through a capacitor, charged by the 50-µA
current source. See Functional Block Diagram.
7.3.3 Input Undervoltage Lockout With Hysteresis
The undervoltage lockout keeps the outputs off and the soft-start capacitor discharged for subnormal input
voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation.
7.3.4 Shutdown and Pulse-by-Pulse Current Limiting
See Shutdown Options (See Functional Block Diagram).
7.4 Device Functional Modes
This device has no functional modes.
7.4.1 Shutdown Options (See Functional Block Diagram)
Since both the compensation and soft-start terminals have current source pullups, either can readily accept a
pull-down signal which only has to sink a maximum of 100 A to turn off the outputs. This is subject to the added
requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of the shutdown pin which has been improved to
enhance the available shutdown options. Activating this circuit by applying a positive signal on the shutdown pin
performs two functions; the PWM latch is immediately set providing the fastest turn-off signal to the outputs; and
a 150-A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the
PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a
convenient implementation of pulse-by-pulse current limiting. Holding the shutdown pin high for a longer duration,
however, will ultimately discharge this external capacitor, recycling slow turnon upon release.
The shutdown pin should not be left floating as noise pickup could conceivably interrupt normal operation. All
transitions of the voltage on the shutdown pin should be within the time frame of one clock cycle and not
repeated at a frequency higher than 10 clock cycles.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved
performance and lowered external parts count when used in designing all types of switching power supplies. The
UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR
logic which results in a HIGH output level when OFF.
8.2 Typical Application
VREF
Reference
Regulator
16
Clock
0.1
0.1
4
3 kW
PWM
Adj.
+VIN
15
VC
13
Flip/
Flop
0.1
SYNC
10 kW
11
A
3
RT
Out A
Deadtime
3.6 kW
.009
Ramp
CT
6
1 k, 1 W
(2)
Oscillator
1.5 kW
7
.001
100 W
Comp
14
B
5
Out B
0.1
PWM
9
1 = VOS
2=I(+)
10 kW
0.1
GND
12
50 mA
3=I(−)
8
1
2
1
2
5 mF
1
+
3
3
1
1
2
2
3
3
5 kW
5 kW
E/A
−
V/I Meter
Soft-Start
+
5 kW
VREF
10
2
Shutdown
D.U.T.
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Lab Test Fixture
10
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UC2527A, UC3525A, UC3527A
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
Typical Application (continued)
8.2.1 Theory of Operation
+VSUPPLY
Q1
T1
C1
13
R1
+VC
A
T2
11
UC1525A
GND
B
30 W
14
Q2
C2
R2
12
Return
Figure 6. Low Power Transformers
Low power transformers can be driven by the UC1525A. Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
VREF 16
Q1
Q5 Q8
7.4 kW
RT
6
CT
5
Q3
Q6 Q9
2 kW
14 kW
Ramp To PWM
2 kW
SYNC
3
DISCHARGE
7
5 pF
Q10
Q11
25 kW
Q14
400 mA
Blanking To Outout
23 kW
Q4
Q2
Q7
1 kW
1 kW
Q12
Q13
GND 12
3 kW
250 kW
4
Clock
Figure 7. UC1525A Oscillator Schematic
Copyright © 1997–2017, Texas Instruments Incorporated
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Typical Application (continued)
+VIN
15
Q3
Q4
Q1
Inv Input
Q2
1
to PWM
Comparator
NI Input
2
200 mA
100 W
5.8 V
100 mA
Comp
9
Figure 8. UC1525A Error Amplifier
+VIN
13 +VC
Q7
Q5
Q9
Q4
5K
11
14
+VREF
5 kW
Clock
Q2
Q3
10 kW
10 kW
F/F
Output
Q8
Q6
Q1
Q10
Q11
Q6 Ommitted
In UC1527A
2 kW
PWM
Figure 9. UC1525A Output Circuit (1/2 circuit shown)
Q1
+VSUPPLY
To Output Filter
R1
R2
13
+VC
A
11
UC1525A
B
14
GND
12
Return
Figure 10. Grounded Driver Outputs For Single-Ended Supplies
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UC2527A, UC3525A, UC3527A
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
Typical Application (continued)
For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totempole source transistors on alternate oscillator cycles.
+15 V
13
Q1
+V C
A
T1
11
30 W
D1
UC1525A
Q2
B
14
GND
30 W
D2
12
D1, D2: UC3611
Return
Figure 11. Output Drivers With Low Source Impedance
The low source impedance of the output drivers provides rapid charging of power FET input capacitance while
minimizing external components.
+VSUPPLY
R1
C1
13
+VC
R2
A
Q1
11
T1
C2
UC1525A
R3
B
Q2
14
GND
12
Return
Figure 12. Conventional Push-Pull Bipolar Design
In conventional push-pull bipolar designs, forward base drive is controlled by R1–R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors C1 and C2.
8.2.2 Design Requirements
This example illustrates the design process and component selection for a push-pull DC-DC converter utilizing
the UC1525A. The converter regulates a 30-V input to a 5-V output with 10-A maximum load.
Table 1. Design Parameters
PARAMETER
MIN
TYP
30
UNIT
Input voltage range
VOUT
Output voltage
iOUT
Output current
fO
Oscillator frequency
100
kHz
fS
Switching frequency
50
kHz
Copyright © 1997–2017, Texas Instruments Incorporated
25
MAX
VIN
35
5
1
V
V
10
A
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
www.ti.com
8.2.3 Detailed Design Procedure
8.2.3.1 Timing Resistor and Capacitor Selection
Generally, higher switching frequency gives smaller size but have higher switching loss. Operation at 100 kHz
was selected in this example as a reasonable compromise between size and efficiency. The value of RT = 10 kΩ,
CT = 1.37 nF and RD = 100 Ω were chosen for 100-kHz oscillator frequency based on equation:
1
f
CT (0.7 R T 3 RD )
(1)
8.2.3.2 Turns Ratio Selection
The maximum primary-to-secondary turns ratio NMAX can be determined by the target output voltage, minimum
input voltage, and the estimated maximum duty cycle. DLIM = 0.35 was selected for this example. NMAX can be
calculated using Equation 1.
2 u DLIM u VIN(min) 2 u 0.35 u 25 V
NMAX
3.3
VOUT VF
5 V 0.3 V
(2)
Rounding NMAX down to the next lowest integer results in a turns ratio of N = 3.
8.2.3.3 Inductor Selection
The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load
current ripple is a good compromise between core loss and copper loss of the inductor. Higher ripple current
allows for a smaller inductor size, but places more burden on the output capacitor to smooth the ripple voltage on
the output. In this example, a ripple current of 25% of 10 A was chosen. The inductor value can be calculated as:
VOUT VF
1 N u (VOUT VF )
LO
u(
) 11.57 PH
'IL u fSW
2
2 u VIN(max)
(3)
8.2.3.4 Rectification Diode Selection
A rectification diode should always possess low-forward voltage drop. When used in high-frequency switching
applications, the diode must also possess a short recovery time. Schottky diodes meet both requirements and
are therefore strongly recommended in push-pull converter designs.
8.2.3.5 VC Capacitor Selection
The primary purpose of the VC capacitor is to supply the peak transient currents of the drivers as well as provide
stability for the VC regulator. These peak currents can be several amperes. The recommended value of VC
capacitor should be no smaller than 0.1 μF, and should be a good quality, low ESR, ceramic capacitor. VC
capacitor should be placed as close as possible to the VC pin to minimize potentially damaging voltage
transients caused by trace inductance.
8.2.3.6 Output Capacitor Selection
The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of
charge during load transient conditions.
8.2.3.7 Input Capacitor Selection
The input supply voltage typically has high source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. The input capacitor should be selected for RMS current rating and minimum ripple voltage.
14
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UC2527A, UC3525A, UC3527A
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
8.2.4 Application Curves
4
Saturation Voltage (V)
Sink = VOL
Source = VO - VOH
3
2
1
0
0.01
0.1
Output Current (Source or Sink)
1
D001
Figure 13. UC1525A Output Saturation Characteristics
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SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
www.ti.com
9 Power Supply Recommendations
The voltage range for VIN is 8 V to 35 V.
The voltage range for VC is 4.5 V to 35 V. Choose a voltage level which is suitable for the power switch, for
example, 12 V for MOSFET.
10 Layout
10.1 Layout Guidelines
High-speed circuits demand careful attention to layout and component placement. To assure proper performance
of the UC1525A follow these rules:
• Use a ground plane
• Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins
to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin will serve this
purpose.
• Bypass VIN, VC, and VREF. Use 0.1-µF monolithic ceramic capacitors with low equivalent series inductance.
Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane.
• Treat the timing capacitor, CT, like a bypass capacitor.
10.2 Layout Example
xx
xx
2
x
1 CVREF
2 RFB
1
x
1
CP
x
x
INV
Rz
x
x
Cz
x
1
NI
+VIN
x
SYNC
OUTB
1
x
CT
GND
x
x
RT
OUTA
x
DISCH
ARGE
SHUT
DOWN
SS
COMP
x
2
RT
1
RD
x
RB
x
VC
CT
Vin
1
UC1525A
CVC
OSC
xx
xx
xxxx
xx
xx
xxxx
2
x
1
2
VREF
2
x
CVIN
xx
xx
xx
xx
xx
xx
xx
xx
xxxx
xx
xx
xx
xx
xxxx
xx
xx
xxxx
FB
2
x
x
1
RA
OUTB
VC
OUTA
SHUTDOWN
1 CSS
x
Figure 14. UC1525A Layout Example
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UC2527A, UC3525A, UC3527A
www.ti.com
SLUS191D – FEBRUARY 1997 – REVISED JULY 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Switching Power Supply Topology Voltage Mode vs Current Mode (SLUA119)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UC1525A
Click here
Click here
Click here
Click here
Click here
UC1527A
Click here
Click here
Click here
Click here
Click here
UC2525A
Click here
Click here
Click here
Click here
Click here
UC2527A
Click here
Click here
Click here
Click here
Click here
UC3525A
Click here
Click here
Click here
Click here
Click here
UC3527A
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1997–2017, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-89511032A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596289511032A
UC1525AL/
883B
5962-8951103EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8951103EA
UC1525AJ/883B
Samples
5962-8951104EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8951104EA
UC1527AJ/883B
Samples
UC1525AJ
ACTIVE
CDIP
J
16
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1525AJ
Samples
UC1525AJ883B
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8951103EA
UC1525AJ/883B
Samples
UC1525AL
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1525AL
Samples
UC1525AL883B
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596289511032A
UC1525AL/
883B
UC1527AJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1527AJ
Samples
UC1527AJ883B
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8951104EA
UC1527AJ/883B
Samples
UC2525ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-25 to 85
UC2525ADW
Samples
UC2525ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-25 to 85
UC2525ADW
Samples
UC2525AJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-25 to 85
UC2525AJ
Samples
UC2525AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-25 to 85
UC2525AN
Samples
UC2525ANG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-25 to 85
UC2525AN
Samples
UC2525BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-25 to 85
UC2525BDW
Samples
UC2525BN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-25 to 85
UC2525BN
Samples
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UC2527AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2527AN
Samples
UC3525ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3525ADW
Samples
UC3525ADWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3525ADW
Samples
UC3525ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3525ADW
Samples
UC3525ADWTRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3525ADW
Samples
UC3525AJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
0 to 70
UC3525AJ
Samples
UC3525AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3525AN
Samples
UC3525ANG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3525AN
Samples
UC3527AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3527AN
Samples
UC3527ANG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3527AN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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