UC3843DR-8

UC284x, UC384x CURRENT-MODE PWM CONTROLLERS SLVS038D – JANUARY 1989 – REVISED JULY 1999 D D D D D D D D D D D D Optimized for Off-Line and dc-to-dc Converters Low Start-Up Current ( 5 kΩ: f [ R1.72C T T Figure 3. Oscillator Section POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 UC284x, UC384x CURRENT-MODE PWM CONTROLLERS SLVS038D – JANUARY 1989 – REVISED JULY 1999 APPLICATION INFORMATION TIMING RESISTANCE vs FREQUENCY DEAD TIME vs TIMING CAPACITANCE 100 100 CT = 10 nF VCC = 15 V RT ≥ 5 kΩ TA = 25°C 40 CT = 4.7 nF CT = 22 nF R T – Timing Resistance – kΩ Dead Time – µ s 40 10 4 1 CT = 1 nF CT = 22 nF 10 CT = 47 nF CT = 100 nF 4 0.4 VCC = 15 V TA = 25°C 1 100 0.1 0 4 10 40 100 1k 10 k 100 k 1M f - Frequency - Hz CT – Timing Capacitance – nF Figure 4 Figure 5 open-loop laboratory test fixture In the open-loop laboratory test fixture shown in Figure 6, high peak currents associated with loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to the GND terminal in a single-point ground. The transistor and 5-kΩ potentiometer sample the oscillator waveform and apply an adjustable ramp to the ISENSE terminal. REF RT A 4.7 kΩ VCC 2N2222 100 kΩ 1 kΩ Error Amplifier Adjust DUT VFB 5 kΩ REF COMP ISENSE 0.1 µF UC284x UC384x VCC OUTPUT 0.1 µF 1 kΩ, 1 W OUTPUT 4.7 kΩ ISENSE Adjust RT/CT GND GND CT Figure 6. Open-Loop Laboratory Test Fixture 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UC284x, UC384x CURRENT-MODE PWM CONTROLLERS SLVS038D – JANUARY 1989 – REVISED JULY 1999 APPLICATION INFORMATION shutdown technique The PWM controller (see Figure 7) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset. 1 kΩ REF COMP Shutdown 330 Ω ISENSE 500 Ω Shutdown To Current-Sense Resistor Figure 7. Shutdown Techniques A fraction of the oscillator ramp can be resistively summed with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 8). Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. REF 0.1 µF RT RT/CT CT R1 ISENSE R2 ISENSE C RSENSE Figure 8. Slope Compensation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  1999, Texas Instruments Incorporated