UCC21520, UCC21520A
SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021
UCC21520 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver
1 Features
3 Description
•
The UCC21520 and the UCC21520A are isolated
dual-channel gate drivers with 4-A source and 6-A
sink peak current. It is designed to drive power
MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz
with best-in-class propagation delay and pulse-width
distortion.
•
•
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
HEV and BEV battery chargers
Isolated converters in DC-DC and AC-DC power
supplies
Server, telecom, it and industrial infrastructures
Motor drive and DC-to-AC solar inverters
LED lighting
Inductive heating
Uninterruptible power supply (UPS)
The input side is isolated from the two output
drivers by a 5.7-kVRMS reinforced isolation barrier,
with a minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1500 VDC.
Every driver can be configured as two low-side
drivers, two high-side drivers, or a half-bridge driver
with programmable dead time (DT). A disable pin
shuts down both outputs simultaneously when it is set
high, and allows normal operation when left open or
grounded. As a fail-safe measure, primary-side logic
failures force both outputs low.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC21520DW
DW SOIC (16)
10.30 mm × 7.50 mm
UCC21520ADW
DW SOIC (16)
10.30 mm × 7.50 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VCCI 3,8
16 VDDA
Driver
INA
1
DIS
5
NC
7
DT
6
MOD
DEMOD
Reinforced Isolation
•
•
Universal: dual low-side, dual high-side or halfbridge driver
Operating temperature range –40 to +125°C
Switching parameters:
– 19-ns typical propagation delay
– 10-ns minimum pulse width
– 5-ns maximum delay matching
– 6-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater
than 100 V/ns
Surge immunity up to 12.8 kV
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range to interface with both
digital and analog controllers
Up to 25-V VDD output drive supply
– 5-V and 8-V VDD UVLO options
Programmable overlap and dead time
Rejects input pulses and noise transients shorter
than 5 ns
Fast disable for power sequencing
Industry standard wide body SOIC-16 (DW)
package
Safety-related certifications:
– 8000-VPK reinforced Isolation per DIN V VDE V
0884-11:2017-01
– 5.7-kVRMS isolation for 1 minute per UL 1577
– CSA certification per IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1 end
equipment standards
– CQC certification per GB4943.1-2011
Disable,
UVLO
and
Deadtime
UVLO
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
Driver
INB
2
GND
4
MOD
DEMOD
UVLO
10 OUTB
9
VSSB
Copyright © 2017, Texas Instruments Incorporated
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21520, UCC21520A
www.ti.com
SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Power Ratings.............................................................5
7.6 Insulation Specifications............................................. 5
7.7 Safety-Related Certifications...................................... 6
7.8 Safety-Limiting Values................................................ 6
7.9 Electrical Characteristics.............................................7
7.10 Switching Characteristics..........................................8
7.11 Insulation Characteristics Curves..............................9
7.12 Typical Characteristics............................................ 10
8 Parameter Measurement Information.......................... 14
8.1 Propagation Delay and Pulse Width Distortion......... 14
8.2 Rising and Falling Time.............................................14
8.3 Input and Disable Response Time............................ 14
8.4 Programable Dead Time........................................... 15
8.5 Power-up UVLO Delay to OUTPUT..........................15
8.6 CMTI Testing.............................................................16
9 Detailed Description......................................................17
9.1 Overview................................................................... 17
9.2 Functional Block Diagram......................................... 17
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................21
10 Application and Implementation................................ 22
10.1 Application Information........................................... 22
10.2 Typical Application.................................................. 23
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Example...................................................... 36
13 Device and Documentation Support..........................38
13.1 Third-Party Products Disclaimer............................. 38
13.2 Documentation Support.......................................... 38
13.3 Certifications........................................................... 38
13.4 Receiving Notification of Documentation Updates..38
13.5 Support Resources................................................. 38
13.6 Trademarks............................................................. 38
13.7 Electrostatic Discharge Caution..............................38
13.8 Glossary..................................................................38
14 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2020) to Revision E (December 2021)
Page
• Updated Features .............................................................................................................................................. 1
• Changed tPWD in Switching Characteristics ....................................................................................................... 8
Changes from Revision C (December 2019) to Revision D (March 2020)
Page
• Added cross reference to table note1 ................................................................................................................4
• Added VDDx power-up delay typ and max values ............................................................................................ 8
• Changed DT pin configuration recommendations ........................................................................................... 21
• Added update to bootstrap circuit recommendations....................................................................................... 24
• Added update to gate resistor selection recommendations .............................................................................25
• Added gate to source resistor recommendation .............................................................................................. 26
• Added update to Cboot selection recommendations ....................................................................................... 28
2
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SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021
5 Description (continued)
Each device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the
driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under
voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21520 and the UCC21520A enable high efficiency, high power
density, and robustness in a wide variety of power applications.
6 Pin Configuration and Functions
INA
1
16
VDDA
INB
2
15
OUTA
VCCI
3
14
VSSA
GND
4
13
NC
DISABLE
5
12
NC
DT
6
11
VDDB
NC
7
10
OUTB
VCCI
8
9
VSSB
Not to scale
Figure 6-1. DW Package 16-Pin SOIC Top View
Table 6-1. Pin Functions
PIN
NAME
DISABLE
NO.
5
TYPE(1)
DESCRIPTION
I
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when
connecting to a micro controller with distance.
DT
6
I
Programmable dead time function.
Tying DT to VCCI allows the outputs to overlap. Placing a 500-Ω to 500-kΩ resistor (RDT)
between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is
recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with RDT
to achieve better noise immunity. It is not recommended to leave DT floating.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC
7
–
No Internal connection.
NC
12
–
No internal connection.
NC
13
–
No internal connection.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL
capacitor located as close to the device as possible.
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Table 6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P = Power, G = Ground, I = Input, O = Output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.3
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.3
30
V
OUTA to VSSA, OUTB to VSSB
–0.3
VVDDA+0.3,
VVDDB+0.3
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.3,
VVDDB+0.3
V
–0.3
VVCCI+0.3
V
–5
VVCCI +0.3
V
1500
V
–40
150
°C
–65
150
°C
Output signal voltage
INA, INB, DIS, DT to GND
Input signal voltage
INA, INB Transient for 50 ns
Channel to channel voltage
Junction temperature, TJ
VSSA-VSSB, VSSB-VSSA
(2)
Storage temperature, Tstg
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
To maintain the recommended operating conditions for TJ, see the Section 7.4.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
4
MIN
MAX
UNIT
3
18
V
VCCI
VCCI Input supply voltage
VDDA,
VDDB
Driver output bias supply
UCC21520ADW – 5-V UVLO version
6.5
25
V
VDDA,
VDDB
Driver output bias supply
UCC21520DW – 8-V UVLO version
9.2
25
V
TA
Ambient Temperature
–40
125
°C
TJ
Junction Temperature
–40
130
°C
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SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021
7.4 Thermal Information
UCC21520,
UCC21520A
THERMAL METRIC(1)
UNIT
DW-16 (SOIC)
RθJA
Junction-to-ambient thermal resistance
67.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.4
°C/W
RθJB
Junction-to-board thermal resistance
32.1
°C/W
ψJT
Junction-to-top characterization parameter
18.0
°C/W
ψJB
Junction-to-board characterization parameter
31.6
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Application
Report.
7.5 Power Ratings
PD
Power dissipation by UCC21520 or UCC21520A
PDI
Power dissipation by transmitter side of
UCC21520 or UCC21520A
PDA, PDB
Power dissipation by each driver side of
UCC21520 or UCC21520A
VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3
V, 3 MHz 50% duty cycle square wave 1-nF
load
VALUE
UNIT
1.05
W
0.05
W
0.5
W
7.6 Insulation Specifications
PARAMETER
clearance(1)
TEST CONDITIONS
VALUE
UNIT
CLR
External
Shortest pin-to-pin distance through air
>8
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 10.5 µm)
>21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage(3)
qpd
Apparent charge(4)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (see Figure 7-1)
1500
VRMS
DC voltage
2121
VDC
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s
Ω
109
Pollution degree
2
Climatic category
40/125/21
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
7.7 Safety-Related Certifications
VDE
CSA
Certified according to DIN V VDE V
0884-11:2017-01,
Certified according to IEC 60950-1, IEC
and DIN EN 60950-1 (VDE 0805 Teil 62368-1, IEC 61010-1 and IEC 60601-1
1):2014-08
UL
CQC
Recognized under
UL 1577 Component
Recognition Program
Certified according to GB
4943.1-2011
Reinforced Insulation Maximum
Transient Isolation voltage, 8000
VPK;
Maximum Repetitive Peak Isolation
Voltage, 2121 VPK;
Maximum Surge Isolation Voltage,
8000 VPK
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC 60950-1 2nd
Ed.+A1+A2, 800 VRMS maximum working
voltage (pollution degree 2, material group I)
Reinforced insulation per CSA 62368-1-14
and IEC 62368-1 2nd Ed., 800 VRMS
maximum working voltage (pollution degree
Single protection, 5700
2, material group I);
VRMS
Basic insulation per CSA 61010-1-12+A1
and IEC 61010-1 3rd Ed., 600 VRMS
maximum working voltage (pollution degree
2, material group III);
2 MOPP (Means of Patient Protection) per
CSA 60601- 1:14 and IEC 60601-1 Ed.3+A1,
250 VRMS maximum working voltage
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate 660 VRMS
maximum working voltage
Certification number: 40040142
Master contract number : 220991
Certificate number:
CQC16001155011
File number: E181974
7.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
6
Safety output supply
current
TEST CONDITIONS
SIDE
MIN
TYP
MAX
UNIT
RθJA = 67.3°C/W, VDDA/B = 12 V, TA =
25°C, TJ = 150°C
See Figure 7-2.
DRIVER A,
DRIVER B
75
mA
RθJA = 67.3°C/W, VDDA/B = 25 V, TA =
25°C, TJ = 150°C
See Figure 7-2.
DRIVER A,
DRIVER B
36
mA
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7.8 Safety-Limiting Values (continued)
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
PS
Safety supply power
TS
Safety temperature(1)
(1)
TEST CONDITIONS
RθJA = 67.3°C/W, TA = 25°C, TJ = 150°C
See Figure 7-3.
SIDE
MIN
TYP
MAX
INPUT
50
DRIVER A
900
DRIVER B
900
TOTAL
1850
150
UNIT
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 7.4 table is that of a device installed on a high-K test board for leaded
surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS , where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI , where VI is the maximum input voltage.
7.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI operating current
(f = 500 kHz) current per channel,
COUT = 100 pF
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
(f = 500 kHz) current per channel,
COUT = 100 pF
2.5
mA
VCCI UVLO THRESHOLDS
VVCCI_ON
Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
Falling threshold VCCI_OFF
2.35
2.5
2.65
V
VVCCI_HYS
Threshold hysteresis
0.2
V
UCC21520ADW VDD UVLO THRESHOLDS (5-V UVLO Version)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
5.7
6.0
6.3
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
5.4
5.7
6
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.3
V
UCC21520DW VDD UVLO THRESHOLDS (8-V UVLO Version)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
8.3
8.7
9.2
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
7.8
8.2
8.7
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.5
V
INA, INB AND DISABLE
VINAH, VINBH,
VDISH
Input high voltage
1.6
1.8
2
V
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7.9 Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VINAL, VINBL,
VDISL
Input low voltage
VINA_HYS,
VINB_HYS,
VDIS_HYS
Input hysteresis
VINA, VINB
Negative transient, ref to GND, 50 ns Not production tested, bench test
pulse
only
MIN
TYP
MAX
0.8
1
1.2
0.8
UNIT
V
V
–5
V
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pull-up
performance. See tRISE in Section
7.10 and Section 9.3.4 for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 12 V, IOUT = –10
mA, TA = 25°C
11.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 12 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
Pull DT pin to VCCI
Overlap determined by INA INB
DT pin is left open, min spec
characterized only, tested for
outliers
Dead time
RDT = 20 kΩ
0
160
-
8
15
ns
200
240
ns
7.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
6
16
ns
7
12
ns
20
ns
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
14
19
30
ns
tPDLH
Propagation delay from INx to OUTx
rising edges
14
19
30
ns
tPWD
Pulse width distortion |tPDLH – tPDHL|
6
ns
tDM
Propagation delays matching
between VOUTA, VOUTB
5
ns
100
us
Output off for less than minimum,
COUT = 0 pF
f = 100 kHz
tVDD+ to OUT VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB. See
INA or INB tied to VCCI
Figure 8-6
8
MIN
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SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
|CMH|
High-level common-mode transient
immunity
INA and INB both are tied to VCCI;
VCM=1500V; (See Section 8.6)
100
|CML|
Low-level common-mode transient
immunity
INA and INB both are tied to GND;
VCM=1500V; (See Section 8.6)
100
TYP
MAX
UNIT
V/ns
7.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (
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