UCC21530
SLUSDC0C – OCTOBER 2018 – REVISED NOVEMBER 2021
UCC21530 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver
with 3.3-mm Channel-to-Channel Spacing
1 Features
3 Description
•
The UCC21530 is an isolated dual-channel gate
driver with 4-A source and 6-A sink peak current. It
is designed to drive IGBTs, Si MOSFETs, and SiC
MOSFETs up to 5-MHz with best-in-class propagation
delay and pulse-width distortion.
•
•
•
•
•
•
•
•
•
•
•
•
•
Universal: dual low-side, dual high-side or halfbridge driver
Wide body SOIC-14 (DWK) package
3.3-mm spacing between driver channels
Switching parameters:
– 19-ns typical propagation delay
– 10-ns minimum pulse width
– 5-ns maximum delay matching
– 6-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater
than 100-V/ns
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range
Up to 25-V VDD output drive supply
Programmable overlap and dead time
Rejects input pulses and noise transients shorter
than 5 ns
Operating temperature range –40 to +125°C
Safety-related certifications:
– 8000-VPK isolation per DIN V VDE V
0884-11 :2017-01
– 5.7-kVRMS isolation for 1 minute per UL 1577
– CSA certification per IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1 end
equipment standards
– CQC certification per GB4943.1-2011
2 Applications
•
•
•
•
•
Solar string and central inverters
AC-to-DC and DC-to-DC charging piles
AC inverter and servo drive
AC-to-DC and DC-to-DC power delivery
Energy storage systems
The input side is isolated from the two output
drivers by a 5.7-kVRMS reinforced isolation barrier,
with a minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1850 V.
This device can be configured as two low-side drivers,
two high-side drivers, or a half-bridge driver with
programmable dead time (DT). The EN pin pulled low
shuts down both outputs simultaneously and allows
for normal operation when left open or pulled high. As
a fail-safe measure, primary-side logic failures force
both outputs low.
The device accepts VDD supply voltages up to 25 V.
A wide input VCCI range from 3 V to 18 V makes
the driver suitable for interfacing with both analog and
digital controllers. All the supply voltage pins have
under voltage lock-out (UVLO) protection.
Device Information(1)
PART NUMBER
UCC21530
(1)
PACKAGE
DWK SOIC (14)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21530
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety-Limiting Values................................................ 7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics..........................................9
6.11 Insulation Characteristics Curves............................10
6.12 Typical Characteristics............................................ 11
7 Parameter Measurement Information.......................... 16
7.1 Propagation Delay and Pulse Width Distortion......... 16
7.2 Rising and Falling Time.............................................16
7.3 Input and Enable Response Time.............................16
7.4 Programable Dead Time........................................... 17
7.5 Power-Up UVLO Delay to OUTPUT......................... 17
7.6 CMTI Testing.............................................................18
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................23
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
10 Power Supply Recommendations..............................36
11 Layout........................................................................... 37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................40
12.1 Documentation Support.......................................... 40
12.2 Receiving Notification of Documentation Updates..40
12.3 Support Resources................................................. 40
12.4 Trademarks............................................................. 40
12.5 Electrostatic Discharge Caution..............................40
12.6 Glossary..................................................................40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2019) to Revision C (November 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed maximum pulse-width distortion value in Features section from "5 ns" to "6 ns"................................ 1
• Changed maximum pulse width distortion specification in Section 6.10 from "5 ns" to "6 ns"............................9
Changes from Revision A (March 2019) to Revision B (December 2019)
Page
• Added VDE certification, CSA master contract, and CQC certificate numbers to Safety-Related Certifications
table ................................................................................................................................................................... 7
2
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5 Pin Configuration and Functions
Figure 5-1. DWK Package, 14-Pin SOIC (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
DT pin configuration:
•
Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
DT
6
I
•
Placing a resistor (RDT) between DT and GND adjusts dead time according to the equation:
DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a ceramic capacitor, 2.2
nF or greater, close to DT pin to achieve better noise immunity.
EN
5
I
Enable both driver outputs if asserted high, disable the output if set low. It is recommended to tie
this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF low ESR/ESL
capacitor close to EN pin when connecting to a micro controller with distance.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity.
NC
7
–
No internal connection. This pin can be left floating, tied to VCCI, or tied to GND.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as
close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor
located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor
located as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.5
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.5
30
V
OUTA to VSSA, OUTB to VSSB
–0.5
VVDDA+0.5,
VVDDB+0.5
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.5,
VVDDB+0.5
V
–0.5
VVCCI+0.5
V
–2
VVCCI+0.5
V
Output signal voltage
INA, INB, EN, DT to GND
Input signal voltage
INA, INB Transient for 200ns
Channel to channel internal isolation voltage
1850
V
Junction temperature, TJ (2)
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
|VSSA-VSSB|
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
To maintain the recommended operating conditions for TJ, see the Section 6.4.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
VCCI
4
MIN
MAX
3
18
V
8-V UVLO version UCC21530B-Q1
9.2
25
V
12-V UVLO version UCC21530-Q1
14.7
25
V
VCCI Input supply voltage
UNIT
VDDAVSSA,
VDDBVSSB
Driver output bias supply refer to Vss
TA
Ambient Temperature
–40
125
°C
TJ
Junction Temperature
–40
130
°C
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6.4 Thermal Information
UCC21530
THERMAL METRIC(1)
DWK-14 (SOIC)
UNIT
RθJA
Junction-to-ambient thermal resistance
68.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.7
°C/W
RθJB
Junction-to-board thermal resistance
27.6
°C/W
ψJT
Junction-to-top characterization parameter
17.7
°C/W
ψJB
Junction-to-board characterization parameter
27
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PD
Power dissipation by UCC21530
PDI
Power dissipation by transmitter side of
UCC21530
PDA, PDB
Power dissipation by each driver side of
UCC21530
VCCI = 18 V, VDDA/B = 15 V, INA/B = 3.3 V,
3.9 MHz 50% duty cycle square wave 1-nF
load
VALUE
UNIT
1810
mW
50
mW
880
mW
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
clearance(1)
VALUE
UNIT
CLR
External
Shortest pin-to-pin distance through air
>8
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 10.5 µm)
>21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11):
2017-01(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage(3)
Apparent charge(4)
qpd
I
CIO
Barrier capacitance, input to
output(5)
RIO
Isolation resistance, input to
output(5)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 6-1)
1500
VRMS
DC voltage
2121
VDC
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s
pC
pF
Ω
109
Pollution degree
2
Climatic category
40/125/21
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
Certified according to
DIN V VDE V
0884-11:2017-01 and
DIN EN 60950-1 (VDE
0805 Tiel 1):2014-08
CSA
UL
Certified according to IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1
CQC
Recognized under UL
1577 Component Recognition Certified according to GB 4943.1-2011
Program
Reinforced Insulation
Maximum Transient
Isolation voltage,
8000 VPK; Maximum
Repetitive Peak Isolation
Voltage, 2121 VPK;
Maximum Surge
Isolation Voltage, 8000
VPK
Reinforced insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd
Ed.+A1+A2, 800 VRMS maximum
working voltage (pollution degree 2,
material group I) Reinforced insulation
per CSA 62368-1-14 and IEC 62368-1
2nd Ed., 800 VRMS maximum working
voltage (pollution degree 2, material
group I); Basic insulation per CSA
61010-1-12+A1 and IEC 61010-1 3rd
Ed., 600 VRMS maximum working
voltage (pollution degree 2, material
group III); 2 MOPP (Means of Patient
Protection) per CSA 60601- 1:14 and
IEC 60601-1 Ed.3+A1, 250 VRMS
maximum working voltage
Single protection, 5700 VRMS
Reinforced Insulation, Altitude ≤ 5000
m, Tropical Climate 660 VRMS
maximum working voltage
Certification number:
40040142
Master contract number: 220991
File number: E181974
Certificate number: CQC16001155011
6.8 Safety-Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety output supply
current
PS
Safety supply power
TS
Safety temperature(1)
(1)
TEST CONDITIONS
SIDE
MIN
TYP
MAX
UNIT
RθJA = 68.3°C/W, VDDA/B = 15 V, TA =
25°C, TJ = 150°C
See Figure 6-2
DRIVER A,
DRIVER B
58
mA
RθJA = 68.3°C/W, VDDA/B = 25 V, TA =
25°C, TJ = 150°C
See Figure 6-2
DRIVER A,
DRIVER B
35
mA
RθJA = 68.3°C/W, TA = 25°C, TJ = 150°C
See Figure 6-3
INPUT
50
DRIVER A
880
DRIVER B
880
TOTAL
1810
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 6.4 table is that of a device installed on a high-K test board for leaded
surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS , where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI , where VI is the maximum input voltage.
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6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI per operating current
(f = 500 kHz) current per channel
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 15 V
3.0
mA
VCCI TO GND UNDERVOLTAGE THRESHOLDS
VVCCI_ON
UVLO Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
UVLO Falling threshold
2.35
2.5
2.65
V
VVCCI_HYS
UVLO Threshold hysteresis
0.2
V
UCC21530B-Q1 VDD to VSS UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
8
8.5
9
V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
7.5
8
8.5
V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
0.5
V
UCC21530-Q1 VDD TO VSS UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
12.5
13.5
14.5
V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
11.5
12.5
13.5
V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
1.0
V
INA and INB
VINAH, VINBH
Input high threshold voltage
1.6
1.8
2
V
VINAL, VINBL
Input low threshold voltage
0.8
1
1.2
V
VINA_HYS,
VINB_HYS
Input threshold hysteresis
VINA, VINB
Negative transient, ref to GND, 50 ns Not production tested, bench test
pulse
only
0.8
V
–5
V
EN THRESHOLDS
8
VENH
Enable high voltage
VENL
Enable low voltage
2.0
V
0.8
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VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pull-up
performance. See tRISE in Section
6.10 and Section 8.3.4 for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 15 V, IOUT = –10
mA, TA = 25°C
14.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 15 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
DT pin tied to VCCI
Dead time
RDT = 20 kΩ
Overlap determined by INA INB
160
200
-
240
ns
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
16
ns
7
12
ns
20
ns
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
14
19
30
ns
tPDLH
Propagation delay from INx to OUTx
rising edges
14
19
30
ns
tPWD
Pulse width distortion |tPDLH – tPDHL|
6
ns
tDM
Propagation delays matching
between VOUTA, VOUTB
5
ns
tVCCI+ to OUT VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See Figure 7-5
Output off for less than minimum,
COUT = 0 pF
f = 100 kHz
40
INA or INB tied to VCCI
tVDD+ to OUT VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
INA or INB tied to VCCI
See Figure 7-6
50
|CMH|
High-level common-mode transient
immunity (See Section 7.6)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM = 1500 V;
100
|CML|
Low-level common-mode transient
immunity (See Section 7.6)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM = 1500 V;
100
µs
V/ns
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6.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (
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