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UCC21530-Q1
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver
with 3.3-mm Channel-to-Channel Spacing
1 Features
3 Description
•
The UCC21530-Q1 is an isolated dual-channel gate
driver with 4-A source and 6-A sink peak current. It is
designed to drive IGBTs and SiC MOSFETs up to 5MHz with best-in-class propagation delay and pulsewidth distortion.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Universal: Dual Low-Side, Dual High-Side or HalfBridge Driver
Wide Body SOIC-14 (DWK) Package
3.3mm spacing between driver channels
Switching Parameters:
– 19-ns Typical Propagation Delay
– 10-ns Minimum Pulse Width
– 5-ns Maximum Delay Matching
– 6-ns Maximum Pulse-Width Distortion
Common-Mode Transient Immunity (CMTI)
Greater than 100-V/ns
Surge Immunity up to 12.8-kVPK
Isolation Barrier Life >40 Years
4-A Peak Source, 6-A Peak Sink Output
TTL and CMOS Compatible Inputs
3-V to 18-V Input VCCI Range
Up to 25-V VDD Output Drive Supply
Programmable Overlap and Dead Time
Rejects Input Pulses and Noise Transients
Shorter than 5 ns
Operating Temperature Range –40 to +125°C
Safety-Related Certifications:
– 8000-VPK Isolation per DIN V VDE V 0884-11
:2017-01 (Planned)
– 5.7-kVRMS Isolation for 1 Minute per UL 1577
– CSA Certification per IEC 60950-1, IEC 623681, IEC 61010-1 and IEC 60601-1 End
Equipment Standards (Planned)
– CQC Certification per GB4943.1-2011
(Planned)
AEC-Q100 Qualified With:
– Device Temperature Grade 1
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
The input side is isolated from the two output drivers
by a 5.7-kVRMS reinforced isolation barrier, with a
minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1850 V.
This driver can be configured as two low-side drivers,
two high-side drivers, or a half-bridge driver with
programmable dead time (DT). The EN pin pulled low
shuts down both outputs simultaneously and allows
for normal operation when left open or pulled high. As
a fail-safe measure, primary-side logic failures force
both outputs low.
The device accepts VDD supply voltages up to 25 V.
A wide input VCCI range from 3 V to 18 V makes the
driver suitable for interfacing with both analog and
digital controllers. All the supply voltage pins have
under voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21530-Q1
enables high efficiency, high power density, and
robustness in a wide variety of power applications.
Device Information(1)
PART NUMBER
UCC21530-Q1
PACKAGE
DWK SOIC (14)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
2 Applications
•
•
•
•
•
•
HEV and BEV Battery Chargers
Solar String and Central Inverters
AC-to-DC and DC-to-DC Charging Piles
AC Inverter and Servo Drive
AC-to-DC and DC-to-DC Power Delivery
Energy Storage Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21530-Q1
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
7.6 CMTI Testing........................................................... 17
1
1
1
2
3
4
8
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety-Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
Propagation Delay and Pulse Width Distortion.......
Rising and Falling Time .........................................
Input and Enable Response Time...........................
Programable Dead Time ........................................
Power-Up UVLO Delay to OUTPUT .......................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information ................ 15
7.1
7.2
7.3
7.4
7.5
Detailed Description ............................................ 18
15
15
15
16
16
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
13.1 Package Option Addendum .................................. 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2019
C
Initial Release
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SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
5 Pin Configuration and Functions
DWK Package
14-Pin SOIC
Top View
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
DT
6
I
DT pin configuration:
•
Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
•
Placing a resistor (RDT) between DT and GND adjusts dead time according to the
equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a
ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity.
EN
5
I
Enable both driver outputs if asserted high, disable the output if set low. It is recommended
to tie this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF
low ESR/ESL capacitor close to EN pin when connecting to a micro controller with distance.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC
7
–
No internal connection.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor
located as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P =Power, I= Input, O= Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.5
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.5
30
V
OUTA to VSSA, OUTB to VSSB
–0.5
VVDDA+0.5,
VVDDB+0.5
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.5,
VVDDB+0.5
V
–0.5
VVCCI+0.5
V
–2
VVCCI+0.5
V
Output signal voltage
INA, INB, EN, DT to GND
Input signal voltage
INA, INB Transient for 200ns
Channel to channel internal isolation voltage
Junction temperature, TJ
|VSSA-VSSB|
(2)
Storage temperature, Tstg
(1)
(2)
1850
V
–40
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3
18
V
Driver output bias supply refer to Vss
14.7
25
V
TA
Ambient Temperature
–40
125
°C
TJ
Junction Temperature
–40
130
°C
VCCI
VCCI Input supply voltage
VDDAVSSA,
VDDBVSSB
4
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6.4 Thermal Information
UCC21530-Q1
THERMAL METRIC (1)
DWK-14 (SOIC)
UNIT
RθJA
Junction-to-ambient thermal resistance
68.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.7
°C/W
RθJB
Junction-to-board thermal resistance
27.6
°C/W
ψJT
Junction-to-top characterization parameter
17.7
°C/W
ψJB
Junction-to-board characterization parameter
27
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PD
Power dissipation by UCC21530-Q1
PDI
Power dissipation by transmitter side of
UCC21530-Q1
PDA, PDB
Power dissipation by each driver side of
UCC21530-Q1
VCCI = 18 V, VDDA/B = 15 V, INA/B = 3.3 V,
3.9 MHz 50% duty cycle square wave 1-nF
load
VALUE
UNIT
1810
mW
50
mW
880
mW
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6.6 Insulation Specifications
VALUE
UNIT
CLR
PARAMETER
External clearance (1)
Shortest pin-to-pin distance through air
TEST CONDITIONS
>8
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 10.5 µm)
>21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage (3)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 1)
1500
VRMS
DC voltage
2121
VDC
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;
109
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
Plan to certify according
to DIN V VDE V 088411:2017-01 and DIN EN
60950-1 (VDE 0805 Tiel
1):2014-08
UL
Plan to certify according to IEC 60950-1,
IEC 62368-1, IEC 61010-1 and IEC
60601-1
CQC
Recognized under UL 1577
Component Recognition
Program
Plan to certify according to GB
4943.1-2011
Single protection, 5700 VRMS
Certification number:
TBD
Master contract number: TBD
File number: E181974
Certificate number: TBD
6.8 Safety-Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
RθJA = 68.3ºC/W, VDDA/B = 15 V, TA =
25°C, TJ = 150°C
IS
Safety output supply
current
Safety supply power
TS
Safety temperature (1)
(1)
MIN
TYP
MAX
UNIT
DRIVER A,
DRIVER B
58
mA
DRIVER A,
DRIVER B
35
mA
INPUT
50
RθJA = 68.3ºC/W, TA = 25°C, TJ = 150°C
DRIVER A
880
See Figure 3
DRIVER B
880
TOTAL
1810
See Figure 2
RθJA = 68.3ºC/W, VDDA/B = 25 V, TA =
25°C, TJ = 150°C
See Figure 2
PS
SIDE
150
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI per operating current
(f = 500 kHz) current per channel
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 15 V
3.0
mA
VCCI TO GND UNDERVOLTAGE THRESHOLDS
VVCCI_ON
UVLO Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
UVLO Falling threshold
2.35
2.5
2.65
V
VVCCI_HYS
UVLO Threshold hysteresis
0.2
V
VDD TO VSS UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
12.5
13.5
14.5
V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
11.5
12.5
13.5
V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
1.0
V
INA and INB
VINAH, VINBH
Input high threshold voltage
1.6
1.8
2
V
VINAL, VINBL
Input low threshold voltage
0.8
1
1.2
V
VINA_HYS,
VINB_HYS
Input threshold hysteresis
VINA, VINB
Negative transient, ref to GND, 50
ns pulse
0.8
Not production tested, bench test
only
V
–5
V
EN THRESHOLDS
VENH
Enable high voltage
VENL
Enable low voltage
8
2.0
V
0.8
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pullup performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 15 V, IOUT = –10
mA, TA = 25°C
14.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 15 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
DT pin tied to VCCI
Dead time
RDT = 20 kΩ
Overlap determined by INA INB
160
200
-
240
ns
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
16
ns
7
12
ns
20
ns
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
14
19
30
ns
tPDLH
Propagation delay from INx to OUTx
rising edges
14
19
30
ns
tPWD
Pulse width distortion |tPDLH – tPDHL|
6
ns
tDM
Propagation delays matching
between VOUTA, VOUTB
f = 100 kHz
5
ns
tVCCI+ to
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See Figure 31
INA or INB tied to VCCI
OUT
tVDD+ to
Output off for less than minimum,
COUT = 0 pF
40
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
INA or INB tied to VCCI
See Figure 32
|CMH|
High-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1500 V;
100
|CML|
Low-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1500 V;
100
µs
50
V/ns
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6.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (
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