UCC24650DBVR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents UCC24650 SLUSBL6 – FEBRUARY 2015 UCC24650 200-V Wake-Up Monitor for Fast Transient PSR 1 Features 3 Description • The UCC24650 is an easy-to-use secondary-side voltage monitor that periodically measures its own VDD voltage. A relative droop of 3% from the previous reading triggers a wake-up alert signal to a receiving primary-side regulation (PSR) controller. Its low-power consumption helps achieve tPCD(min) tDM < tPCD(min) PCD VOUT (ripple) 0.97VS&H A. Not to scale Figure 11. Timing Diagram of Internal PCD Signal 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 UCC24650 www.ti.com SLUSBL6 – FEBRUARY 2015 Feature Description (continued) VNOM VOUT 0.97 VNOM IOUT IWAKE Wake-up pulse generated by sinking current out of VSEC VSEC VAUX Wake-up signal detected by primary controller; switching initiated A. Not to scale Figure 12. Simplified Timing Diagram of System Behavior 7.3.3 Sample, Hold, and Transient Detector The sample-and-hold function (S&H) monitors the VDD voltage, samples that voltage during a PCD pulse, and holds the buffered sample constant during the interval between power cycles. The held sample is scaled to about 97% of the external voltage to serve as a –3% droop-detection threshold reference voltage. The external VDD voltage is continually compared to the internal droop reference by the transient detection comparator, and a wake-up signal is triggered if VDD falls below the droop-reference voltage. The S&H droop-reference voltage is refreshed at the end of each power cycle detected by the PCD function, to track minor changes in output voltage. The droop-reference voltage is held accurately for PCD intervals less than tSW(max), but may drift either higher or lower during longer intervals. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 11 UCC24650 SLUSBL6 – FEBRUARY 2015 www.ti.com Feature Description (continued) 7.3.4 Wake Pulse Generator and WAKE Switch The WAKE pin not only functions as a PCD input as described in PCD, but also serves as an output driver to accomplish the wake-up function. An integrated N-channel MOSFET switch is connected between WAKE and GND and is driven by the WAKE-pulse oscillator when the conditions for wake-up are met (see Functional Block Diagram). Each wake-up pulse is of short duration to limit internal dissipation and is repeated periodically until a PSR-driven power cycle is detected or until VDD has fallen to the UVLO turn-off threshold. Figure 13 shows two possible typical system responses. The solid lines indicate the successful wake-up of a compatible PSR controller from the sleeping or Wait state between low-frequency power cycles. After a load step causes the output voltage (at VDD) to cross the previously stored reference voltage, the WAKE output drives a current pulse to the PSR controller which responds with multiple power cycles to restore regulation. At each power cycle, the reference voltage is refreshed and further WAKE pulses are suppressed. In the case where the PSR controller does not respond to the first wake-up pulse, the dotted lines indicate that the wake-up pulses are repeated, the reference voltage is not refreshed, and the output voltage continues to fall. IWAKE VOUT (ripple) 0.97VS&H (Dotted lines indicate waveforms if primary-side controller does not respond to wake-up signal.) Figure 13. System Response to Wake-Up Signal After Load-Transient Event In the event that a power cycle occurs during the droop before VOUT has reached the WAKE threshold, the S&H reference is updated to the VOUT voltage at that moment. This may extend the droop by another 3% before the WAKE threshold is reached and the condition for a wake-up signal is met, effectively delaying the wake-up as illustrated by Figure 14 and Figure 15. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 UCC24650 www.ti.com SLUSBL6 – FEBRUARY 2015 Feature Description (continued) VNOM VOUT 0.97 VNOM WAKE Threshold Power-cycle at low frequency generated by PSR IOUT IWAKE PCD Figure 14. Simplified Typical System Response to Wake-Up Signal After Load-Transient Event VNOM VOUT Previous Threshold Power-cycles at low frequency generated by PSR ~ 0.94 VNOM New Threshold IOUT IWAKE PCD Figure 15. Simplified Delayed System Response to Wake-Up Signal After Load-Transient Event The typical on-state resistance of the WAKE switch is approximately 150 Ω at 25°C and varies with junction temperature. Consequently, the wake-pulse current capability in low-voltage applications also varies with temperature (see Figure 7 in the Typical Characteristics). A built-in current limit prevents excess pulse current and power dissipation in higher-voltage applications. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 13 UCC24650 SLUSBL6 – FEBRUARY 2015 www.ti.com Feature Description (continued) In a typical isolated-flyback PSR topology, the wake-pulse current establishes a signal voltage across the system impedance, which consists mainly of the parallel combination of the primary magnetizing inductance, LM, and the switched-node capacitance, CSWN, scaled by the transformer turns-ratio. In applications with higher output voltages, some rectifier diodes may exhibit high forward voltage drop characteristics, along with possible additional voltage due to package inductance and stray inductance. This negative forward voltage is impressed on the WAKE input with respect to GND, as shown in Figure 16. VOUT NP ISEC NS IOUT RWAKE VSEC IWAKE UCC24650 5 WAKE VDD 1 3 ENS DS COUT GND 2 RPL LD LSTRAY (LD+STRAY × dISEC+/dt + VF(max)) VSEC dISEC+/dt ISEC VOUT 0 A, 0 V t 0A ±10 mA t (MAX) IWAKE Figure 16. High dISEC/dt may Generate Significant IWAKE. To avoid exceeding the maximum source-current rating for WAKE (see Absolute Maximum Ratings), a series resistance may be required to limit the WAKE current. Its value is calculated by Equation 1. However, this resistance presents additional impedance to the WAKE signal current that can be developed. Do not oversize RWAKE to avoid depressing the Wake-Up signal level at the PSR detection input. A trade-off between the level of reverse-current limiting and the WAKE signal drive level may be necessary. R WAKE t  VF(max)  LSUMdISEC / dt   0.7 V 10 mA where • • 14 VF(max) is the highest forward voltage drop expected. LSUM is the combined stray and package inductance. Submit Documentation Feedback (1) Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 UCC24650 www.ti.com SLUSBL6 – FEBRUARY 2015 Feature Description (continued) 7.3.5 PCD Counter and ENS Switch Some PSR applications may use an SR in place of the output diode rectifier to improve efficiency. For applications using the UCC24610 SR controller, the UCC24650 device provides the ENS output which can be used to enable the SR controller when the switching frequency is high, and disable it when the switching frequency is very low, to reduce standby power dissipation. Although the ENS function is specifically optimized for use with the UCC24610 device, it may also be used for other purposes provided the ENS pin is operated within its specified limits. The ENS output consists of an open-drain, N-channel MOSFET switch with on-resistance of approximately 2.7 kΩ at 25°C. A PCD counter (see Functional Block Diagram) monitors the time intervals between pulses and determines whether to turn on or off the ENS switch. At power-up, the ENS switch is off (high-impedance opendrain state) by default, and remains that way as long as the power-cycle period, tSW, is less than the disable qualifying interval, tDISS, to keep the SR controller enabled. After tSW > tDISS for a count of at least 63 consecutive power cycles, the ENS switch is turned on (low-impedance to GND) to disable the SR controller. This disablecount is reset to zero if any switching cycle period occurs where tSW < tDISS. This consecutive count requirement ensures that the switching frequency is consistently low enough to justify disabling the SR controller to minimize its bias power. There is considerable hysteresis in the qualifying interval timing, so the ENS switch remains on (SR or other secondary circuit is disabled) until tSW becomes less than the enable qualifying interval, tENS. In other words, the switching frequency is increasing. When tSW < tENS for 32 cumulative power cycles, the ENS switch is turned off and the SR controller is enabled. When ENS is in the Low state, the cumulative count allows any number of switching cycles with tSW > tENS without resetting the count. Figure 17 and Figure 18 show these ENS state transitions based on the switching period timing and interval count. VSEC tSW > tENS tSW < tENS for NENS ENS A. Not to scale Figure 17. Simplified Timing Diagram of ENS Behavior for Gradual Increase of Load Only 32 shorter tSW intervals are necessary to re-enable the SR controller to avoid excess rectifier dissipation as the system load increases. However, these shorter intervals (higher frequency) are not required to be consecutive, so that ENS is allowed to toggle High eventually, even if the switching frequency is not yet consistently higher. This method ensures that the SR or other circuitry is not prevented from re-enabling if the frequency is not consistent due to variable loads. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 15 UCC24650 SLUSBL6 – FEBRUARY 2015 www.ti.com Feature Description (continued) VSEC tSW < tDISS tSW > tDISS for NDISS ENS A. Not to scale Figure 18. Simplified Timing Diagram of ENS Behavior for Gradual Decrease of Load At least 63 consecutive counts of tSW > tDISS are necessary to disable the SR controller, to ensure that random deviations in tSW do not unnecessarily disrupt normal SR operation. In this manner, the ENS function is heavily skewed in favor of keeping the SR controller enabled, unless it is consistently operated at a very-low frequency, particularly during no-load operation. ENS is not affected in the case of a wake-up event, and the count is not changed. After a wake-up, the switching frequency generally increases quite rapidly, so the ENS switch is turned off to re-enable the SR controller as soon as the count of tSW < tENS reaches 32. Depending on the previous cumulative switching period history, the time to re-enable the SR controller may be anywhere between 32 switching cycles and immediate. 7.4 Device Functional Modes The UCC24650 operates as a voltage monitor in either of two modes: ENS output is High (driver is off), or ENS output is Low (driver is on). In either mode, when the monitor detects a 3% droop in the VDD voltage, it triggers a Wake-Up signal on the WAKE pin. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: UCC24650 UCC24650 www.ti.com SLUSBL6 – FEBRUARY 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The UCC24650 Wake-Up monitor is intended to be used with the UCC28730 PSR controller in off-line isolated DCM flyback converters. The UCC24650 signals the UCC28730 that the output voltage has drooped. This allows the PSR controller to react to a load increase even while operating at extremely-low switching frequencies. This pair of devices also operates at very-low bias currents to facilitate the achievement of