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UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016
UCC25710 LLC Half-Bridge Controller For Multi-String LED Lighting
1 Features
3 Description
•
•
•
The UCC25710 device is an LLC half-bridge
controller for accurate control of multi-string LED
backlight applications. It is optimized for multitransformer, multi-string LED architectures. Superior
LED current matching in multiple strings can be
achieved with this controller and architecture.
Compared to existing LED backlight solutions, the
multi-transformer architecture provides the highest
overall efficiency from AC input to LED load.
1
•
•
•
•
•
•
•
•
•
•
Closed-Loop LED String Current Control
PWM Dimming Input
Adjustable FMIN (3% accuracy), and FMAX (7.5%
Accuracy)
LLC and Series LED Switch Control for Dimming
Programmable Dimming LLC ON/OFF Ramp for
Elimination of Audible Noise
Closed-Loop Current Control at Low Dimming
Duty Cycles
Programmable Soft Start
Accurate VREF for Tight Output Regulation
Overvoltage, Undervoltage and Input Overcurrent
Protection With Auto-Restart Response
Second Overcurrent Threshold With Latch-Off
Response
400-mA/-800-mA Gate Drive Current
Low Start-Up and Operating Currents
Lead (Pb)-Free, 20-Pin, SOIC Package
2 Applications
•
•
LED Backlight for LCD TV and Monitors
LED General Lighting
SPACE
Simplified Application Diagram
The LLC controller function includes a Voltage
Controlled Oscillator (VCO) with programmable FMIN
and FMAX, half-bridge gate drivers with a fixed dead
time of 500 ns and a GM current amplifier. The LLC
power delivery is modulated by the controller’s VCO
frequency. The VCO has an accurate and
programmable frequency range. At very low power
levels the VCO frequency goes from FMAX to zero to
maximize efficiency at low LED currents.
Device Information(1)
PART NUMBER
UCC25710
PACKAGE
SOIC (20)
BODY SIZE (NOM)
12.80 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency and Linearity Results (Dual 45-W
Strings)
LED String 1
±
+
100
4
LED String 2
±
LED String N
TN
±
+
20 V to 9.5 V
UCC25710
1
ON/OFF
VCC
10 BLON
DTY
7
DADJ
8
2
GD1
FMIN 20
3
GD2
FMAX 19
4
GND
SS 18
13 CL
15 CREF
5
VREF
95
2
90
0
Linearity
85
-2
ICOMP 17
CS 16
LEDSW
6
14 DSR
OV 12
9
UV 11
DIM
Efficiency
+
Efficiency - %
T2
Linearity Error - %
T1
VIN
80
-4
0
10
100
Dimming Duty Cycle -%
DIM PWM Output
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2011) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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5 Description (continued)
The LED current loop reference is set by a divider off the VREF 5-V output. The reference can be varied over a
0.5-V to 2.6-V range, allowing analog dimming to be combined with PWM dimming.
PWM dimming is used to control an external LED series switch and also to gate on and off the LLC power stage.
The LEDSW output along with a simple drive circuit is used to switch on and off the LED string current. This
output responds directly to the input signal at the dimming input, DIM. The LLC is also ramped on and off with
the dimming PWM input. The on and off LLC dimming edges are ramped at programmable slew rates to control
audible noise. The dimming function includes duty-cycle compensation to allow optimization of overall efficiency
and dimming linearity over a maximum range.
The control voltage to the VCO is set by ICOMP (current amplifier output) during LED ON-times. During start-up
the soft-start pin, SS, controls the VCO response until it exceeds ICOMP. During dimming the rise and fall rates
of the VCO input are controlled by the voltage at the dimming slew rate, DSR, pin while the pedestal of VCO
control level continues to be controlled by ICOMP. The current amplifier output is connected to ICOMP only
during the commanded dimming LED ON-time. The LLC on-time is extended beyond the LED current ON-time at
low dimming duty-cycles to maintain closed-loop control of the LED current.
Protection thresholds for LED string overvoltage and undervoltage conditions are set with external resistive
dividers and accurate internal thresholds. Input current to the converter is monitored with both a restart and latchoff response depending on the overcurrent level. The controller also includes thermal shutdown protection.
The auto restart response to any fault includes a 10-ms reset period followed by a soft start. In the case of a
severe input overcurrent, restart is disabled until the input supply is cycled through its UVLO threshold.
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UCC25710
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6 Pin Configuration and Functions
DW Package
20-Pin SOIC
Top View
VCC
1
20
FMIN
GD1
2
19
FMAX
GD2
3
18
SS
GND
4
17
ICOMP
VREF
5
16
CS
LEDSW
6
15
CREF
DTY
7
14
DSR
DADJ
8
13
CL
DIM
9
12
OV
10
11
UV
BLON
Pin Functions
PIN
TYPE
DESCRIPTION
VCC
P
Connect a DC power voltage to VCC. Bypass VCC to GND with a 0.47-µF or larger ceramic
capacitor using short PC-board traces. VCC directly supplies power to the gate drivers and
VREF which biases all circuit blocks in the UCC25710. Undervoltage lockout (UVLO)
comparator prevents operation until VCC rises above VVCCON.
GD1&2
O
Gate drive outputs operate 180° out of phase with a fixed 500 ns of dead time. They typically
drive either primary end of a gate drive transformer. At start-up or during a fault recovery,
initiating the LLC converter begins with GD2 turning on first.
4
GND
P
The ground pin is both the reference pin for the controller and the low-side return for the gate
drive signals. Take special care to return all AC decoupling as close as possible to this pin
and avoid any common trace length with analog signal return paths.
5
VREF
O
The internal 5-V supply and reference rail is brought out to this pin. A small decoupling
capacitor to ground of 1 µF is required. VREF can support up to 10-mA current external to
the device. VREF is enabled when VCC is above VVCCON and BLON is above VBLON.
NO.
1
2, 3
NAME
6
LEDSW
O
The LED switch output is a control signal to a series LED switch. This output is low during a
low level at the DIM input and whenever the LLC converter is disabled. PWM dimming is
disabled during soft start, and the LEDSW output is high independent of the DIM input. A
simple gate drive circuit is generally required at this output to drive the external FET.
7
DTY
I/O
The duty-cycle pin is averaged with a capacitor to ground to form a 1-D proportional voltage
that is compared to the DADJ saw tooth voltage. The average voltage at this pin is 2.5 V(1D)+0.1 V, where D is the dimming PWM duty-cycle the DIM input.
I/O
A capacitor to ground at the duty-cycle adjust input sets the positive slope of a saw tooth
waveform that is compared to a voltage proportional to 1-D where D is the dimming PWM
duty-cycle of the DIM input. At the falling edge of the DIM input this comparison is used to
extend the LLC ON-time beyond the ON-time of the LED series switch.
8
DADJ
9
DIM
I
A PWM input signal at the dimming pin controls the average load current by cycling on and
off both an external series LED switch and the gate drives to the LLC converter. A high on
this pin corresponds to an ON condition. The controller ignores a low condition at this input
during start-up or fault recovery until after the completion of a soft-start sequence.
10
BLON
I
Backlight ON is an enable signal for the control device. The signal is active high with a
threshold of approx 1.2 V. The 5-V reference (VREF) is enabled with BLON which is the bias
supply for many of the internal blocks of the device.
4
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SLUSAD7B – APRIL 2011 – REVISED JULY 2016
Pin Functions (continued)
PIN
NO.
NAME
TYPE
DESCRIPTION
11
UV
I
This pin is used to monitor for an undervoltage condition on the load. A level below VUVTH on
this pin causes the converter to disable the gate drive outputs as well as the LEDSW output.
Immediately, a TRSTDLY (10 ms) reset delay and soft-start sequence is initiated. The reset
delay and soft-start sequence is repeated as long at the UV pin is low at the end of the
sequence.
12
OV
I
This pin is used to monitor for an overvoltage condition on an LED string. A level above
VOVTH on this pin causes the converter to disable the gate drive outputs as well as the
LEDSW output. If the OV input falls below its trip threshold the converter responds with a
TRSTDLY (10 ms) reset delay and soft start.
13
CL
I
Current limit input connects to a signal that represents the power converter’s input current.
Dual thresholds provide a shutdown retry or latch-off response.
14
DSR
I/O
The dimming slew rate pin is used to limit the rate of the VCO frequency change at the LLC
on or off edges of a dimming PWM cycle. A capacitor to ground at this pin programs the
maximum positive and negative slew rates that appear at the control input to the VCO.
Pulling this pin below about 0.8 V disables the GD outputs.
15
CREF
I
Current Reference is used to set the regulating voltage for the LED current feedback signal
at the CS input. This voltage input is set using a resistor divider from VREF. A nominal level
of around 0.7 V is recommended although a range of 0.6 V to 2.7 V is accommodated.
Internal reference levels of 0.5 V and 2.8 V replace the CREF input voltage at the current
amplifier when the CREF pin voltage is respectively below or above these levels. The 0.5-V
internal reference can be achieved by shorting CREF to ground, the internal 2.8-V reference
can be achieved by shorting CREF to VREF.
16
CS
I
Current sense input monitors the LED current. This signal is compared to VCREF by the
current amplifier to regulate the total LED current.
17
ICOMP
O
This output pin is used to compensate the current regulating loop. A capacitor, or capacitor
resistor series combination is typically used. During current regulation the voltage into the
VCO is slaved to this pin. Pulling this pin below about 0.8 V disables the GD outputs. During
PWM dimming OFF-time this pin is tri-stated and the compensation network is meant to hold
the proper LLC control voltage until the LLC converter is turned back on. To optimize this
operation any DC loading on this pin must be avoided.
18
SS
I/O
The soft-start pin is used to control the rate of change of the VCO frequency during start-up.
At start-up a low value pullup current source, ISS, is applied to this pin. A soft-start sequence
is initiated at start-up and during any fault recovery. The SS pin must charge to 4.2 V before
the controller allows PWM dimming to take place.
19
FMAX
I/O
The maximum frequency of the LLC converter is set by a resistor to ground at this pin. It is
actually the difference between the maximum and minimum frequency that is set by this
resistor.
20
FMIN
I/O
The minimum frequency of the LLC converter is set by a resistor to ground at this pin.
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SLUSAD7B – APRIL 2011 – REVISED JULY 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
20
V
Supply voltage
VCC
LEDSW output current
ILEDSW
±2
VREF output current
IVREF
–20
Gate drive RMS current continuous GD1, GD2
IGD1, IDG2
25
Gate drive voltage, GD1 GD2
VGD1, VGD2
–0.5
VCC + 0.5
Voltage
CS, CL, OV, UV, BLON,
DIM, CREF
–0.5
7
Lead temperature 1.60 mm (1/16 inch) from case for 10 s
V
260
Operating junction temperature, TJ
–55
150
Storage temperature, Tstg
–65
150
(1)
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
all voltages are with respect to GND; currents are positive into and negative out of the specified terminal. -40°C < TJ = TA <
125°C (unless otherwise noted)
MIN
VCC
Operating input voltage
CVCC
VCC bypass capacitor
0.47
Operating junction temperature
NOM
11
MAX
18
UNIT
V
µF
–40
125
°C
Switching frequency at gate drive outputs
25
350
kHz
VCREF
Input voltage (linear range)
0.6
VCREF
Input voltage (using internal clamps)
CVREF
VREF bypass capacitor
CSS
SS capacitor
10
250
CICOMP
ICOMP capacitor
0.5
47
CDTY
DTY capacitor
0.22
6.8
µF
CDSR
DSR capacitor
0
2500
pF
6
1.65
0
0.22
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2.7
VVREF
1
2.2
V
µF
nF
Copyright © 2011–2016, Texas Instruments Incorporated
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SLUSAD7B – APRIL 2011 – REVISED JULY 2016
7.4 Thermal Information
UCC25710
THERMAL METRIC (1)
DW (SOIC)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
79
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43
°C/W
RθJB
Junction-to-board thermal resistance
44
°C/W
ψJT
Junction-to-top characterization parameter
16
°C/W
ψJB
Junction-to-board characterization parameter
44
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY INPUT
VVCCMAX
VCC operating voltage
18
V
IOFF
Supply current, off
VVCC = 8 V
160
250
µA
ION
Supply current, on
Switching frequency = FMIN (30 KHz)
1.4
2.1
mA
IDISABLE
Supply current, disabled
VVCC = 12 V, VBLON = 0 V
240
350
ILATCHOFF
Supply current, latched off
Fault latch set
600
900
µA
UNDERVOLTAGE LOCKOUT
VVCCON
VCC turnon threshold
VVCC low-to-high
8.6
9.3
10.1
VVCCOFF
VCC turnoff threshold
VVCC high-to-low
8.3
9
9.6
VVCCHYS
Hysteresis
0.2
0.35
0.5
V
5-V REFERENCE OUTPUT
VVREF
5-V Reference
IVREF = 0 to 10 mA, TJ = 25°C
4.95
5
5.05
VVREF
5-V Reference
IVREF = 0 to 10 mA, TJ = –40°C to 125°C
4.85
5
5.15
–15
15
V
CURRENT AMPLIFIER
VICOMPIOS
Input offset voltage
VCREF = 1.65 V, ICOMP tied to CS
ICS
Input bias current at CS input
VCREF = 1.65 V, VCS = 1.65 V
–0.25
0.25
ICR
Input bias current at CREF
input
VCREF = 1.65 V, VCS = 1.65 V
–0.25
0.25
VICOMPHI
ICOMP high
VCS = 0 V, VCREF = 1.65 V, IICOMP = 50 µA
VICOMPLO
ICOMP low
VCS = 3 V, VCREF = 1.65 V, IICOMP = –50 µA
GMICOMP
ICOMP transconductance
ICOMP tied to CS, IICOMP = –100 µA to 100 µA
IICOMPSRC
Source current ICOMP
VCS = 0.65 V, VCREF = 1.65 V, VICOMP = 2.5 V
IICOMPSNK
Sink current ICOMP
IICOMPLGK
LED off leakage current at
ICOMP
VCREFCLO
CREF low Clamp
VCREF = 0 V, ICOMP tied to CS, regulating voltage
at ICOMP
0.475
0.5
0.535
VCREFCHI
CREF high Clamp
VCREF = 3 V, ICOMP tied to CS, regulating voltage
at ICOMP
2.65
2.8
2.95
4.6
4.85
0.35
0.65
440
510
600
120
150
180
VCS = 2.65 V, VCREF = 1.65 V, VICOMP = 2.5 V
195
245
295
VDIM = 0 V, VICOMP = 2.5 V, TJ = –40°C to 85°C
–0.1
Product Folder Links: UCC25710
µA
V
µs
µA
0.1
V
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mV
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Electrical Characteristics (continued)
TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
2.5
3
µA
3.4
5
kΩ
3.95
4.15
4.4
V
7
10
13
ms
SOFT START
ISS
Soft-start charging current
VSS = 2.25 V
RSSDC
Soft-start discharge
resistance
VSS = 1 V
VSSTH
Soft-start threshold
SS clamp released
TRSTDLY
Reset delay
From UVLO turnon to start of soft start
VOLTAGE CONTROLLED OSCILLATOR
FMIN
FMIN GD1, GD2
RMIN = 100 kΩ, VICOMP = 5 V
29.5
30.5
31.5
FMAX
FMAX GD1, GD2
RMIN = 100 kΩ, RMAX = 4.99 kΩ, VICOMP = 0.95 V
275
300
320
TDT
Dead-time GD1, GD2
RMIN = 100 kΩ, VICOMP = 3 V
400
500
600
TMATCH
ON-time mismatching
RMIN = 100 kΩ, VICOMP = 3 V
–50
VVCOTHLO
VICOMP VCO Threshold Low
Disable GD1, GD2, VICOMP high to low
0.8
0.9
0.95
VVCOMAX
VICOMP for FMIN
Frequency reaches FMIN
3.8
4
4.2
50
kHz
ns
V
GATE DRIVERS
VGDHI
GD1, GD2 VOUT high
IGD1, IGD2 = –20 mA, below VCC
1.8
3
V
RGDHSRES
GD1, GD2 ON-resistance
high
IGD1, IGD2 = –20 mA
14
30
Ω
VGDLO
GD1, GD2 VOUT low
IGD1, IGD2 = 20 mA
0.08
0.2
V
RGDLSRES
GD1, GD2 ON-resistance low IGD1, IGD2 = 20 mA
4
10
Ω
TGDRISE
GD1, GD2 output rise time
CGD = 1 nF, 1 V to 9 V
25
35
TGDFALL
GD1, GD2 output fall time
CGD = 1 nF, 9 V to 1 V
20
30
2.27
2.4
2.53
V
190
240
300
mV
0.25
µA
ns
UNDERVOLTAGE PROTECTION
VUVTH
Undervoltage threshold
VUVHY
Undervoltage threshold
hysteresis
IUV
UV input bias current
High-to-low on UV input
VUV = 2.7 V
–0.25
OVERVOLTAGE PROTECTION
VOVTH
Overvoltage threshold
VOVHY
Overvoltage threshold
hysteresis
IOV
OV input bias current
Low-to-high on OV input
VOV = 2.3 V
2.46
2.6
2.74
V
190
240
300
mV
0.25
µA
V
–0.25
CURRENT LIMIT PROTECTION
VCLTH
Current limit threshold
VCLHY
Current limit threshold
hysteresis
Low-to-high on CL input
VCLLTH
Current limit latching
threshold
Low-to-high on CL input
ICL
CL input bias current
VCL = 2.2 V
0.9
0.95
1
375
475
525
mV
1.75
1.9
2.05
V
0.25
µA
–0.25
THERMAL SHUTDOWN
tTSD
Junction temperature at
thermal shutdown
tHYS
Thermal hysteresis
Temperature rising
135
160
185
25
45
100
200
350
kΩ
0.8
1.2
1.6
V
°C
BACKLIGHT ON INPUT
RBLON
RBLON pulldown resistance
VBLON
Enable threshold
8
Pull down to GND
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Electrical Characteristics (continued)
TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM DIMMING
VDIM
Dimming input threshold
RDIM
DIM pullup resistance
Pullup resistance to VREF, VDIM = 0 V – 4.5 V
1.2
1.5
1.8
V
140
180
240
kΩ
VLEDSWHI
High-level at LEDSW output
ILEDSW = –100 µA, below VCC, VDIM = 3 V
0.4
1
VLEDSWLO
Low-level at LEDSW output
ILEDSW = 100 µA, VDIM = 0 V
0.2
0.5
RLEDSWHI
High-level output resistance
ILEDSW = –500 µA – 0 µA, VDIM = 3 V
4
6
RLEDSWLO
Low-level output resistance
ILEDSW = 500 µA – 0 µA, VDIM = 0 V
2
3
RDTY
DTY output resistance
VDTY = 0 V – 2.5 V , VDIM = 0 V
30
40
50
VDTYH
DTY max level
VDIM = 0 V
2.45
2.6
2.7
VDTYL
DTY min level
VDIM = 3 V
0.05
0.1
0.15
IDADJCH
DADJ charging current
VDADJ = 2.5 V, VDIM = 0 V
16
20
25
µA
RDADJDC
DADJ discharge resistance
VDADJ = 0.5 V, VDIM = 3 V
1
1.5
kΩ
TDADJ
DADJ delay
CADJ = 2.2 nF, VDTY = 2.6 V, delay from DIM highto-low to DSR discharge
225
275
330
µs
IDSRCH
DSR slew rate charge current VDSR = 2.5 V, VICOMP = 4 V, VDIM = 3 V
38
44
50
IDSRDC
DSR slew rate discharge
current
VDSR = 2.5 V, VICOMP = 4 V, VDIM = 0 V
38
44
50
VDSRCL
DSR clamp above ICOMP
VICOMP = 2 V, level above VICOMP
0.45
0.7
0.95
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kΩ
V
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V
9
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7.6 Typical Characteristics
9.5
1.6
9.4
VVCCON and VVCCOFF Threshold (V)
VCC Supply Current (mA)
1.4
Switching Frequency = FMIN
No Gate Drive Load
1.2
1.0
Turn On
0.8
0.6
Turn Off
0.4
Rising - V VCCON
9.3
9.2
9.1
9.0
8.9
Falling - VVCCOFF
8.8
8.7
0.2
8.6
0
8.5
0
2
4
6
8
10
12
14
16
18
-40
-20
0
20
40
60
80
100
120
140
VCC Supply Voltage (V)
Temperature (°C)
Figure 1. Supply Current vs Dimming Duty Cycle
Figure 2. VVCCON and VVCOFF Threshold vs Temperature
400
2.0
Switching Frequency = FMIN
No Gate Drive Load
IDISABLE and IOFF Supply Current (mA)
1.9
ION Supply Current (mA)
1.8
1.7
VVCC = 18 V
1.6
1.5
1.4
VVCC = 12 V
1.3
1.2
350
IDISABLE
VVCC = 12 V
VBLON = 0 V
300
250
200
IOFF
VVCC = 8 V
150
1.2
1.0
100
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
Figure 3. Supply Current vs Temperature
Figure 4. IDISABLE and IOFF Supply Current vs
Temperature
400
5.10
VCREF = 0 V
VCREF = 1 V
300
Output Current at ICOMP (mA)
VVREF Reference Voltage (V)
V CREF = 1.5 V
5.05
5.00
4.95
200
VCREF = 5.0 V
100
V CREF = 2.0 V
0
-100
Sinking Current
-200
4.90
-300
-40
10
Sourcing Current
-20
0
20
40
60
80
100
120
140
0
1.0
2.0
3.0
4.0
5.0
Temperature (°C)
Input Voltage at CS(V)
Figure 5. Reference Voltage vs Temperature
Figure 6. Output Current (ICOMP) vs Input Voltage (CS)
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Typical Characteristics (continued)
31.5
4%
31.3
3%
31.1
FMIN Switching Frequency (kHz)
2%
1%
0
-1%
-2%
-3%
30.7
30.5
30.3
30.1
29.9
-4%
29.7
-5%
29.5
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
100
120
140
Temperature (°C)
Figure 7. GMICOMP vs Temperature
Figure 8. Minimum Switching Frequency vs Temperature
600
580
TDT Gate Drive Dead Time (ns)
315
310
305
300
295
290
560
540
520
500
480
460
440
285
420
280
400
-40
-20
0
20
40
60
80
100
120
140
-40
-20
Temperature (°C)
0
20
40
60
12
120
12
140
1.8
CLOAD = 4.7 nF
RLOAD = 2.5 kW
CLOAD = 4.7 nF
RLOAD = 2.5 kW
10
10
1.2
TA = 25oC
6
0.9
4
0.6
TA = 125oC
2
0
100
200
Gate Drive Voltage (V)
8
Gate Drive Source Current (A)
1.5
0
100
Figure 10. Gate Drive Dead Time vs Temperature
1.8
-100
80
Temperature (°C)
Figure 9. Maximum Switching Frequency vs Temperature
Gate Drive Voltage (V)
80
Temperature (°C)
320
FMAX Switching Frequency (kHz)
30.9
1.5
8
1.2
TA = 25oC
6
0.9
4
0.3
2
0
0
300
0.3
0
-100
Time (ns)
0.6
TA = 125oC
Gate Drive Sinking Current (A)
GMICOMP Change From Value at 25oC (%)
5%
0
100
200
300
Time (ns)
Figure 11. Gate Driver Outputs (Rising Edge) vs Time
Figure 12. Gate Driver Outputs (Falling Edge) vs Time
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Typical Characteristics (continued)
450
CDTY = 2.2 mF
Dimming Frequency= 300 Hz
400
1.5%
1%
TDADJ On-Time Extension (ms)
IIDSRCH, IIDSRDC Change From Value at 25oC (%)
2%
Discharge Current
0.5%
0
Charge Current
-0.5%
-1%
-1.5%
350
CDADJ 3.3 nF
300
250
200
150
CDADJ 1.0 nF
100
CDADJ 330 pF
50
-2%
0
-40
-20
0
20
40
60
80
100
120
140
0
20
40
60
80
100
Temperature (°C)
Dimming PWM Duty Cycle (%)
Figure 13. DSR Currents vs Temperature
Figure 14. LLC ON-Time Extension vs Dimming Duty Cycle
14
330
CDADJ = 2.2 nF
VDTY = 2.6 V
320
CLOAD = 100 pF
TA = -40oC
LEDSW Output
12
TA = 125oC
10
300
LEDSW Voltage (V)
TDADJ On-Time Extension (ms)
310
290
280
270
260
8
TA = 25oC
6
DIM Input
4
250
2
240
0
230
-40
12
-20
0
20
40
60
80
100
120
140
-1
0
1
2
3
4
5
6
7
8
9
Temperature (°C)
Time (ms)
Figure 15. LLC ON-Time Extension vs Temperature
Figure 16. LEDSW Rise and Fall vs Time
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8 Detailed Description
8.1 Overview
The UCC25710 is a highly integrated LLC controller designed specifically for multi-string LED lighting
applications. The half-bridge LLC control is combined with independent PWM dimming or non-dimming of the
LED current for control of the light output.
The UCC25710 is designed to provide power from a high voltage DC bus, such as the output from a PFC stage.
Input over current-sensing protects the system in the event of a fault and gate drive outputs provide the drive
signals to the LLC stage. Output overvoltage and undervoltage provide additional protection. LED current is
sensed with a resistor in series with the LED’s. The UCC25710 has separate enable and dimming inputs.
This arrangement of a multi-transformer architecture, as shown in Figure 25, results in a highly efficient power
supply.
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8.2 Functional Block Diagram
UVLO
VCC
1
+
VVREF
RST Gen
VVCCON/VCCOFF
9.3 V/9.0 V
*
S
Q
R
Q
2.5 mA
RESET
H
ENBL
VREF
FAULT
delay
5V
REF
5
L
ENBL
TRSTDLY
10 ms
VVREF
7 DTY
~4 V
IDADJCH
20 mA
BLON 10
200 kW
+
SS-END
8
DADJ
9
DIM
6
LEDSW
VVREF
GD Enable
2
200 kW
LLC-OFF
Dead Time
GD1
3
OFF
ON
H
GD2
Dimming PWM
Edge Sync
D
80 kW
Q
2*F
GND
4
CLR
FSW
VCO
FMIN 20
80 kW
Q
SS-END
GD Toggle
FMAX
D
RESET
Q
LED-ON
FMIN
VVCO
FMAX 19
1V
0.9V
CLR
Q
4V
Zero Frequency Command
VVCO
VCLLTH
1.9 V
Latch-Off
LATCH -OFF
VCLREFCLO, 0.5 V
VCLREFCHI, 2.8 V
CREF 15
+
+
+
Low ICC
CS 16
GMICOMP
510 mS
FAULT
LED-ON
delay
2.4 ms
Current
Amplifier
Q
S
Q
R
UVLO
VVREF
H
TSD
DIM ON/OFF
CLAMP
+
+
VVREF
ICOMP 17
Dimming Slew
Control
ICOMP
IDSRCH
44 mA
GND
12 OV
+
LLC-OFF
VOVTH
2.6 V/2.4 V
L
4 kW
DSR 14
VVREF
ISS
2.5 mA
13 CL
VCLTH
0.95 V/0.475 V
H
IDSRDC
44 mA
SS Clamp
+
le
b
isa
D
SS-END
SS 18
+
VUVTH
2.4 V/2.6 V
11 UV
Soft Start
VSSTH
4.2 V
S
Q
*
Q
R
UCC25710
RESET
14
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8.3 Feature Description
Signal names and pin functions are depicted in Functional Block Diagram.
8.3.1 Multi-transformer Architecture
The multi-transformer LED driver architecture is a very attractive solution for driving multiple LED strings at the
same current using a single power train and control device. Excellent LED string current matching from string to
string (
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