UCC2750DWTR

application INFO available UCC2750 UCC3750 Source Ringer Controller FEATURES DESCRIPTION • Provides Control for Flyback Based Four Quadrant Amplifier Topology The UCC3750 Source Ringer Controller provides a complete control and drive solution for a four quadrant flyback-based ring generator circuit. The IC controls a primary side switch, which is modulated when power transfer is taking place from input to output. It also controls two secondary switches which act as synchronous rectifier switches during positive power flow. These switches are pulse-width-modulated when the power is being delivered back to the source. • Onboard Sine Wave Reference with Low THD • Selectable Ringing Frequency for Different Phone Systems (20Hz, 25Hz and 50Hz) • Programmable Output Amplitude and DC Offset • DC Current Limiting for Short Circuit Protection • Secondary Side Voltage Mode Control • Operates from a Single 5V Supply The UCC3750 has an onboard sine wave reference with programmable frequencies of 20Hz, 25Hz and 50Hz. The reference is derived from a high-frequency (32kHz) crystal connected externally. Two frequency-select pins control an internal divider to give a sinusoidal output at 20Hz, 25Hz or 50Hz. The ring generator can also be used at other frequencies by supplying externally generated sine-waves to the chip or by clocking the crystal input at a fixed multiple of the desired frequency. Other features included in the UCC3750 are programmable DC current limit (with buffer amplifier), a charge-pump circuit for gate drive voltage, internal 3V and 7.5V references, a triangular clock oscillator and a buffer amplifier for adding programmable DC offset to the output voltage. The UCC3750 also provides an uncommitted amplifier (AMP) for other signal processing requirements. TYPICAL APPLICATION 0V VOUT –48V VIN 48V VOUT 28 26 GD2 2 27 25 GD3 ENBL GD1 UCC3750 REF VCP 4 VS 2 6 24 RT 23 CT VS 1 5 1 RGOOD VDD 7 11 OUTDC OUT2 15 12 NEGDC 13 AMP OUT 14 AMP IN NEG2 18 22 XTAL1 OUT1 16 21 XTAL2 NEG1 17 20 FS 0 19 FS 1 S INFLT 10 5V S INREF S WRLY GND 9 8 3 C17 0.047µF UDG-99073 SLUS172C - DECEMBER 1999 - REVISED AUGUST 2005 UCC2750 UCC3750 CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS Input Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V Maximum Forced Voltage VCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 13.2V VS1, VS2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 5V OUT1, OUT2, AMPOUT, OUTDC Maximum Forced Voltage . . . . . . . . . . . . . . . . –0.3V to 7.5V Maximum Forced Current . . . . . . . . . . . . . . Internally Limited NEG1, NEG2, AMPIN, NEGDC Maximum Forced Voltage . . . . . . . . . . . . . . . . –0.3V to 7.5V SINREF, SINFLT Maximum Forced Voltage . . . . . . . . . . . . . . . . –0.3V to 7.5V Logic Inputs Maximum Forced Voltage . . . . . . . . . . . . . . . . –0.3V to 7.5V Reference Output Current (REF) . . . . . . . . . . Internally Limited Output Current (GD1, GD2, GD3) Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5A Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C DIL-28, SOIC- 28 (Top View) N Package, DW Package Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Databook for thermal limitations and considerations of packages. RGOOD 1 28 GD2 GD1 2 27 ENBL GND 3 26 GD3 VCP 4 25 REF VS 1 5 24 RT VS 2 6 23 CT VDD 7 22 XTAL1 S WRLY 8 21 XTAL2 S INREF 9 20 FS 0 S INFLT 10 19 FS 1 OUTDC 11 18 NEG2 NEGDC 12 17 NEG1 AMP OUT 13 16 OUT1 AMP IN 14 15 OUT2 ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the UCC3750, –40°C to +85°C for the UCC2750, RT = 14k, CT = 470pF, CREF = 0.1µF, FS0 = 0, FS1 = 0, VDD = 5V. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.5 1 mA VDD Supply Supply Current - Active With 12V Supplied to VCP and Charge Pump Disabled Internal Reference w/External Bypass Output Voltage (REF) 7.55 7.8 V Load Regulation IREF = 0mA – 2mA 7.3 30 60 mV Line Regulation VCP = 10V to 13V, IREF = 1mA 3 15 mV Amplifier Input Voltage Error, DC Offset and Amp Amplifiers DC Limit Amplifier 2.9 3 3.1 V 0.7125 0.75 0.7875 V 15 100 nA Input Bias Current AVOL VOUT = 2V to 4V VOH Source 100µA VOL Sink 100µA Short Circuit Current VIN = 0V and 5V with VOUT = 0V and 5V 0.5 TJ = 25°C, Program Frequency–Reference Frequency 70 5.35 dB 6 7.0 V 0.2 0.65 V 2 3 mA –1 0 1 Hz 2 % 0.475 0.5 0.525 V 2.85 3.0 3.15 V Sine Reference Accuracy Total Harmonic Distortion (Note 1) Amplitude Peak Offset 2 UCC2750 UCC3750 ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the UCC3750, –40°C to +85°C for the UCC2750, RT = 14k, CT = 470pF, CREF = 0.1µF, FS0 = 0, FS1 = 0, VDD = 5V. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Oscillator Accuracy 108 128 148 kHz Peak Voltage 4.6 4.75 4.9 V Valley Voltage 2.9 3.05 3.2 V 10 30 Ω 10 30 Ω 12 14 V Charge Pump Switch Pull Up Resistance (VS1, VS2) Switch Pull Down Resistance (VS1, VS2) VDD = 5V, IVCP = 10mA Output Voltage (VCP) 11 Output Drivers Pull Up Resistance 9 15 Ω Pull Down Resistance 9 15 Ω Rise Time CL = 2.7nF 50 100 ns Fall Time CL = 2.7nF 50 100 ns Current Limit DC Limit Threshold Voltage Positive R5/R6 = 3 0.4 0.5 0.6 V DC Limit Threshold Voltage Negative R5/R6 = 3 –0.6 –0.5 –0.4 V 48 50 % 50 % Duty Cycle Maximum PWM Duty Cycle Rectifier Duty Cycle Note 1: Guaranteed by measuring the steps of the PWL Sine Wave. STATE 0 1 2 3 4 % VCC 0.3333 0.3384 0.3528 0.3745 0.4 VALUE FOR REF = 7.5 2.5 2.538 2.646 2.808 3 STATE 5 6 7 8 % VCC 0.4255 0.4471 0.4616 0.4666 VALUE FOR REF = 7.5 3.191 3.353 3.462 3.5 PIN DESCRIPTIONS AMPIN: Inverting input of the uncommitted amplifier. Table I. Frequency selection table (for 32kHz crystal). AMPOUT: Output of the uncommitted amplifier. FS0 0 1 0 1 CT: This pin programs the internal PWM oscillator frequency. Capacitor from CT to GND sets the charge and discharge time of the oscillator. ENBL: Logic input which enables the outputs and the charge pump when high. ENBL should be pulled low to turn the outputs off. FS1 0 0 1 1 SINREF (Hz) 20 25 50 High Impedance GD1: Output driver that controls the primary side switch in a flyback converter through a gate drive transformer. The output signal on this pin is PWM during positive power transfer modes and zero during negative power transfer modes. FS0, FS1: Frequency select pins for the internal sine-wave generator. Table 1 provides the SINREF frequencies as a function of FS0 and FS1 when a 32kHz crystal is used at the crystal inputs (XTAL1, XTAL2). Other proportional frequencies can be obtained with a different crystal. Inputs FS0 and FS1 are TTL compatible. 3 UCC2750 UCC3750 PIN DESCRIPTIONS (cont.) GD2: Output driver that controls the p-channel secondary side switch in the flyback converter. The output signal on this pin is PWM during mode 4 (Fig. 2) when the reference signal is negative and power is being returned to the input. This pin functions as a synchronous rectifier output during mode 1 with positive reference signal and positive power transfer. This output is logically inverted to provide the correct polarity drive signal for a p-channel switch. REF: Internal 7.5V reference. For best results, bypass to GND with a ceramic capacitor(>0.1µF). GD3: Output driver that controls the n-channel secondary side switch in the flyback converter. The output signal on this pin is PWM during mode 2 (Fig. 2) when the reference signal is positive and power is being returned to the input. This pin functions as a synchronous rectifier output during mode 3 with a negative reference signal and positive power transfer. SINFLT: This signal is the buffered version of SINREF. This signal is summed with the DC offset level with appropriate scaling. RGOOD: Logic output that indicates that the error amplifier output is within range (0< D< 0.5). This pin can source upto 0.5mA of current. RT: Resistor from RT to GND helps set the oscillator frequency. RT programs the charge and discharge currents of CT. GND: Reference point for the internal reference and all thresholds. Also provides the signal return path for all other pins. SINREF: This pin is the output of the sine-wave reference generator. It has a high output impedance (≈25kΩ). A 0.01µF capacitor to GND is recommended to provide smoothing of the sinewave. When FS0 and FS1 are both set high, the sine reference generator is disabled allowing this pin to accept an external sinewave input. NEG1: Inverting input of the buffer amplifier that acts as a summing junction for the DC (battery) offset voltage and sinewave reference. SWRLY: Logic output that leads the battery offset crossings (by typically 5ms) to allow “zero voltage” relay switching. This pin can typically source 250µA. NEG2: Inverting input of the error amplifier where the ringer output voltage and the reference signal with the desired offset are applied with a weighted sum. Feedback compensation is connected between NEG2 and OUT2. XTAL1: Crystal connection for external crystal. This pin can be also used to clock the internal sine wave generator when XTAL2 is connected to VDD/2. XTAL2: Crystal connection for external crystal. VCP: External connection for charge pump storage capacitor. A capacitance ≥2.2mF is recommended for low charge pump output ripple. The voltage at this pin is used by the output drivers for gate drive voltages. Alternatively, a regulated gate drive voltage (>10V) can be connected at this pin while leaving the charge pump circuit at nodes VS1, VS2 disconnected. NEGDC: Inverting input of the amplifier used for DC current limiting. OUT1: Output of the buffer amplifier that provides scaling and filtering for the reference signal before feeding it into the error amplifier. This output is also used internally to select the PWM mode for the flyback converter. OUT2: Output of the error amplifier. Used to connect compensation components. This output’s absolute value determines the duty cycle of the PWM pulse. The polarity of this signal also determines the PWM mode. VDD: External supply input used to bias internal logic functions. Typically a regulated 5V supply is connected between this pin and GND. It also is the input voltage for the voltage tripler circuit to generate the gate drive voltage. OUTDC: Output of the DC current limit amplifier. The DC current limit is activated when this pin is above 4.5V or below 1.5V. VS1, VS2: Voltage switches for the voltage tripler (charge pump circuit). They provide different voltage levels to external capacitors in order to pump up the voltage from VDD to VCP. 4 UCC2750 UCC3750 DETAILED BLOCK DIAGRAM SWRLY FS0 8 XTAL1 XTAL2 XTAL OSC 21 13 AMPIN 14 SINREF 19 9 SINFLT NEG1 10 12 VCM – AMP + VCM – + 5 VS2 6 VDD 7 15 REF CHARGE PUMP + – REF – + VCM MAG FULLWAVE RECTIFIER SIGN ERROR AMP MODE INTERNAL REFERENCE REF=7.5V VCM = 3.0V + – CONTROL LOGIC MODE SIGN SIGN DC CURRENT LIMIT MAG VS1 OUT2 18 VCP 4 4 NEG2 16 DC OFFSET AMP 11 VCP OUT1 – + VCM REF NEGDC 17 SINE REFERENCE GENERATOR VCM OUTDC FS1 REF 22 AMPOUT 20 PWM OUT1 OUT2 0 0 PWM OFF 0 1 OFF PWM OUT3 RECIRC OFF 1 0 OFF 1 1 PWM RECIRC OFF 2 GD1 28 GD2 26 GD3 VCP VCP PWM OFF RAMP CLOCK VCM GENERATOR 25 3 24 23 1 27 REF GND RT CT RGOOD ENBL UDG-99074 Note: All pin numbers are for N or DW Packages. APPLICATION INFORMATION The UCC3750 provides complete control and protection functions for a four quadrant flyback converter used to generate ring signals for telephone circuits. A typical application circuit for a 15 REN ring generator is shown in Fig. 1. DC-DC converter operation where Q1 is modulated with the PWM signal and rectification is provided through the Q2, DR2 path to provide a positive output proportional to the increasing, positive reference voltage. The pulse-width is controlled by the error amplifier output to increase or decrease the output as dictated by the reference. The maximum duty cycle is limited to 50% to prevent DR1 from turning on prior to Q2/DR2. As shown, the flyback converter takes a DC input (typically 48V) and provides an isolated output with a programmable frequency (and amplitude) AC signal superimposed on a programmable DC offset. The power path consists of a primary side PWM switch Q1, primary return rectifier DR1, a 4-winding transformer T1, output rectifiers DR2 and DR3, synchronous/PWM switches Q2 and Q3, and output filter CF. Resistor RSENSE provides the output current sensing for protection circuits. In mode 2, the reference begins to decrease, necessitating that the power transfer back to the input. For this mode, switch Q3 needs to be modulated while DR1 acts as the rectifier back to the input. The UCC3750 has mode decoding circuitry which automatically directs the PWM signal to Q3 and turns off Q1. Different operating modes of the converter are depicted in Table 2. Fig. 2 shows the output voltage and current waveforms for a purely capacitive load and identifies the four operating modes. Fig. 3 shows the PWM waveforms for the circuit and Fig. 4a - 4d show the equivalent circuits under the operating modes. The addition of Q2, Q3 and primary diode facilitates true four quadrant operation where both the output voltage and power transfer can be bi-directional. Mode 1 is similar to the commonly used Table II. Operating modes. 5 Mode Reference Polarity Power Flow E.A. Output 1 2 3 4 + + – – + – + – – + + – Source Rectifier (PWM) Switch Switch Q1 Q2 Q3 (D1) Q1 Q3 Q2 (D1) RTN VIN C23 C1 C2 0.47µF 100µF 100µF R22 C22 R1 10k R23 Figure 1. Typical application circuit. 6 1 CR9 3 4 Q6 MP S A06 2 5 1 6 Q5 2 Q4 2N5457 3 1 2N7001DICT 3 2 1 C3 0.1µF R20 1 2 C21 T2 R2 R6 10k 3 VDD C5 0.47µF 4 Q3 S3 S2 S4 S1 X1 32kHz R5 30k R9 AMP IN XTAL1 XTAL2 14 22 21 19 25 16 17 OUT1 NEG1 8 9 3 10 18 GND C11 0.22µF CR5 C9 0.47µF VDD C10 2.2µF C16 2.2µF R12 2.7k C18 22µF R14 3.3M C13 1µF C19 100µF R26 REF R15 15k R13 62k R25 10k C14 1nF R11 148k CR7 C12 0.22µF CR6 15 7 5 6 4 NEG2 OUT2 VDD VS 1 VS 2 VCP S INFLT S WRLY C17 0.047µF 27 R18 ENBL REF S INREF FS 1 FS 0 AMP OUT 13 20 NEGDC OUTDC RGOOD CT RT GD1 26 GND GD3 12 11 1 23 24 2 28 GD2 C4 1µF 250V R17 CR12 C6 0.1µF C7 470pF R4 16k R3 CR10 CR8 IRF840 MTP 2P 50E Q2 CR3 BYV26C CR2 BYV99 R21 7,9 10 CR1 BYV99 T1 C20 VB REF VDD 5V R27 R10 148k VOUT UCC2750 UCC3750 APPLICATION INFORMATION (cont.) UDG-99075 UCC2750 UCC3750 APPLICATION INFORMATION (cont.) When the reference signal goes from positive to negative, a transition is made from mode 2 to mode 3. In mode 3, the converter once again acts as a DC-DC flyback converter (with negative output). Similar to mode 1, Q1 is controlled by the PWM output, however, the rectifying path is now through Q3/DR3 as the output polarity is reversed. At the mode boundaries, there could be some distortion which won’t affect the THD too much as it is near zero crossings. Finally, as the reference signal starts increasing towards zero, the direction of power transfer is again reversed and Q2 is PWMed in mode 4. It should be noted that in modes 2 and 3 when the reference is decreasing, the phase of the feedback path is inverted compared to the other two modes. Traditional PWM methods will result in instability due to this characteristic. The UCC3750 separates the error signal magnitude and polarity and determines the correct PWM signal based on a separate mode determination circuit. UDG-96172-1 UDG-96173 Figure 2. Operating modes. Figure 3. Circuit waveforms. UDG-96162-1 UDG-96163 Figure 4a. Mode 1: Forward power transfer, positive output. Figure 4b. Mode 2: Reverse power transfer, positive output. UDG-96164-1 UDG-96165-1 Figure 4c. Mode 3: Forward power transfer, negative output. Figure 4d. Mode 4: Reverse power transfer, negative output. 7 UCC2750 UCC3750 APPLICATION INFORMATION (cont.) R13  R13 R13   • VCM – VOUT1= 1+ + • REF R26  R14 R26  Sine Reference Generator The IC has a versatile low frequency sinewave reference generator with low harmonic distortion and good frequency accuracy. In its intended mode as shown in Fig. 5, the reference generator will take an input from a 32kHz crystal (connected between XTAL1 and XTAL2) and generate a sine-wave at 20Hz, 25Hz or 50Hz based on the programming of pins FS0 and FS1 (See Table 2). If the crystal frequency is changed, the output frequencies will be appropriately shifted. C-2 type Quartz crystals (Epson makes available through DigiKey) are recommended for this application. If the frequency accuracy is not a major concern, the more common and less expensive clock crystal (C-type) at 32.768kHz can be used with a minor output frequency offset (20.5Hz instead of 20Hz). Additionally, the XTAL1 input can be clocked at a desired frequency to get a different set of output frequencies at the sine-wave output (with divide ratios of 1600, 1280 and 640). The sine-wave output is centered around an internal reference of 3V. A capacitor from SINREF to GND helps provide smoothing of the sine wave reference. Recommended value is at least 0.01µF and maximum of 0.1µF. When FS0 and FS1 are both 1 (high), the sine reference is disabled and external sine-wave can be fed into the SINREF pin. This signal should have the same DC offset as the internal sine-wave (3V). – (1) R13 R13 • VB – • VAC R14 R15 In order to nullify the effect of VCM on this value, the ratio of R26 to R14 should be made 1.5. With this ratio, the equation becomes: VOUT1= VCM – R13 R13 • VB – • VAC R14 R15 (2) VOUT1 is the reference voltage that the second amplifier (AMP2) uses to program the output voltage. Assuming that Z4 is high DC impedance, the output voltage is derived by summing the currents into pin 18. The output is given as:  R10 R10   • VCM VO = 1+ +  R27 R12  – (3) R10 R10 • REF – • VOUT1 R12 R27 Again, if the ratio of R27 to R10 is made 1.5, the effect of VCM is nullified and the output voltage becomes (after substituting for VOUT1): VO = Reference and Error Amplifier The recommended circuit connections for these circuits are shown in Fig. 6. The sine-wave is added to a DC offset to create the composite reference signal for the error amplifier. The DC reference can vary over a wide range. For pure AC outputs it is zero, while in many common applications, it is the talk battery voltage (–48V). The UCC3750 accomplishes this task by summing the two signals weighted by resisting R14 and R15. The output of AMP1 also helps determine the mode of the circuit. R10 • R13 R10 • R13 • VB + • VAC R12 • R14 R12 • R15 (4) From equation 4, it can be seen that if the output voltage DC value has to track VB directly, the following condition should be forced: R10 • R13 = R12 • R14 (5) However, in some cases, this becomes impractical due to large AC gain required form VAC to VO. Only a small part of the gain can be accommodated in the first amplifier stage due to its output voltage limitations. As a result, the required resistance values become very high. This Referring to Fig. 6, the output of AMP1 is given by : UDG-96166-1 UDG-96167-1 Figure 5. Sine-wave generator. Figure 6. Error amplifier setup. 8 UCC2750 UCC3750 APPLICATION INFORMATION (cont.) problem is only manifested for high values of VB (e.g. 48V) and can be alleviated by using a fraction of the required DC offset as the VB input and regaining the offset with resistive ratios. ulation turns on the PWM signal when the ramp signal falls below MAG on the falling slope and turns it off at the end of the clock cycle. This technique enables synchronized turn-on of the rectifier switches immediately after the PWM pulse is turned off. The triangular nature of the ramp ensures that the maximum duty cycle of the PWM output is 50%, providing inherent current limiting. The error amplifier compares the reference signal with the output voltage by way of weighted sum at its inverting input. The error signal is further processed to separate its polarity and magnitude. An absolute value circuit (precision full-wave rectifier) is used to get the magnitude information. The polarity is used along with the reference signal polarity to determine the mode information. The absolute value circuit provides phase inversion when appropriate for modes 2 and 3 to maintain the correct loop gain polarity. While the output of the error amplifier swings around 3V, the full-wave rectifier output (MAG) converts it into a signal above 3V. This signal is compared to the oscillator ramp to generate the PWM output. Control Logic and Outputs The PWM signal is processed through control logic which takes into account the operating mode and output polarity to determine which output to modulate. The logic table for the outputs is given in Table 2. For example, assume that the reference signal is in the first quadrant (positive and increasing). The output will lag the reference by a certain delay and hence the error amp output will be positive, resulting in SIGN = 0. The logic table indicates that GD1 is modulated during this phase allowing power transfer to increase the output voltage to keep up with the reference. Increasing error (MAG) will result in larger duty cycle and enable the output to increase and catch up with the reference. If the output becomes higher than the reference (as is likely in the second quadrant when the reference is dropping), the SIGN becomes 1 and GD3 is modulated to decrease the output level by transferring power to the input. At the boundary of the first and second quadrant, there may be some switching back and forth between modes as the reference slope crosses through zero. Some of this switching can be eliminated by judicious selection of error amplifier filtering and compensation components. In the first quadrant, when PWM is applied to Q1, Q2 is turned on in the rectifier mode by the clock signal to allow the flyback transformer flux to Oscillator and PWM Comparator The UCC3750 has an internal oscillator capable of high frequency (>250kHz) operation. A resistor on the RT pin programs the current that charges and discharges CT, resulting in a triangular ramp waveform. Fig 7. shows the oscillator hook-up circuit. The ramp peak and valley are 4.75V and 3V respectively. The nominal frequency is given by: fOS C = 1 1.17 • RT • CT The ramp waveform and the rectified output of the error amplifier are compared by the PWM comparator to generate the PWM signal. The PWM action is disabled on the positive slope of the ramp signal. Leading edge mod- 3V RT RT 24 4.75V IR IR 3.0V – + R Q + – S CT CT 23 IR UDG-99077 Figure 7. Oscillator setup. 9 UCC2750 UCC3750 APPLICATION INFORMATION (cont.) R S ENS E 11 OUTDC R5 R6 12 NEGDC VCM 4 – DC + TO P WM UDG-96170-1 Figure 8. Current limiting. Figure 9. Charge pump circuits. reset (and to transfer power to the output). Operation in quadrants 3 and 4 is symmetrical to the first two quadrants with Q2 and Q3 interchanged. Note that the output signal for Q2 is logically inverted to allow for driving the p-channel switch. An n-channel switch can also be used for Q2, but the drive circuit must be transformer isolated and the polarity inverted. The outputs are designed for high peak current drive and low internal impedance. In isolated systems, GD1 must be coupled to Q1 using a gate-drive transformer. Charge Pump and Reference The UCC3750 is designed to work on the secondary side of an isolated power supply. It requires a 5V power supply with respect to its GND pin to operate. Note that the GND pin of the IC is also the reference point of the ring signal that is generated by the converter. If the converter output is connected in series with any other voltage, it should be ensured that the available supply voltage is referenced to the converter output return. The IC along with its associated charge pump components shown in Fig. 9 generates all the other voltages the system requires. The UCC3750 typically requires about 5mA to operate without any loads on the drive outputs. The charge pump capacitor should be large enough to keep the VCP fairly constant when driving Q1-Q3 in the converter. DC Current Limit The DC current limit function provides protection against short circuit conditions by limiting the maximum current level and shutting off the PWM function when the limit point is reached. 120 The DC limit is activated when DC out is below 0.5 VCM or above 1.5 • VCM. The DC current limit can be programmed by setting: 160 100 140 MAG. 80 MAGNITUDE (dB) With this ratio, a symmetric DC limit with thresholds of ±0.5V is obtained. For other ratios, the positive and negative voltage thresholds for current sense signal are given by: VCM VS ENS E (P OS ) = 4 120 60 100 40 80 PHAS E 60 PHASE (Degree) R5 = 3. R6 VS ENS E (NEG) = 180 20 40 0  R6   • 1 R5  20 -20 1 VCM  5R6   • 14  R5  10 100 100 1000 10k 10000 100k 100000 1M 100000 0 FREQUENCY (Hz) 0 10M 1E+07 Figure 10. Frequency response to error amplifiers. Even though the DC current is typically sensed in the secondary, the currentl limit is applied fo the active PWM switch at the time. For example, if Q1 is the PWM switch and DCLIM is activated, the UCC3750 will prevent trun-on for Q1 during the negative slope of the ramp (Fig. 2). The DC limit is functional on a cycle-by-cycle basis. Table II. Revision History Revision C 10 Date 08/2005 Comment Changed amplifier input bias current maximum limit from 600 nA to 100 nA and Typical from 500 nA to 15 nA. PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) UCC2750DW ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples UCC2750DWG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples UCC2750DWTR ACTIVE SOIC DW 28 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples UCC2750DWTRG4 ACTIVE SOIC DW 28 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples UCC3750DW ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples UCC3750DWG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples UCC3750DWTR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples UCC3750DWTRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples UCC3750N ACTIVE PDIP N 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples UCC3750NG4 ACTIVE PDIP N 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2010 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC3750DWTR Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC3750DWTR SOIC DW 28 1000 346.0 346.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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