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UCC27527, UCC27528
SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
UCC2752x Dual 5-A High-Speed Low-Side Gate Driver Based on
CMOS Input Threshold Logic
1 Features
3 Description
•
•
•
•
The UCC2752x family of devices are dual-channel,
high-speed, low-side gate driver devices capable of
effectively driving MOSFET and IGBT power
switches. Using a design that inherently minimizes
shoot-through current, UCC2752x can deliver highpeak current pulses of up to 5-A source and 5-A sink
into capacitive loads along with rail-to-rail drive
capability and extremely small propagation delay
typically 17 ns. In addition, the drivers feature
matched internal propagation delays between the two
channels which are very well suited for applications
requiring dual-gate drives with critical timing, such as
synchronous rectifiers. The input pin thresholds are
based on CMOS logic, which is a function of the VDD
supply voltage. Wide hysteresis between the high and
low thresholds offers excellent noise immunity. The
Enable pins are based on TTL and CMOS compatible
logic, independent of VDD supply voltage.
1
•
•
•
•
•
•
•
•
•
•
•
•
Industry-Standard Pin Out
Two Independent Gate-Drive Channels
5-A Peak Source and Sink Drive Current
CMOS Input Logic Threshold
(Function of Supply Voltage on VDD Pins)
Hysteretic Logic Thresholds for High Noise
Immunity
Independent Enable Function for Each Output
Inputs and Enable Pin Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
4.5-V to 18-V Single Supply Range
Outputs Held Low During VDD UVLO (Ensures
Glitch-Free Operation at Power Up and Power
Down)
Fast Propagation Delays (17-ns Typical)
Fast Rise and Fall Times (7-ns and 6-ns Typical)
1-ns Typical Delay Matching Between 2 Channels
Outputs Held in Low When Inputs Floating
SOIC-8, and 3-mm x 3-mm WSON-8 Package
Options
Operating Temperature Range of –40°C to 140°C
–5-V Negative Voltage Handling Capability on
Input Pins
Device Information(1)
PART NUMBER
UCC27527
UCC27528
PACKAGE
BODY SIZE (NOM)
WSON (8)
3.00 mm x 3.00 mm
SOIC (8)
4.90 mm x 3.91 mm
WSON (8)
3.00 mm x 3.00 mm
SOIC (8)
4.90 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
Switch-Mode Power Supplies
DC-to-DC Converters
Motor Control, Solar Power
Gate Drive for Emerging Wideband Gap Power
Devices Such as GaN
Dual Input Configuration
Dual Non-Inverting Inputs
UCC27527
UCC27528
8
INA+
7
INB+
3
6
OUTA
4
5
VDD
INA-
1
INB-
2
GND
OUTB
ENA
1
8
ENB
INA
2
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
+
+
•
•
•
•
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27527, UCC27528
SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
6
6
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
11.3 Thermal Considerations ........................................ 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Revision D (July 2013) to Revision E
•
Page
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision C (June 2013) to Revision D
Page
•
Added OUTA, OUTB voltage field and values. ...................................................................................................................... 5
•
Changed table note from "Values are verified by characterization and are not production tested." to "Values are
verified by characterization on bench."................................................................................................................................... 5
•
Changed Bias Current TYP values from 170 µA to 180 µA. .................................................................................................. 6
Changes from Revision B (January 2013) to Revision C
Page
•
Changed UCC27527 packaging options ................................................................................................................................ 4
•
Added UCC27527 Bias Current specifications....................................................................................................................... 6
•
Added an updated Output Stage section. ............................................................................................................................ 15
•
Added UCC2752X Gate Driver Output Structure image ...................................................................................................... 15
•
Added updated Drive Current and Power Dissipation section. ............................................................................................ 21
•
Added a PSW... equation. .................................................................................................................................................... 21
Changes from Revision A (December 2012) to Revision B
•
2
Page
Changed Feature bullet from "-5-V Negative Voltage Handling Capability on Input and Enable Pins" to -5-V
Negative Voltage Handling Capability on Input Pins"............................................................................................................. 1
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SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
Changes from Original (December 2012) to Revision A
Page
•
Changed marketing status from Product Preview to Final .................................................................................................... 1
•
Added note to packaging section, "DSD package is rated MSL level 2" .............................................................................. 4
•
Changed ENA, ENB voltage from (-6.5 V to 20) to (-0.3 to 20). ............................................................................................ 5
•
Changed Enable voltage, ENA and ENB min value from -5 V to 0 V. ................................................................................... 5
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: UCC27527 UCC27528
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UCC27527, UCC27528
SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
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5 Description (continued)
The UCC27528 is a dual noninverting driver. UCC27527 features a dual input design which offers flexibility of
both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin can be
used to control the state of the driver output. The unused input pin can be used for enable and disable functions.
For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family
to ensure that outputs are held low when input pins are in floating condition. UCC27528 features Enable pins
(ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up
to VDD for active high logic and can be left open for standard operation.
6 Pin Configuration and Functions
8-Pin WSON and SOIC
DSD and D Package
Top View
UCC27528DSD
(TOP VIEW)
UCC27527D
(TOP VIEW)
UCC27528D
(TOP VIEW)
UCC27527DSD
(TOP VIEW)
ENA 1
8
ENB
INA- 1
8
INA+
ENA
1
8
ENB
INA-
1
8
INA+
INA 2
7
OUTA
INB- 2
7
INB+
INA
2
7
OUTA
INB-
2
7
INB+
GND 3
6
VDD
GND 3
6
OUTA
GND
3
6
VDD
GND
3
6
OUTA
INB 4
5
OUTB
OUTB 4
5
VDD
INB
4
5
OUTB
OUTB
4
5
VDD
Pin Functions (UCC27527)
PIN
NUMBER
NAME
I/O
DESCRIPTION
1
INA-
I
Inverting Input to Channel A: when Channel A is used in Non-Inverting configuration
connect INA- to GND in order to Enable Channel A output, OUTA held low if INA- is
unbiased or floating.
2
INB-
I
Inverting Input to Channel B: when Channel B is used in Non-Inverting configuration
connect INB- to GND in order to Enable Channel B output, OUTB held low if INB- is
unbiased or floating.
3
GND
–
Ground: All signals referenced to this pin.
4
OUTB
I
Output of Channel B
5
VDD
O
Bias Supply Input
6
OUTA
I
Output of Channel A
7
INB+
O
Non-Inverting Input to Channel B: When Channel B is used in Inverting configuration
connect INB+ to VDD in order to Enable Channel B output, OUTB held low if INB+ is
unbiased or floating.
8
INA+
I
Non-Inverting Input to Channel A: When Channel A is used in Inverting configuration
connect INA+ to VDD in order to Enable Channel A output, OUTA held low if INA+ is
unbiased or floating.
Pin Functions (UCC27528)
PIN
NUMBER
NAME
I/O
DESCRIPTION
1
ENA
I
Enable input for Channel A: ENA biased low Disables Channel A output regardless of
INA state, ENA biased high or floating Enables Channel A output, ENA allowed to
float.
2
INA
I
Input to Channel A: Non-Inverting Input in UCC27528, OUTA held low if INA is
unbiased or floating.
3
GND
–
Ground: All signals referenced to this pin.
4
INB
I
Input to Channel B: Non-Inverting Input in UCC27528, OUTB held low if INB is
unbiased or floating.
5
OUTB
O
Output of Channel B
6
VDD
I
Bias supply input
4
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SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
Pin Functions (UCC27528) (continued)
PIN
I/O
DESCRIPTION
NUMBER
NAME
7
OUTA
O
Output of Channel A
8
ENB
I
Enable input for Channel B: ENB biased low Disables Channel B output regardless of
INB state, ENB biased high or floating Enables Channel B output, ENB allowed to
float.
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
OUTA, OUTB voltage
MIN
MAX
VDD
–0.3
20.0
DC
–0.3
VDD + 0.3
Repetitive pulse < 200 ns (3)
–2.0
VDD + 0.3
Output continuous source/sink
current
IOUT_DC
Output pulsed source/sink current
(0.5 µs)
IOUT_pulsed
A
5
(4)
Operating virtual junction temperature, TJ range
Lead temperature
(1)
(2)
(3)
(4)
V
0.3
INA, INB, INA+, INA-, INB+, INB- voltage (4)
ENA, ENB voltage
UNIT
–6.5
20
–0.3
20
–40
150
Soldering, 10 s
300
Reflow
260
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
Values are verified by characterization on bench.
The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–4000
4000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–1000
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
Supply voltage range, VDD
4.5
12
18
V
Operating junction temperature range
–40
140
°C
–5
18
0
18
Input voltage, INA, INB, INA+, INA-, INB+, INBEnable voltage, ENA and ENB
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UNIT
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V
5
UCC27527, UCC27528
SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
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7.4 Thermal Information
UCC27527, UCC27528
THERMAL METRIC (1)
D
DSD
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
128
46.1
RθJC(top)
Junction-to-case (top) thermal resistance
77.7
50.7
RθJB
Junction-to-board thermal resistance
68.5
21.8
ψJT
Junction-to-top characterization parameter
20.7
1.1
ψJB
Junction-to-board characterization parameter
68.0
22.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
9.0
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS CURRENTS
IDD(off)
Startup current
VDD = 3.4 V,
INA=VDD,
INB=VDD
UCC27528
55
125
225
UCC27527
55
180
270
VDD = 3.4 V,
INA=GND,
INB=GND
UCC27528
25
125
225
UCC27527
25
180
270
TJ = 25°C
3.91
4.20
4.50
TJ = -40°C to 140°C
3.75
4.20
4.65
μA
UNDERVOLTAGE LOCKOUT (UVLO)
VON
Supply start threshold
VOFF
Minimum operating
voltage after supply start
3.60
3.90
4.40
VDD_H
Supply voltage
hysteresis
0.20
0.30
0.50
55
70
V
INPUTS (INA, INB, INA+, INA-, INB+, INB-), UCC2752X (D, DSD)
VIN_H
Input signal high
threshold
Output high for non-inverting input pins
Output low for inverting input pins
VIN_L
Input signal low
threshold
Output low for non-inverting input pins
Output high for inverting input pins
VIN_HYS
Input hysteresis
30
%VDD
38
17
ENABLE (ENA, ENB) UCC2752X (D, DSD)
VEN_H
Enable signal high
threshold
Output enabled
1.7
1.9
2.1
VEN_L
Enable signal low
threshold
Output disabled
0.95
1.10
1.25
0.70
0.80
1.10
VEN_HYS Enable hysteresis
V
OUTPUTS (OUTA, OUTB)
ISNK/SRC
Sink/source peak
current (1)
CLOAD = 0.22 µF, FSW = 1 kHz
VDDVOH
High output voltage
IOUT = -10 mA
0.075
VOL
Low output voltage
IOUT = 10 mA
0.01
ROH
Output pull-up
resistance (2)
IOUT = -10 mA
2.5
5
7.5
Ω
ROL
Output pull-down
resistance
IOUT = 10 mA
0.15
0.5
1
Ω
(1)
(2)
6
±5
A
V
Ensured by design.
ROH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC2752X output stage.
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SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
tR
Rise time
CLOAD = 1.8 nF, VDD = 10 V
7
tF
Fall time (1)
CLOAD = 1.8 nF, VDD = 10 V
6
tM
Delay matching between 2 channels
INA = INB, OUTA and OUTB at 50%
transition point, VDD = 10 V
1
tPW
Minimum input pulse width that
changes the output state (1)
VDD = 10 V
tD1, tD2
Input to output propagation delay
tD3, tD4
EN to output propagation delay
(1)
(1)
(1)
MAX
UNIT
4
ns
15
CLOAD = 1.8 nF, 7-V input pulse, VDD
= 10 V
6
17
26
CLOAD = 1.8 nF, 7-V enable pulse,
VDD = 10 V
6
13
23
See timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4
High
High
Input
Input
Low
Low
High
High
Enable
Enable
Low
Low
90%
90%
Output
Output
10%
10%
tD3
tD4
tD3
UDG-11217
Figure 1. Enable Function
(For Non-Inverting Input Driver Operation)
tD4
UDG-11218
Figure 2. Enable Function
(For Inverting Input Driver Operation)
High
High
Input
Input
Low
Low
High
High
Enable
Enable
Low
Low
90%
90%
Output
Output
10%
10%
tD1
tD2
UDG-11219
Figure 3. Non-Inverting Input Driver Operation
tD1
tD2
UDG-11220
Figure 4. Inverting Input Driver Operation
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7.7 Typical Characteristics
10
0.17
IN=Low/High
9
0.15
IDD (mA)
Startup Current (mA)
0.16
0.14
0.13
0.12
8
VDD=12V
CLoad=500pF
fSW=500kHz
7
0.11
Both Channel Switching
VDD=3.4V
0.10
−50
0
50
Temperature (°C)
100
6
−50
150
VDD = 12 V
fSW = 500 kHz
VDD = 3.4 V
50
Temperature (°C)
100
150
G001
CLOAD = 500 pF
Both Channel Switching
Figure 6. Operating Supply Current vs Temperature
(Outputs Switching)
Figure 5. Start-Up Current vs Temperature
0.8
4.8
INA/INB=VDD
INA/INB=GND
UVLO Rising
UVLO Falling
0.7
4.6
UVLO Threshold (V)
Operating Supply Current (mA)
0
G001
0.6
0.5
0.4
4.4
4.2
4
VDD=12V
0.3
−50
0
50
Temperature (°C)
100
3.8
−50
150
0
G001
50
Temperature (°C)
100
150
G001
VDD = 12 V
Figure 7. Supply Current vs Temperature (Outputs In DC
On/Off Condition)
Figure 8. UVLO Threshold vs Temperature
7.6
VDD=12V
EN High Threshold
EN Low Threshold
Enable Threshold (V)
Input Threshold (V)
7
2.2
VDD=12V
Input High Threshold
Input Low Threshold
6.4
5.8
5.2
1.8
1.4
4.6
4
−50
0
50
Temperature (°C)
100
150
1
−50
0
G001
VDD = 12 V
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100
150
G001
VDD = 12 V
Figure 9. Input Threshold vs Temperature
8
50
Temperature (°C)
Figure 10. Enable Threshold vs Temperature
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SLUSBD0E – JUNE 2013 – REVISED DECEMBER 2014
Typical Characteristics (continued)
7
1
Output Pull−Down Resistance (Ω)
Output Pull−Up Resistance (Ω)
RoH
6
5
4
VDD=12V
Iout=10mA
3
−50
0
VDD = 12 V
50
Temperature (°C)
100
RoL
0.8
0.6
0.4
VDD=12V
Iout=10mA
0.2
−50
150
0
G001
IOUT = 10 mA
VDD = 12 V
Figure 11. Output Pullup Resistance vs Temperature
50
Temperature (°C)
100
150
G001
IOUT = 10 mA
Figure 12. Output Pulldown Resistance vs Temperature
8
8
VDD=10V
Cload=1.8nF
7
Fall Time (ns)
Rise Time (ns)
7
6
5
6
5
VDD=10V
Cload=1.8nF
4
−50
0
VDD = 10 V
50
Temperature (°C)
100
4
−50
150
CLOAD = 1.8 nF
VDD = 10 V
Figure 13. Rise Time vs Temperature
100
150
G001
CLOAD = 1.8 nF
16
Turn−On
Turn_Off
Enable Propagation Delay (ns)
Input Propagation Delay (ns)
50
Temperature (°C)
Figure 14. Fall Time vs Temperature
20
18
16
14
VDD=10V
12
−50
0
G001
0
50
Temperature (°C)
100
150
Turn−On
Turn_Off
14
12
10
VDD=10V
8
−50
G001
VDD = 10 V
0
50
Temperature (°C)
100
150
G001
VDD = 10 V
Figure 15. Input To Output Propagation Delay vs
Temperature
Figure 16. En To Output Propagation Delay vs Temperature
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Typical Characteristics (continued)
30
VDD = 4.5 V
VDD = 12 V
VDD = 15 V
60
50
Cload=1.8nF
Both channels switching
40
Input to Output On Delay
Input to Output Off Delay
EN to Output On Delay
EN to Output Off Delay
26
Propagation Delays (ns)
Operating Supply Current (mA)
70
30
20
22
18
14
10
10
Cload=1.8nF
0
0
6
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
G000
Both Channels Switching
4
8
12
Supply Voltage (V)
CLOAD = 1.8 nF
Figure 17. Operating Supply Current vs Frequency
G000
Figure 18. Propagation Delays vs Supply Voltage
10
Cload=1.8nF
Rise time (ns)
Cload=1.8nF
Rise time (ns)
20
CLOAD = 1.8 nF
18
12
6
16
4
8
12
Supply Voltage (V)
16
8
6
4
20
4
8
12
Supply Voltage (V)
G000
16
CLOAD = 1.8 nF
CLOAD = 1.8 nF
Figure 19. Rise Time vs Supply Voltage
Figure 20. Fall Time vs Supply Voltage
20
G000
2.5
VDD = 4.5 V
Enable Threshold (V)
Enable High Threshold
Enable Low Threshold
2
1.5
1
0.5
−50
0
50
Temperature (°C)
100
150
G017
VDD = 4.5 V
Figure 21. Enable Threshold vs Temperature
10
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8 Detailed Description
8.1 Overview
The UCC2752x family of products represent Texas Instruments’ latest generation of dual-channel, low-side highspeed gate driver devices featuring 5-A source/sink current capability, industry best-in-class switching
characteristics and a host of other features listed in table below all of which combine to provide efficient, robust,
and reliable operation in high-frequency switching power circuits.
Table 1. UCC27527 and UCC27528 Features and Benefits
FEATURE
BENEFIT
Best-in-class 13-ns (typ) propagation delay
Extremely low pulse transmission distortion
1-ns (typ) delay matching between channels
Ease of paralleling outputs for higher (2x) current capability, ease of
driving parallel power switches
Expanded VDD Operating range of 4.5 V to 18 V
Flexibility in system design
Expanded operating temperature range of -40 °C to 140 °C
(See Electrical Characteristics table)
VDD UVLO Protection
Outputs are held Low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down
Outputs held Low when input pins (INx) in floating condition
Safety feature, especially useful in passing abnormal condition tests
during safety certification
Outputs enabled when enable pins (ENx) in floating condition
Pin-to-pin compatibility with UCC2732X family of products from TI, in
designs where pin #1, 8 are in floating condition
CMOS input threshold logic
Enhanced noise immunity, higher threshold level and wider
hysteresis which is a function of VDD supply voltage and ability to
employ RCD delay circuits on input pins.
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply
by VDD pin bias voltage
architecture
8.2 Functional Block Diagram
VDD
VDD
500 kW
ENA
500 kW
1
8
ENB
VDD
INA
OUTA
2
7
465 kW
VDD
VDD
VDD
UVLO
GND
6
3
VDD
OUTB
INB
4
5
465 kW
Figure 22. UCC27528 Block Diagram
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Functional Block Diagram (continued)
INA+
8
VDD
465 kW
5
VDD
6
OUTA
4
OUTB
VDD
VDD
230 kW
INA-
1
VDD
GND
3
UVLO
INB+
VDD
7
VDD
465 kW
230 kW
INB-
2
Figure 23. UCC27527 Block Diagram
8.3 Feature Description
8.3.1 VDD and Undervoltage Lockout
The UCC2752x devices have internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output low,
regardless of the status of the inputs. The UVLO is typically 4.25 V with 350-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops in the VDD bias voltage when the system commences switching and there is a sudden
increase in IDD. The capability to operate at low voltage levels such as below 5 V, along with best in class
switching characteristics, is especially suited for driving emerging GaN power semiconductor devices.
For example, at power-up, the UCC2752x driver-device output remains low until the VDD voltage reaches the
UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with VDD until steadystate VDD is reached. The non-inverting operation in Figure 24 shows that the output remains low until the UVLO
threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 25 shows
that the output remains low until the UVLO threshold is reached, and then the output is out-phase with the input.
With UCC27527 the output turns to high state only if INX+ is high and INX- is low after the UVLO threshold is
reached.
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low
ESR should be connected in parallel and close proximity, in order to help deliver the high-current peaks required
by the load. The parallel combination of capacitors should present a low impedance characteristic for the
expected current levels and switching frequencies in the application.
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VDD Threshold
VDD Threshold
VDD
VDD
EN
EN
IN
IN
OUT
OUT
UDG-11228
UDG-11229
Figure 24. Power-Up Non-Inverting Driver
Figure 25. Power-Up Inverting Driver
8.3.2 Operating Supply Current
The UCC2752x products feature very low quiescent IDD currents. The typical operating supply current in Under
Voltage Lock-Out (UVLO) state and fully-on state (under static and switching conditions) are summarized in
Figure 5, Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC
high or DC low, refer Figure 6) represents lowest quiescent IDD current when all the internal logic circuits of the
device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT
current due to switching and finally any current related to pull-up resistors on the enable pins and inverting input
pins. For example when the inverting Input pins are pulled low additional current is drawn from VDD supply
through the pull-up resistors (refer to Figure 22 though Figure 23). Knowing the operating frequency (fSW) and the
MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as
product of QG and fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load in both channels is provided in Figure 17. The strikingly linear variation and close
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device
attesting to its high-speed characteristics.
8.3.3 Input Stage
The Input pins of UCC2752X gate driver devices are based on what is known as CMOS input threshold logic. In
CMOS input threshold logic the threshold voltage level is a function of the bias voltage on the VDD pin of the
device. The typical high threshold is 55% of VDD supply voltage and the typical low threshold is 38% of VDD
supply voltage. There is built in hysteresis which is typically 17% of VDD supply voltage.
In most applications, the absolute value of the threshold voltage offered by the CMOS logic will be higher (eg.
VINH = 5.5 V if VDD = 10 V) than what is offered by the more common TTL and CMOS compatible input
threshold logic where VINH is typically less than 3 V). The same is true of the input threshold hysteresis
parameter as well. This offers the following benefits:
• Better noise immunity which is desirable in high power systems.
• Ability to accept slow dV/dt input signals, which allows designers to use RCD circuits on the input pin to
program propagation delays in the application, as shown below:
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D
PWM Input
VH
R del
INx
OUTx
VL
C del
PWM Input Signal
VIN
Driver Output
Figure 26. Using RCD Circuits
æ VL - VIN _ H
ö
t del = -RdelCdel ´ In ç
+ 1÷
ç V -V
÷
H
L
è
ø
(1)
The UCC2752x devices feature an important safety feature, whenever any of the input pins is in a floating
condition, the output of the respective channel is held in the low state. This is achieved using VDD pull-up
resistors on all the inverting inputs (INA-, INB- in UCC27527) or GND pull-down resistors on all the non-inverting
input pins (INA, INB in UCC27528 and INA+, INB+ in UCC27527), as shown in the device's block diagrams.
While UCC27528 features one input pin per channel, the UCC27527 features a dual input configuration with two
input pins available to control the output state of each channel. With the UCC27527 device the user has the
flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input pin (INx-). The
state of the output pin is dependent on the bias on both the INx+ and INx- pins (where x = A, B). Once an input
pin has been chosen to drive a channel, the other input pin of that channel (the unused Input pin) must be
properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating
condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that
channel is disabled using the internal pull-up and down resistors for safety purposes. Alternatively, the unused
input pin can effectively be used to implement an enable and disable function, as explained below.
• In order to drive the channel “x” (x = A or B) in a non-inverting configuration, apply the PWM control input
signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (eg. tied to GND) in order to
enable the output of this channel.
– Alternately, the INx- pin can be used to implement the enable and disable function using an external logic
signal. OUTx is disabled when INx- is biased high and OUTx is enabled when INX- is biased low.
• In order to drive the channel “X” (X = A or B) in an inverting configuration, apply the PWM control input signal
to INX- pin. In this case, the unused input pin, INX+, must be biased high (eg. tied to VDD) in order to enable
the output of the channel.
– Alternately, the INX+ pin can be used to implement the enable and disable function using an external logic
signal. OUTX is disabled when INX+ is biased low and OUTX is enabled when INX+ is biased high.
• Finally, it is worth noting that the UCC27527 output pin can be driven into high state ONLY when INx+ pin is
biased high AND INx- input is biased low.
Refer to the input and output logic truth table and typical application diagram for additional clarification.
8.3.4 Enable Function
The enable function is an extremely beneficial feature in gate driver devices especially for certain applications
such as synchronous rectification where the driver outputs can be disabled in light-load conditions to prevent
negative current circulation and to improve light-load efficiency.
UCC27528 device is provided with independent enable pins ENx for exclusive control of each driver channel
operation. The enable pins are based on a non-inverting configuration (active high operation). Thus when ENx
pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are disabled. Like the
input pins, the enable pins are also based on a TTL/CMOS compatible input threshold logic that is independent
of the supply voltage and can be effectively controlled using logic signals from 3.3-V and 5-V microcontrollers.
The UCC2752X devices also feature tight control of the Enable function threshold voltage levels which eases
system design considerations and ensures stable operation across temperature (refer to Figure 10). The ENx
pins are internally pulled up to VDD using pull-up resistors as a result of which the outputs of the device are
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enabled in the default state. Hence the ENx pins can be left floating or Not Connected (N/C) for standard
operation, where the enable feature is not needed. Essentially, this allows the UCC27528 device to be pin-to-pin
compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins 1, 8 are N/C pins. If the
channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity,
ENA and ENB should be connected and driven together.
The UCC27527 device does not feature dedicated enable pins. However, as mentioned earlier, an
enable/disable function can be easily implemented in UCC27527 using the unused input pin. When INx+ is
pulled-down to GND or INx- is pulled-down to VDD, the output is disabled. Thus INx+ pin can be used like an
enable pin that is based on active high logic, while INx- can be used like an enable pin that is based on active
low logic. It is important to note that while the ENA, ENB pins in the UCC27528 are allowed to be in floating
condition during standard operation and the outputs will be enabled, the INx+, INx- pins in UCC27527 are not
allowed to be floating since this will disable the outputs.
8.3.5 Output Stage
The UCC2752x device output stage features a unique architecture on the pull-up structure which delivers the
highest peak Source current when it is most needed during the Miller plateau region of the power switch turn-on
transition (when the power switch drain/collector voltage experiences dV/dt). The output stage pull-up structure
features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the N-Channel
MOSFET is to provide a brief boost in the peak sourcing current enabling fast turn-on. This is accomplished by
briefly turning-on on the N-Channel MOSFET during a narrow instant when the output is changing state from Low
to High.
VCC
ROH
RNMOS, Pull Up
Input Signal
Anti ShootThrough
Circuitry
Gate
Voltage
Boost
OUT
Narrow Pulse at
each Turn On
R OL
Figure 27. UCC2752x Gate Driver Output Structure
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the onresistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned-on only for a narrow instant when output changes state from low to high. Thus it should
be noted that effective resistance of UCC2752x pull-up stage during turn-on instant is much lower than what is
represented by ROH parameter.
The pull-down structure in UCC2752x is simply composed of a N-Channel MOSFET. The ROL parameter (see
Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pull-down
stage in the device. In UCC2752x, the effective resistance of the hybrid pull-up structure during turn-on is
estimated to be approximately 1.5 x ROL, estimated based on design considerations.
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Each output stage in UCC2752x is capable of supplying 5-A peak source and 5-A peak sink current pulses. The
output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS output stage
which delivers very low drop-out. The presence of the MOSFET body diodes also offers low impedance to
switching overshoots and undershoots. This means that in many cases, external Schottky diode clamps may be
eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either
damage to the device or logic malfunction.
The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive gate transformer applications
where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven
complementary to each other. This is due to the extremely low drop-out offered by the MOS output stage of
these devices, both during high (VOH) and low (VOL) states along with the low impedance of the driver output
stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance. The low
propagation delays also ensure accurate reset for high-frequency applications.
For applications that have zero voltage switching during power MOSFET turn-on or turn-off interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.
8.3.6 Low Propagation Delays and Tightly Matched Outputs
The UCC2752x driver devices offer a very low propagation delay of 17-ns (typical) between input and output
which offers lowest level of pulse transmission distortion available in the industry for high-frequency switching
applications. For example in synchronous rectifier applications, the SR MOSFETs can be driven with very low
distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver devices also
feature an extremely accurate, 1-ns (typ) matched internal propagation delays between the two channels which
is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a
pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both
channels are driven by a common control signal from the PFC controller device. In this case the 1-ns delay
matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turn-on
delay difference.
Since the CMOS input threshold of UCC27528 allows the use of slow dV/dt input signals, when paralleling
outputs for obtaining higher peak output current capability, it is recommended to connect external gate resistors
directly to the output pins to avoid shoot-through current conduction between the 2 channels, as shown in
Figure 28. While the two channels are inherently very well matched (4-ns Max propagation delay), it should be
noted that there may be differences in the input threshold voltage level between the two channels or differences
in the input signals which can cause the delay between the two outputs.
VDD
VDD
500 kW
ENA
500 kW
1
8
ISHOOT-THROUGH
VDD
Slow Input Signal
INA
2
VIN_H
(Channel B)
7
465 kW
VIN_H
(Channel A)
VDD
INB
OUTA
VDD
UVLO
GND
ENB
VDD
6
3
VDD
4
5
OUTB
465 kW
Figure 28. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling
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8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See the VDD and Undervoltage Lockout section for
information on UVLO operation mode. In the normal mode the output state is dependent on states of the IN+ and
IN– pins. Table 2 and Table 3 lists the output states for different input pin combinations.
Table 2. Device Logic Table (UCC27528)
UCC27528
ENA
ENB
INA
INB
OUTA
H
H
L
L
L
L
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
L
Any
Any
L
L
Any
Any
x (1)
x (1)
L
L
(1)
(1)
L
L
L
L
x (1)
x (1)
L
H
L
H
x (1)
x (1)
H
L
H
L
(1)
(1)
H
H
H
H
x
x
(1)
OUTB
x
x
Floating condition
Table 3. Device Logic Table (UCC27527)
INx+ (x = A or B)
INx- (x = A or B)
OUTx+ (x = A or B)
L
L
L
L
H
L
H
L
H
H
H
L
(1)
Any
L
Any
x (1)
L
x
(1)
Floating condition
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver
device can be employed between the PWM output of control devices and the gates of the power semiconductor
devices. Further, gate driver devices are indispensable when sometimes it is just not feasible to have the PWM
controller device directly drive the gates of the switching devices. With advent of digital power, this situation will
be often encountered since the PWM signal from the digital controller is often a 3.3-V logic signal which is not
capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the 3.3-V signal to
the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter
follower configurations, prove inadequate with digital power since they lack level-shifting capability. Gate driver
devices effectively combine both the level-shifting and buffer drive functions. Gate driver devices also find other
needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver
physically close to the power switch, driving gate drive transformers and controlling floating power device gates,
reducing power dissipation and thermal stress in controller devices by moving gate charge power losses into
itself. In summary Gate-driver devices are an extremely important component in switching power combining
benefits of high performance, low cost, component count, board-space reduction and simplified system design.
9.2 Typical Application
ENB
UCC2752x
ENA
1
ENA
INA
2
INA
3
GND
4
INB
ENB
8
OUTA
7
VDD
6
OUTB
5
V+
GND
INB
GND
GND
UDG-11225
Figure 29. UCC2752x Typical Application Diagram (X = 8)
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Typical Application (continued)
UCC27527
INA-
1
INA-
INA+
8
2
INB-
INB+
7
3
GND
OUTA
6
INB+
V+
GND
4
GND
OUTB
VDD
5
GND
Figure 30. UCC27527 Typical Application Diagram
Channel A in Inverting and Channel B in Non-Inverting Configuration,
(Enable Function Not Used)
OUTA is
ENABLED when
ENA is HIGH
UCC27527
INA-
1
INA-
INA+
8
ENA
ENB
2
INB-
INB+
7
INB+
3
GND
OUTA
6
4
OUTB
VDD
5
OUTB is
ENABLED when
ENB is LOW
V+
GND
GND
GND
Figure 31. UCC27527 Typical Application Diagram
Channel A In Inverting And Channel B In Non-Inverting Configuration,
(Enable Function Implemented)
9.2.1 Design Requirements
When selecting the proper gate driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are Input-to-Output
Logic, Enable and Disable function, VDD, Propagation delay, and power dissipation.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
9.2.2.1 Input-to-Output Logic
The design should specify which type of input-to-output configuration should be used. UCC27528 can only
provide dual non-inverting input-to-output with enable control. If turning on the power MOSFET or IGBT when the
input signal is in high state is preferred, then the non-inverting configuration must be selected. If turning off the
power MOSFET or IGBT when the input signal is in high state is preferred, the inverting configuration must be
chosen. UCC27527 has dual configuration channel. Each Channel of UCC27527 device can be configured in
either an inverting or non-inverting input-to-output configuration using the INx– or INx+ pins respectively like in
Figure 30 and Figure 31. To configure the channel for use in inverting mode, tie the INx+ pin to VDD and apply
the input signal to the INx– pin. For the non-inverting configuration, tie the INx– pin to GND and apply the input
signal to the INx+ pin.
9.2.2.2 Enable and Disable Function
Certain applications demand independent control of the output state of the driver. UCC278525 device offers two
independent enable pins ENx for exclusive control of each driver channels as listed in Table 2. The UCC27527
device does not feature dedicated enable pins. However, as mentioned earlier, an enable/disable function can be
easily implemented in UCC27527 using the unused input pin. When INx+ is pulled-down to GND or INx- is
pulled-down to VDD, the output is disabled. Thus INx+ pin can be used like an enable pin that is based on active
high logic, while INx- can be used like an enable pin that is based on active low logic. It is important to note that
while the ENA, ENB pins in the UCC27528 are allowed to be in floating condition during standard operation and
the outputs will be enabled, the INx+, INx- pins in UCC27527 are not allowed to be floating since this will disable
the outputs.
9.2.2.3 VDD Bias Supply Voltage
The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Recommended Operating Conditions table. However, different power switches demand different voltage levels to
be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate
voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the
VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC2752X
device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10V,
12 V), IGBTs (VGE = 15 V, 18 V), and wide-bandgap power semiconductors (such as GaN, certain types of
which allow no higher than 6 V to be applied to the gate pins).
9.2.2.4 Propagation Delay
The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC2752X device features fast 17-ns
(typical) propagation delays which ensures very little pulse distortion and allows operation at very highfrequencies. See the Switching Characteristics table for the propagation and switching characteristics of the
UCC2752X device. For certain application which needed programmable propagation delay, The UCC2752X
device can accept slow dv/dt input signals which allows designers to use RCD circuits on the input pin to
program propagation as in Figure 26.
9.2.2.5 Drive Current and Power Dissipation
The UCC27527 and UCC27528 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a
period of several hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON
quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This
repeats at the operating frequency of the power device. The power dissipated in the gate driver device package
depends on the following factors:
• Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close
to input bias supply voltage VDD due to low VOH drop-out)
• Switching frequency
• Use of external gate resistors
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Typical Application (continued)
Since UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the
output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be
negligible.
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
1
EG = CLOAD VDD2
2
where
•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver
(2)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by the following:
PG = CLOAD VDD2 fSW
where
•
fSW is the switching frequency
(3)
With VDD = 12 V, CLOAD = 10 nF and ƒSW = 300 kHz the power loss can be calculated as:
PG = 10nF ´ 12 V 2 ´ 300kHz = 0.432 W
(4)
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must
be dissipated when charging a capacitor. This is done by using the equivalence Qg = CLOADVDD to provide the
following equation for power:
PG = CLOAD VDD2 fSW = Qg VDD fSW
(5)
Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on
each output, the gate charge related power loss can be calculated as:
PG = 2 x 60nC ´ 12 V ´ 300kHz = 0.432 W
(6)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET is being turned-on or off.
Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is
dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed
between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the
use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher
resistance component). Based on this simplified analysis, the driver power dissipation during switching is
calculated as follows:
æ
ö
ROFF
RON
PSW = 0.5 ´ QG ´ VDD ´ fSW ´ ç
+
÷
è ROFF + RGATE RON + RGATE ø
where
•
•
ROFF = ROL
RON (effective resistance of pull-up structure) = 1.5 x ROL
(7)
In addition to the above gate charge related power dissipation, additional dissipation in the driver is related to the
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pull-up and pull-down resistors), enable, and UVLO sections. Referring to the Figure 6 it can be
seen that the quiescent current is less than 0.6 mA even in the highest case. The quiescent power dissipation
can be simply calculated as:
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Typical Application (continued)
PQ = IDD VDD
(8)
Assuming , IDD = 6 mA, the power loss is:
PQ = 0.6 mA ´ 12 V = 7.2mW
(9)
Clearly, this is insignificant compared to gate charge related power dissipation calculated earlier.
With a 12-V supply, the bias current can be estimated as follows, with an additional 0.6-mA overhead for the
quiescent consumption:
P
0.432 W
IDD ~ G =
= 0.036 A
VDD
12 V
(10)
9.2.3 Application Curves
VDD = 5 V, Load = 2 RJK0453DPB
Figure 32. Typical Turnon Waveform
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Figure 33. Typical Turnoff Waveform
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10 Power Supply Recommendations
The bias supply voltage range for which the UCC2752X device is rated to operate is from 4.5 V to 18 V. The
lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD
pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VON
supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of
this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress
rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the
VDD pin is 18 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD_H.
Therefore, ensuring that, while operating at or near the 4.2V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below
the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements.
Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above
the VON threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied
through the VDD pin. Although this fact is well known, recognizing that the charge for source current pulses
delivered by the OUTA/B pin is also supplied through the same VDD pin is important. As a result, every time a
current is sourced out of the output pins, a corresponding current pulse is delivered into the device through the
VDD pin. Thus ensuring that local bypass capacitors are provided between the VDD and GND pins and located
as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount
capacitor is a must. TI recommends having 2 capacitors; a 100-nF ceramic surface-mount capacitor which can
be nudged very close to the pins of the device and another surface-mount capacitor of few microfarads added in
parallel.
11 Layout
11.1 Layout Guidelines
Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device
operation and design robustness. The UCC27527 and UCC27528 family of gate drivers incorporates short
propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and
fall times at the gate of power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the
peak current capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout
guidelines are strongly recommended when designing with these high-speed drivers.
• Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the Output pins and the Gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD
during turn-on of power MOSFET. The use of low inductance SMD components such as chip resistors and
chip capacitors is highly recommended.
• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at 2 instances – during turn-on and turn-off transients, which will induce significant
voltage transients on the output pin of the driver device and Gate of the power MOSFET.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power MOSFET, ground of PWM
controller etc at one, single point. The connected paths should be as short as possible to reduce inductance
and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
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Layout Guidelines (continued)
•
to noise shielding, the ground plane can help in power dissipation as well
In noisy environments, it may be necessary to tie inputs of an unused channel of UCC27527 to VDD (in case
of INx+) or GND (in case of INX-) using short traces in order to ensure that the output is enabled and to
prevent noise from causing malfunction in the output.
11.2 Layout Example
Figure 34. Layout Example for UCC27528
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Layout Example (continued)
Figure 35. Layout Example for UCC27527
(Channel A in Inverting and Channel B in Non-Inverting Configuration)
11.3 Thermal Considerations
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a gate driver device to be useful over a particular temperature
range the package must allow for the efficient removal of the heat produced while keeping the junction
temperature within rated limits. The UCC27527 and UCC27528 family of drivers is available in two different
packages to cover a range of application requirements. The thermal metrics for each of these packages are
summarized in the Thermal Information section of the datasheet. For detailed information regarding the thermal
information table, please refer to Application Note from Texas Instruments entitled IC Package Thermal Metrics,
SPRA953).
Among the different package options available in the UCC2752x family, of particular mention is the DSD package
when it comes to power dissipation capability. The 3-mm x 3-mm WSON (DSD) package offer a means of
removing the heat from the semiconductor junction through the exposed thermal pad at the base of the package.
This pad is soldered to the copper on the printed circuit board directly underneath the device package, reducing
the thermal resistance to a very low value. This allows a significant improvement in heat-sinking over that
available in the D package. The printed circuit board must be designed with thermal lands and thermal vias to
complete the heat removal subsystem. Note that the exposed pads in the WSON-8 package is not directly
connected to any leads of the package. However, it is electrically and thermally connected to the substrate of the
device which is the ground of the device. It is recommended to externally connect the exposed pads to GND in
PCB layout for better EMI immunity.
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC27527
Click here
Click here
Click here
Click here
Click here
UCC27528
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC27527DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27527
UCC27527DSDT
ACTIVE
SON
DSD
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27527
UCC27528D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27528
UCC27528DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27528
UCC27528DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27528
UCC27528DSDT
ACTIVE
SON
DSD
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27528
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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