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UCC27528QDRQ1

UCC27528QDRQ1

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC8_150MIL

  • 描述:

    IC GATE DRVR LOW-SIDE 8SOIC

  • 数据手册
  • 价格&库存
UCC27528QDRQ1 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 UCC27528-Q1 Dual 5-A High-Speed Low-Side Gate Driver Based on CMOS Input Threshold Logic 1 Features 2 Applications • • • • • • • • • • • 1 • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Device Temperature Grade 1 Industry-Standard Pin Out Two Independent Gate-Drive Channels 5-A Peak Source and Sink Drive Current CMOS Input Logic Threshold (Function of Supply Voltage on VDD Pins) Hysteretic Logic Thresholds for High Noise Immunity Independent Enable Function for Each Output Inputs and Enable Pin Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage 4.5-V to 18-V Single Supply Range Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down) Fast Propagation Delays (17-ns Typical) Fast Rise and Fall Times (7-ns and 6-ns Typical) 1-ns Typical Delay Matching Between 2 Channels Outputs Held in Low When Inputs Floating SOIC-8 Package Operating Temperature Range of –40°C to 140°C –5-V Negative Voltage Handling Capability on Input Pins Automotive Switch-Mode Power Supplies DC-to-DC Converters Motor Control, Solar Power Gate Drive for Emerging Wideband Gap Power Devices Such as GaN 3 Description The UCC27528-Q1 device is a dual-channel, highspeed, low-side gate driver capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27528-Q1 device can deliver highpeak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay of 17 ns (typical). In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The enable pins are based on TTL and CMOS compatible logic, independent of the VDD supply voltage. Device Information(1) PART NUMBER UCC27528-Q1 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Dual Non-Inverting Inputs UCC27528-Q1 ENA 1 8 ENB INA 2 7 OUTA GND 3 6 VDD INB 4 5 OUTB 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 11 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application .................................................. 16 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 21 11.3 Thermal Considerations ........................................ 21 12 Device and Documentation Support ................. 21 12.1 Trademarks ........................................................... 21 12.2 Electrostatic Discharge Caution ............................ 21 12.3 Glossary ................................................................ 21 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Original (December 2015) to Revision A • 2 Page Changed device status from Product Preview to Production Data ....................................................................................... 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 5 Description (continued) The UCC27528-Q1 device is a dual noninverting driver. Internal pullup and pulldown resistors on the input pins of the UCC27528-Q1 device ensure that outputs are held low when input pins are in floating condition. The UCC27528-Q1 device features enable pins (ENA and ENB) for better control of the operation of the driver applications. The pins are internally pulled up to the VDD supply for active-high logic and can be left open for standard operation. 6 Pin Configuration and Functions D Package 8-Pin SOIC Top View ENA 1 88 ENB INA 2 77 OUTA GND 3 66 VDD INB 4 55 OUTB Pin Functions PIN NO. NAME I/O DESCRIPTION 1 ENA I Enable input for Channel A: ENA biased low Disables Channel A output regardless of INA state, ENA biased high or floating Enables Channel A output, ENA allowed to float. 2 INA I Input to Channel A: Non-Inverting Input in UCC27528-Q1, OUTA held low if INA is unbiased or floating. 3 GND — 4 INB I Input to Channel B: Non-Inverting Input in UCC27528-Q1, OUTB held low if INB is unbiased or floating. 5 OUTB O Output of Channel B Ground: All signals referenced to this pin. 6 VDD I Bias supply input 7 OUTA O Output of Channel A 8 ENB I Enable input for Channel B: ENB biased low Disables Channel B output regardless of INB state, ENB biased high or floating Enables Channel B output, ENB allowed to float. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 3 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) Supply voltage range INA, INB, voltage VDD (3) ENA, ENB voltage (3) DC OUTA, OUTB voltage Repetitive pulse < 200 ns (4) Output continuous source and sink current IOUT_DC Output pulsed source and sink current (0.5 µs) IOUT_pulsed Operating virtual junction temperature, TJ Lead temperature (2) (3) (4) MAX UNIT 20 V –6.5 20 V –0.3 20 V –0.3 VDD + 0.3 –2 VDD + 0.3 –40 A 5 A 150 °C 300 Reflow 260 –65 V 0.3 Soldering, 10 s Storage temperature, Tstg (1) MIN –0.3 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages. The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin. Values are verified by characterization on bench. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±4000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD Supply voltage Input voltage INA, INB Enable voltage ENA and ENB Operating junction temperature MIN NOM MAX 4.5 12 18 UNIT V –5 18 V 0 18 V –40 140 °C 7.4 Thermal Information THERMAL METRIC (1) D 8 PINS RθJA Junction-to-ambient thermal resistance 128 RθJC(top) Junction-to-case (top) thermal resistance 77.7 RθJB Junction-to-board thermal resistance 68.5 ψJT Junction-to-top characterization parameter 20.7 ψJB Junction-to-board characterization parameter 68 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 7.5 Electrical Characteristics VDD = 12 V, TA = TJ = –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,) PARAMETER TEST CONDITIONS MIN TYP MAX VDD = 3.4 V, INA = VDD, INB = VDD 55 125 225 VDD = 3.4 V, INA = GND, INB = GND 25 125 225 TJ = 25°C 3.91 4.2 4.5 TJ = –40°C to 140°C UNIT BIAS CURRENTS IDD(off) Startup current μA UNDERVOLTAGE LOCKOUT (UVLO) VON Supply start threshold 3.75 4.2 4.65 VOFF Minimum operating voltage after supply start 3.6 3.9 4.4 VDD_H Supply voltage hysteresis 0.2 0.3 0.5 55 70 V INPUTS (INA, INB) VIN_H Input signal high threshold Output high for non-inverting input pins Output low for inverting input pins VIN_L Input signal low threshold Output low for non-inverting input pins Output high for inverting input pins VIN_HYS Input hysteresis 30 %VDD 38 17 ENABLE (ENA, ENB) VEN_H Enable signal high threshold Output enabled 1.7 1.9 2.1 VEN_L Enable signal low threshold Output disabled 0.95 1.10 1.25 VEN_HYS Enable hysteresis 0.7 0.8 1.1 V OUTPUTS (OUTA, OUTB) ISNK/SRC Sink and source peak current (1) CLOAD = 0.22 µF, fSW = 1 kHz VDD–VOH High output voltage IOUT = –10 mA 0.075 VOL Low output voltage IOUT = 10 mA 0.01 ROH Output pullup resistance (2) IOUT = –10 mA 2.5 5 7.5 Ω ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω (1) (2) ±5 A V Ensured by design. ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC27528-Q1 output stage. 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR Rise time CLOAD = 1.8 nF, VDD = 10 V 7 ns tF Fall time CLOAD = 1.8 nF, VDD = 10 V 6 ns tM Delay matching between 2 channels INA = INB, OUTA and OUTB at 50% transition point, VDD = 10 V 1 tPW Minimum input pulse width that changes the output state VDD = 10 V tD1, tD2 Input to output propagation delay, See Figure 2. CLOAD = 1.8 nF, 7-V input pulse, VDD = 10 V 6 17 26 ns tD3, tD4 EN to output propagation delay, See Figure 1 . CLOAD = 1.8 nF, 7-V enable pulse, VDD = 10 V 6 13 23 ns 4 15 ns Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 ns 5 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com High Input Low High Enable Low 90% Output 10% tD3 tD4 UDG-11217 Figure 1. Enable Function (Non-Inverting Input Driver Operation) High Input Low High Enable Low 90% Output 10% tD1 tD2 UDG-11219 Figure 2. Non-Inverting Input Driver Operation 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 7.7 Typical Characteristics 10 0.17 IN = Low/High Supply Current (mA) Startup Current (mA) 0.16 0.15 0.14 0.13 0.12 9 8 7 0.11 0.10 −50 0 50 Temperature (°C) 100 6 −50 150 0 G001 VDD = 12 V VDD = 3.4 V 50 Temperature (°C) 100 150 G001 CLOAD = 500 pF Both Channels Switching fSW = 500 kHz Figure 3. Startup Current vs Temperature Figure 4. Operating Supply Current vs Temperature (Outputs Switching) 4.8 INA/INB = VDD INA/INB = GND UVLO Rising UVLO Falling 0.7 4.6 UVLO Threshold (V) Operating Supply Current (mA) 0.8 0.6 0.5 0.4 4.4 4.2 4 0.3 −50 0 50 Temperature (°C) 100 3.8 −50 150 0 G001 50 Temperature (°C) 100 150 G001 VDD = 12 V Figure 5. Supply Current vs Temperature (Outputs In DC On/Off Condition) Figure 6. UVLO Threshold vs Temperature 7.6 EN High Threshold EN Low Threshold Enable Threshold (V) Input Threshold (V) 7 2.2 Input High Threshold Input Low Threshold 6.4 5.8 5.2 1.8 1.4 4.6 4 −50 0 50 Temperature (°C) 100 150 1 −50 0 G001 VDD = 12 V 50 Temperature (°C) 100 150 G001 VDD = 12 V Figure 7. Input Threshold vs Temperature Figure 8. Enable Threshold vs Temperature Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 7 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Typical Characteristics (continued) 7 1 RoL Output Pulldown Resistance (Ω) Output Pullup Resistance (Ω) RoH 6 5 4 3 −50 0 VDD = 12 V 50 Temperature (°C) 100 0.6 0.4 0.2 −50 150 IOUT = 10 mA VDD = 12 V 7 7 Fall Time (ns) 8 6 100 150 G001 IOUT = 10 mA 6 5 4 −50 0 VDD = 10 V 50 Temperature (°C) 100 4 −50 150 0 G001 CLOAD = 1.8 nF VDD = 10 V Figure 11. Rise Time vs Temperature 50 Temperature (°C) 100 150 G001 CLOAD = 1.8 nF Figure 12. Fall Time vs Temperature 20 16 Turn−On Turn_Off Enable Propagation Delay (ns) Input Propagation Delay (ns) 50 Temperature (°C) Figure 10. Output Pulldown Resistance vs Temperature 8 5 18 16 14 12 −50 0 50 Temperature (°C) 100 150 Turn−On Turn_Off 14 12 10 8 −50 0 G001 VDD = 10 V 50 Temperature (°C) 100 150 G001 VDD = 10 V Figure 13. Input To Output Propagation Delay vs Temperature 8 0 G001 Figure 9. Output Pullup Resistance vs Temperature Rise Time (ns) 0.8 Figure 14. En To Output Propagation Delay vs Temperature Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 Typical Characteristics (continued) 30 VDD = 4.5 V VDD = 12 V VDD = 15 V 60 50 40 30 20 22 18 14 10 10 0 0 6 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) G000 Both Channels Switching CLOAD = 1.8 nF 8 12 Supply Voltage (V) 16 20 G000 Figure 16. Propagation Delays vs Supply Voltage 18 10 8 Rise time (ns) Rise time (ns) 4 CLOAD = 1.8 nF Figure 15. Operating Supply Current vs Frequency 12 6 Input to Output On Delay Input to Output Off Delay EN to Output On Delay EN to Output Off Delay 26 Propagation Delays (ns) Operating Supply Current (mA) 70 4 8 12 Supply Voltage (V) 16 6 4 20 4 8 12 Supply Voltage (V) G000 CLOAD = 1.8 nF 16 20 G000 CLOAD = 1.8 nF Figure 17. Rise Time vs Supply Voltage Figure 18. Fall Time vs Supply Voltage 2.5 VDD = 4.5 V Enable Threshold (V) Enable High Threshold Enable Low Threshold 2 1.5 1 0.5 −50 0 50 Temperature (°C) 100 150 G017 VDD = 4.5 V Figure 19. Enable Threshold vs Temperature Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 9 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8 Detailed Description 8.1 Overview The UCC27528-Q1 device represents Texas Instruments’ latest generation of dual-channel, low-side high-speed gate driver devices featuring 5-A source- and sink current capability, industry best-in-class switching characteristics, and many other features listed in Table 1 all of which combine to provide efficient, robust, and reliable operation in high-frequency switching power circuits. Table 1. UCC27528-Q1 Features and Benefits FEATURE BENEFIT Best-in-class 13-ns (typical) propagation delay Extremely low pulse-transmission distortion 1-ns (typical) delay matching between channels Ease of paralleling outputs for higher (2×) current capability, ease of driving parallel power switches Expanded VDD operating range of 4.5 V to 18 V Expanded operating temperature range of –40 °C to 140 °C (See the Electrical Characteristics table) Flexibility in system design VDD UVLO protection Outputs are held low in UVLO condition, which ensures predictable, glitch-free operation at power up and power down Outputs held low when the input pins (INx) are in floating condition Feature which is specifically useful in passing abnormal condition tests during certification Outputs enabled when the enable pins (ENx) are in floating condition Pin-to-pin compatibility with the UCC2732x family of device from TI, in designs where pin 1 and pin 8 are in the floating condition CMOS input threshold logic Enhanced noise immunity, higher threshold leve,l and wider hysteresis which is a function of the VDD supply voltage and ability to employ RCD delay circuits on input pins. The input and enable pins are able to handle voltage levels not restricted by VDD pin bias voltage System simplification, specifically related to auxiliary bias supply architecture 8.2 Functional Block Diagram VDD VDD 500 kΩ 500 kΩ ENA ENB 1 8 VDD INA OUTA 2 7 465 kΩ VDD VDD GND VDD UVLO 6 3 VDD OUTB INB 4 5 465 kΩ 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 8.3 Feature Description 8.3.1 VDD and Undervoltage Lockout The UCC27528-Q1 device has internal undervoltage-lockout (UVLO) protection feature on the VDD pin supplycircuit blocks. When the VDD supply is rising and the level is still below UVLO threshold, the circuit (as shown in the Functional Block Diagram) holds the output low, regardless of the status of the inputs. The UVLO threshold is 4.25 V (typical) with 350-mV hysteresis (typical). This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when droops in the VDD bias voltage occur when the system commences switching and a sudden increase in the IDD current occurs. The ability to operate at lowvoltage levels, such as below 5 V, along with best-in-class switching characteristics, is well suited for driving emerging GaN-power semiconductor devices. For example, at power-up, the UCC27528-Q1 driver device output remains low until the VDD voltage reaches the UVLO threshold if the enable pin is active or floating. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. The non-inverting operation in Figure 20 shows that the output remains low until the UVLO threshold is reached. The output is then in-phase with the input. Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surfacemount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate-driver device. In addition, to help deliver the high-current peaks required by the load, a larger capacitor (such as a 1-μF capacitor) with relatively low ESR should be connected in parallel and close proximity. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application. VDD Threshold VDD EN IN OUT UDG-11228 Figure 20. Power-Up Non-Inverting Driver 8.3.2 Operating Supply Current The UCC27528-Q1 device features very low quiescent IDD currents. Figure 3, Figure 4, and Figure 5 list the typical operating supply current in the UVLO state and fully-on state (under static and switching conditions). The IDD current that is present when the device is fully on and the outputs are in a static state (DC high or DC low, see Figure 4) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current from switching, and any current related to pullup resistors on the enable pins and inverting input pins. Figure 15 shows a complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages under 1.8-nF switching load in both channels. The strikingly linear variation and close correlation with the theoretical value of the average IOUT indicates negligible shoot-through inside the gate-driver device attesting to the high-speed characteristics. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 11 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.3.3 Input Stage The input pins of UCC27528-Q1 gate driver device are based on CMOS input threshold logic. In CMOS input threshold logic the threshold voltage level is a function of the bias voltage on the VDD pin of the device. The typical high threshold is 55% of the VDD supply voltage and the typical low threshold is 38% of the VDD supply voltage. Built-in hysteresis is available which is typically 17% of the VDD supply voltage. In most applications, the absolute value of the threshold voltage offered by the CMOS logic is higher (for example, VIN_H = 5.5 V if VDD = 10 V) than what is offered by the more common TTL and CMOS-compatible input threshold logic where VIN_H is typically less than 3 V. The same is true of the input-threshold hysteresis parameter as well. This feature offers the following benefits: • Better noise immunity which is desirable in high power systems. • Ability to accept slow dV/dt input signals, which allows designers to use RCD circuits on the input pin to program propagation delays in the application, as shown in Figure 21. D PWM Input Rdel VH INx OUTx VL PWM Input Signal Cdel VIN Driver Output Figure 21. Using RCD Circuits æ VL - VIN _ H ö t del = -RdelCdel ´ In ç + 1÷ ç V -V ÷ H L è ø (1) The UCC27528-Q1 device features an important feature, whenever any of the input pins is in a floating condition, the output of the respective channel is held in the low state. Holding the respective channel in the low state is achieved by using GND pulldown resistors on all the non-inverting input pins (INA, INB), as shown in the Functional Block Diagram. • To drive channel x (x = A or B) in a non-inverting configuration, apply the PWM control input signal to one of the IN pins. In this case, the unused IN pin must be biased low (for example, tied to GND) to enable the output of this channel. – Alternately, the unused IN pin can be used to implement the enable and disable function using an external logic signal. The output pin is disabled when the unused IN pin is biased high and the OUT pin is enabled when the unused IN pin is biased low. See Table 2 and Figure 24 for additional clarification. 8.3.4 Enable Function The enable function is an extremely beneficial feature in gate driver devices, especially for certain applications such as synchronous rectification where the driver outputs can be disabled in light-load conditions to prevent negative current circulation and to improve light-load efficiency. The UCC27528-Q1 device has independent enable pins, ENx, for exclusive control of the operation of each driver channel. The enable pins are based on a non-inverting configuration (active-high operation). Therefore, when the ENx pins are driven high the drivers are enabled and when ENx pins are driven low and the drivers are disabled. Similar to the input pins, the enable pins are also based on a TTL and CMOS-compatible input threshold logic that is independent of the supply voltage and can be effectively controlled using logic signals from 3.3-V and 5-V microcontrollers. The UCC27528-Q1 device also features tight control of the enable-function threshold voltage levels which eases system design considerations and ensures stable operation across temperature (see Figure 8). The ENx pins are internally pulled up to the VDD supply using pullup resistors as a result of which the outputs of the device are enabled in the default state. Therefore, the ENx pins can be left 12 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 floating or not connected (NC) for standard operation in which case the enable feature is not needed. This ability allows the UCC27528-Q1 device to be pin-to-pin compatible with TI’s previous-generation drivers, the UCC27323, UCC273234, and UCC273235 device, where pin 1 and pin 8 are NC pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity, the ENA and ENB pins should be connected and driven together. 8.3.5 Output Stage The UCC27528-Q1 output stage features a unique architecture on the pullup structure which delivers the highest-peak source current when it is most needed during the Miller plateau region of the power-switch turn-on transition (when the power switch drain and collector voltage experiences dV/dt). The output-stage pullup structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The N-Channel MOSFET provides a brief boost in the peak sourcing current which enables fast turn-on. This boost is accomplished by briefly turning on the N-Channel MOSFET during a short time frame when the output is changing state from low to high. VCC ROH RNMOS, Pullup Input Signal Gate Voltage Boost Anti ShootThrough Circuitry OUT Narrow pulse at each turn on ROL Figure 22. UCC27528-Q1 Gate Driver Output Structure The ROH parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the on-resistance of the P-Channel device only because the N-Channel device is held in the off state in DC condition and is turned on only for a short time frame when the output changes state from low to high. Therefore, the effective resistance of UCC27528-Q1 pullup stage during turn-on instant is much lower than what is represented by ROH parameter. The pulldown structure in the UCC27528-Q1 device is simply composed of a N-Channel MOSFET. The ROL parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of the impedance of the pulldown stage in the device. In the UCC27528-Q1 device, the effective resistance of the hybrid pullup structure during turnon is estimated on design considerations as approximately 1.5 × ROL. Each output stage in the UCC27528-Q1 device is capable of supplying 5-A peak source and 5-A peak sink current pulses. The output voltage swings between VDD and GND, providing rail-to-rail operation because of the MOS output stage which delivers very-low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases, external Schottky diode clamps can be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction. The UCC27528-Q1 device is particularly suited for dual-polarity, symmetrical drive-gate transformer applications where the primary winding of transformer driven by the OUTA and OUTB pins, with the inputs INA and INB driven complementary to each other. The device is well suited for these applications because of the extremely low dropout offered by the MOS output stage of the device, both during high (VOH) and low (VOL) states along with the low impedance of the driver output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance. The low propagation delays also ensure accurate reset for high-frequency applications. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 13 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com For applications that have zero voltage switching during power MOSFET turn-on or turn-off interval, the driver supplies high-peak current for fast switching even though the miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before power MOSFET is switched on. 8.3.6 Low Propagation Delays and Tightly Matched Outputs The UCC27528-Q1 driver devices offer a very low propagation delay of 17-ns (typical) between input and output which offers lowest level of pulse transmission distortion available in the industry for high-frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs can be driven with very low distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver devices also feature an extremely accurate, 1-ns (typ) matched internal propagation delays between the two channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1-ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turn-on delay difference. Since the CMOS input threshold of UCC27528-Q1 allows the use of slow dV/dt input signals, when paralleling outputs for obtaining higher peak output current capability, it is recommended to connect external gate resistors directly to the output pins to avoid shoot-through current conduction between the 2 channels, as shown in Figure 23. While the two channels are inherently very well matched (4-ns Max propagation delay), it should be noted that there may be differences in the input threshold voltage level between the two channels or differences in the input signals which can cause the delay between the two outputs. VDD VDD 500 kΩ 500 kΩ ENB ENA 1 8 ISHOOT-THROUGH VDD OUTA INA Slow Input Signal 2 VIN_H (Channel B) 7 465 kΩ VIN_H (Channel A) VDD VDD VDD UVLO GND 6 3 VDD OUTB INB 4 5 465 kΩ Figure 23. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling 14 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 8.4 Device Functional Modes The device operates in normal mode and UVLO mode. See the VDD and Undervoltage Lockout section for information on the UVLO operation mode. In the normal mode the output state is dependent on the state of the IN pins. Table 2 lists the output states for different input-pin combinations. Table 2. Device Logic Table ENA ENB INA INB OUTA H H H H H H H H L L Any Any x (1) x (1) (1) L L L L L H L H H L H L H H H H Any Any L L x (1) x (1) L L L L L L (1) L H L H x (1) x (1) H L H L x (1) x (1) H H H H x (1) x OUTB Floating condition Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 15 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information High-current gate-driver devices are required in switching power applications for a variety of reasons. To implement fast switching in power devices and reduce associated switching power losses, a powerful gate-driver device can be employed between the PWM output of control devices and the gates of the power semiconductor devices. Furthermore, gate driver devices are indispensable when having the PWM-controller device directly drive the gates of the switching devices is not feasible. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is typically a 3.3-V logic signal which is not capable of effectively turning on a power switch. A level shifting circuitry is required to boost the 3.3-V signal to the gatedrive voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar transistors in totem-pole arrangement are emitter follower configurations. These circuits prove inadequate with digital power because they lack level-shifting capability. Gate driver devices effectively combine both the level-shifting and buffer drive functions. Gate driver devices also satisfy other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate drive transformers and controlling floating power device gates which reduces power dissipation and thermal stress in controller devices by moving gate charge power losses into itself. In summary Gate-driver devices are an extremely important component in switching power combining benefits of high performance, low cost, component count, board-space reduction, and simplified system design. 9.2 Typical Application ENB UCC27528-Q1 ENA 1 ENA INA 2 INA 3 GND 4 INB ENB 8 OUTA 7 VDD 6 OUTB 5 V+ GND INB GND GND UDG-11225 Figure 24. UCC27528-Q1 Typical Application Diagram 16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 Typical Application (continued) 9.2.1 Design Requirements When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are input-to-output Logic, enable and disable function, supply voltage (VDD), propagation delay, and power dissipation. The design requirements include the following: • Supply voltage (VDD) • Type of input threshold (CMOS or TTL) • Propagation delay • Delay matching • Peak drive current • Enable function (whether or not it exists) • Operating temperature range 9.2.2 Detailed Design Procedure 9.2.2.1 Input-to-Output Logic The design should specify which type of input-to-output configuration should be used. The UCC27528-Q1 device can only provide dual non-inverting input-to-output with enable control. 9.2.2.2 Enable and Disable Function Certain applications demand independent control of the output state of the driver. The UCC27528-Q1 device offers two independent enable pins ENx pins for exclusive control of each driver channels as listed in Table 2. The ENA, ENB pins in the UCC27528-Q1 device can be in the floating condition during standard operation with the outputs enabled. 9.2.2.3 VDD Bias Supply Voltage The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the Recommended Operating Conditions table. However, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC27528Q1 device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10V, 12 V), IGBTs (VGE = 15 V, 18 V), and wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be applied to the gate pins). 9.2.2.4 Propagation Delay The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC27528-Q1 device features fast 17-ns (typical) propagation delays which ensures very-little pulse distortion and allows operation at very highfrequencies. See the Switching Characteristics table for the propagation and switching characteristics of the UCC27528-Q1 device. For certain application that require programmable propagation delay, The UCC27528-Q1 device can accept slow dv/dt input signals which allows designers to use RCD circuits on the input pin to program propagation as shown in Figure 21. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 17 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Typical Application (continued) 9.2.2.5 Drive Current and Power Dissipation The UCC27528-Q1 driver device is capable of delivering 5 A of current to a MOSFET gate for a period of several hundred nanoseconds at VDD = 12 V. High peak current is required to quickly turn on the device. Then, to turn off the device, the driver is required to sink a similar amount of current to ground. This process repeats at the operating frequency of the power device. The power dissipated in the gate-driver device package depends on the following factors: • The gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close to input bias supply voltage VDD because of low VOH drop-out) • Switching frequency • Use of external gate resistors Because the UCC27528-Q1 device features very-low quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, the effect on the power dissipation within the gate driver can be safely assumed to be negligible. When a driver device is tested with a discrete, capacitive load, calculating the power that is required from the bias supply fairly simple. Use Equation 2 to calculate the energy that must be transferred from the bias supply to charge the capacitor. 1 EG = CLOAD VDD2 2 where • • CLOAD is load capacitor VDD is bias voltage feeding the driver (2) An equal amount of energy is dissipated when the capacitor is charged which leads to a total power loss given by Equation 3. PG = CLOAD VDD2 fSW where • fSW is the switching frequency (3) With VDD = 12 V, CLOAD = 10 nF, and fSW = 300 kHz, use Equation 4 to calculate the power loss. PG = 10 nF ´ 12 V 2 ´ 300 kHz = 0.432 W (4) The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge required to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Use the gate charge Qg to determine the power that must be dissipated when charging a capacitor by using the equivalence Qg = CLOADVDD to provide Equation 5 for power. PG = CLOAD VDD2 fSW = Qg VDD fSW (5) Assuming that the UCC27528-Q1 device is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on each output, use Equation 6 to calculate the gate-charge related power loss. PG = 2 ´ 60 nC ´ 12 V ´ 300 kHz = 0.432 W (6) This power, PG, is dissipated in the resistive elements of the circuit when the MOSFET is turned on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the driver and MOSFET or IGBT, this power is completely dissipated inside the driver package. With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, use Equation 7 to calculate the driver power dissipation during switching. 18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 Typical Application (continued) æ ö ROFF RON PSW = 0.5 ´ QG ´ VDD ´ fSW ´ ç + ÷ è ROFF + RGATE RON + RGATE ø where • • ROFF = ROL RON (effective resistance of pullup structure) = 1.5 × ROL (7) In addition to the previously calculated gate-charge related power dissipation, additional dissipation in the driver is related to the power associated with the quiescent bias current consumed by the device to bias all internal circuits, such as input stage (with pullup and pulldown resistors), enable, and UVLO sections. Referring to Figure 4, the quiescent current is less than 0.6 mA even in the highest case. Use Equation 8 to calculate the quiescent power dissipation. PQ = IDD VDD (8) Assuming, IDD = 6 mA, use Equation 9 to calculate the power loss. PQ = 0.6 mA ´ 12 V = 7.2 mW (9) Clearly, this power loss is insignificant compared to gate-charge related power dissipation that was calculated previously. With a 12-V supply, the bias current can be estimated as shown in Equation 10, with an additional 0.6-mA overhead for the quiescent consumption: P 0.432 W IDD ~ G = = 0.036 A VDD 12 V (10) 9.2.3 Application Curves VDD = 5 V, Load = 2 RJK0453DPB (power FET) Figure 25. Typical Turnon Waveform Figure 26. Typical Turnoff Waveform 10 Power Supply Recommendations The bias supply voltage range for which the UCC27528-Q1 device is rated to operate is from 4.5 V to 18 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VON supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute-maximum voltage rating of the VDD pin of the device (which is a stress rating). Maintaining a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 18 V. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 19 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com The UVLO protection feature also involves a hysteresis function. This hysteresis function means that when the VDD pin bias voltage exceeds the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification, VDD_H. Therefore, ensuring that, while operating at or near the 4.2-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above the VON threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTA or OUTB pin is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the output pins, a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that local bypass capacitors are provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low-ESR, ceramic surface-mount capacitor is a must. TI recommends having 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close to the pins of the device and another surface-mount capacitor of few microfarads added in parallel. 11 Layout 11.1 Layout Guidelines Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device operation and design robustness. The UCC27528-Q1 gate driver incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very-fast rise and fall times at the gate of the power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers: • Locate the driver device as close as possible to power device to minimize the length of high-current traces between the output pins and the gate of the power device. • Locate the VDD bypass capacitors between the VDD and GND pins as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support the high peak current that is drawn from the VDD pin during turn-on of power MOSFET. The use of low inductance SMD components, such as chip resistors and chip capacitors, is highly recommended. • The turn-on and turn-off current-loop paths (driver device, power MOSFET, and VDD bypass capacitor) should be minimized as much as possible to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances: during turn-on transients and turn-off transients, which will induce significant voltage transients on the output pin of the driver device and gate of the power MOSFET. • Wherever possible parallel the source and return traces, taking advantage of flux cancellation. • Separate power traces and signal traces, such as output and input signals. • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as the source of power MOSFET, the ground of PWM controller, and other sources at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. • Use a ground plane to provide noise shielding. Fast rise and fall times at the OUTx pin may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation. 20 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 UCC27528-Q1 www.ti.com SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 11.2 Layout Example INA 8 : ENB 2 : INA 7 : OUTA 3 : GND 6 : VDD 4 : INB 5 : OUTB 0 GND OUTA OUTB VDD GND INB 1 : ENA 1 VDD 2 GND VDD Figure 27. Layout Example for UCC27528-Q1 11.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a gate driver device to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 21 UCC27528-Q1 SNVSA89A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: UCC27528-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC27528QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 27528Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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