UCC27532
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SLUSBD9 – FEBRUARY 2013
2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver
Check for Samples: UCC27532
FEATURES
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Low Cost Gate Driver (offering optimal
solution for driving FET and IGBTs)
Superior Replacement to Discrete Transistor
Pair Drive (providing easy interface with
controller)
CMOS Compatible Input Logic Threshold
(becomes fixed at VDD above 18 V)
Split Outputs Allow Separate Turn-On and
Turn-Off Tuning
Enable with Fixed TTL Compatible Threshold
High 2.5-A Source and 5-A Sink Peak Drive
Currents at 18-V VDD
Wide VDD Range From 10 V up to 35 V
Input Pins Capable of Withstanding up to -5-V
DC Below Ground
Output Held Low When Inputs are Floating or
During VDD UVLO
Fast Propagation Delays (17-ns typical)
Fast Rise and Fall Times
(15-ns and 7-ns typical with 1800-pF Load)
Under Voltage Lockout (UVLO)
Used as a High-Side or Low-Side Driver (if
designed with proper bias and signal isolation)
Low Cost, Space Saving 6-Pin DBV (SOT-23)
Package
Operating Temperature Range of -40°C to
140°C
APPLICATIONS
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Switch-Mode Power Supplies
DC-to-DC Converters
Solar Inverters, Motor Control, UPS
HEV and EV Chargers
Home Appliances
Renewable Energy Power Conversion
SiC FET Converters
DESCRIPTION
The UCC27532 is a single-channel, high-speed, gate
driver capable of effectively driving MOSFET and
IGBT power switches by up to 2.5-A source and 5-A
sink (asymmetrical drive) peak current. Strong sink
capability in asymmetrical drive boosts immunity
against parasitic Miller turn-on effect. The UCC27532
device also features a split-output configuration
where the gate-drive current is sourced through
OUTH pin and sunk through OUTL pin. This pin
arrangement allows the user to apply independent
turn-on and turn-off resistors to the OUTH and OUTL
pins respectively and easily control the switching slew
rates.
The driver has rail-to-rail drive capability and
extremely small propagation delay typically 17 ns.
The UCC27532DBV has CMOS input threshold
centered 55% rise and 45% fall in regards of VDD at
VDD below or equal 18 V. When VDD is above 18 V,
the input threshold remains fixed at its maximum
level.
The driver has EN pin with fixed TTL compatible
threshold. EN is internally pulled up; pulling EN low
disables driver, while leaving it open provides normal
operation. The EN pin can be used as an additional
input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output
low. The logic behavior of the driver is shown in the
application diagram, timing diagram and input and
output logic truth table.
Internal circuitry on VDD pin provides an under
voltage lockout function that holds output low until
VDD supply voltage is within operating range.
The UCC27532 driver is offered in a 6-pin standard
SOT-23 (DBV) package. The device operates over
wide temperature range of -40°C to 140°C.
UCC27532DBV (TOP VIEW)
EN 1
6 OUTH
IN 2
5 OUTL
VDD 3
4 GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
UCC27532
SLUSBD9 – FEBRUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
PART NUMBER
PACKAGE (2)
PEAK CURRENT
(SOURCE AND SINK)
INPUT THRESHOLD
LOGIC
OPERATING
TEMPERATURE RANGE
TA
UCC27532DBV
SOT-23, 6-PIN
2.5 A and 5 A
CMOS-(dependent on
VDD bias voltage)
-40°C to +140°C
DBV package uses Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to
be compatible with either lead free or Sn/Pb soldering operations.
For the most up-to-date packaging information see the TI web site.
ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply voltage range,
VDD
-0.3
35
Continuous
OUTH, OUTL
-0.3
VDD +0.3
Pulse
OUTH, OUTL (200 ns)
-2
VDD +0.3
-5
27
Continuous IN, EN
Pulse IN, EN (1.5 µs)
-6.5
27
Human body model, HBM (ESD)(5)
4000
Charged device model, CDM (ESD)
1000
Operating virtual junction temperature range, TJ
-40
150
Storage temperature range, Tstg
-65
150
Lead temperature
(1)
(2)
(3)
2
Soldering, 10 sec.
300
Reflow
260
V
V
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
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THERMAL INFORMATION
UCC27532
THERMAL METRIC (1)
DBV
UNITS
6 PINS
Junction-to-ambient thermal resistance (2)
θJA
178.3
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
28.3
ψJT
Junction-to-top characterization parameter (5)
14.7
ψJB
Junction-to-board characterization parameter (6)
27.8
θJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1)
(2)
(3)
(4)
(5)
(6)
(7)
109.7
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage range, VDD
TYP
10
Operating junction temperature range
MAX
18
UNIT
32
V
°C
-40
140
Input voltage, IN
-5
25
Enable, EN
-5
25
V
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, IN switching from 0 V to VDD, 1-µF capacitor from VDD to
GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together.
Typical condition specifications are at 25°C.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Bias Currents
IDDoff
Startup Current, VDD = 7.0
IN, EN = VDD
100
240
350
IN, EN = GND
100
250
350
μA
Under Voltage Lockout (UVLO)
VON
Supply start threshold
8.0
8.9
9.8
VOFF
Minimum operating voltage
after supply start
7.3
8.2
9.1
VDD_H
Supply voltage hysteresis
V
0.7
Input (IN)
VIN_H
Input signal high threshold
Output high
8.8
9.4
10
VIN_L
Input signal low threshold
Output low
6.7
7.3
7.9
VIN_HYS
Input signal hysteresis
V
2.1
Enable (EN)
VEN_H
Enable signal high threshold
Output high
1.7
1.9
2.1
VEN_L
Enable signal low threshold
Output low
0.8
1.0
1.2
VEN_HYS
Enable signal hysteresis
V
0.9
Outputs (OUTH/OUTL)
ISRC/SNK
Source peak current (OUTH)/
sink peak current
(OUTL)(13) (1)
CLOAD = 0.22 µF, f = 1 kHz
VOH
OUTH, high voltage
IOUTH = -10 mA
VOL
OUTL, low voltage
IOUTL = 100 mA
ROH
OUTH, pull-up resistance
(15) (2)
TA = 25°C, IOUT = -10 mA
ROL
OUTL, pull-down resistance
Switching Time
TA = -40°C to 140°C, IOUT = -10 mA
TA = 25°C, IOUT = 100 mA
TA = -40°C to 140°C, IOUT = 100 mA
-2.5/+5
A
VDD 0.12
VDD 0.07
0.065
0.125
11
12
12.5
7
12
20
0.45
0.65
0.85
0.3
0.65
1.25
VDD -0.2
Rise time
CLOAD = 1.8 nF
tF
Fall time
CLOAD = 1.8 nF
tD1
Turn-on propagation delay
CLOAD = 1.8 nF, IN = 0 V to VDD
17
26
tD2
Turn-off propagation delay
CLOAD = 1.8 nF, IN = VDD to 0 V
17
26
(3)
4
Ω
(1) (3)
tR
(1)
(2)
V
15
7
ns
Ensured by design and tested during characterization. Not production tested.
Output pull-up resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure. The
effective dynamic pull-up resistance is 3 x ROL.
See Figure 1.
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Timing Diagram
Figure 1. (OUTH tied to OUTL)(Input = IN,
Output = OUT (EN = VDD),
or Input = EN, Output = OUT (IN = VDD)
DEVICE INFORMATION
Block Diagram
(EN Pull-Up Resistance to VREF = 500 kΩ, VREF = 5.8 V, In Pull-Down Resistance to GND = 230 kΩ)
IN
VDD
2
VREF
EN
1
3
VDD
6
OUTH
5
OUTL
VDD
GND
4
UVLO
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DEVICE INFORMATION
Typical Application Diagrams
UCC27532
EN
OUTH
1
6
IN
OUTL
+
2
5
VDD
GND
3
+
–
4
GND
Bouncing Up
to -6.5 V
18 V
ISENSE
Controller
VCE(sense)
VCC
+
–
Figure 2. Driving IGBT Without Negative Bias
UCC27532
EN
OUTH
1
IN
6
OUTL
+
2
5
VDD
GND
3
+
–
4
18 V
+
–
13 V
Figure 3. Driving IGBT With 13-V Negative Turn-Off Bias
6
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E/2
+
–
Isol.
UCC27532
Isol.
UCC27532
Controller
Isol.
UCC27532
Isol.
UCC27532
E/2
+
–
Figure 4. Using UCC27532 Drivers in an Inverter
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DEVICE INFORMATION
SOT-23, 6-Pin (DBV) Package (top view)
EN 1
6 OUTH
IN 2
5 OUTL
VDD 3
4 GND
TERMINAL FUNCTIONS
TERMINAL
I/O
FUNCTION
PIN NUMBER
NAME
1
EN
I
Enable
(Pull EN to GND in order to disable output, pull it high or leave open to enable
output).
2
IN
I
Driver non-inverting input (CMOS threshold for UCC27532DBV).
3
VDD
I
Bias supply input.
4
GND
-
Ground (all signals are referenced to this node).
5
OUTL
O
5-A sink current output of driver.
6
OUTH
O
2.5-A source current output of driver.
INPUT/OUTPUT LOGIC TRUTH TABLE
EN PIN
OUTH PIN
OUTL PIN
OUT
(OUTH and OUTL pins
tied together)
L
L
High-impedance
L
L
L
H
High-impedance
L
L
H
L
High-impedance
L
L
H
H
H
High-impedance
H
IN PIN
8
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TYPICAL CHARACTERISTICS
12
25
10
Fall Time (ns)
Rise Time (ns)
20
15
10
8
6
4
Cload = 1.8nF
Cload = 1.8nF
2
5
0
10
20
30
0
40
Supply Voltage (V)
30
40
C002
Figure 6. Fall Time vs. Supply Voltage
21
30
VDD = 10V
TurnOn
VDD = 18V
TurnOff
VDD = 32V
25
Supply Current (mA)
19
20
Supply Voltage (V)
Figure 5. Rise Time vs. Supply Voltage
Input To Output Propagation Delay (ns)
10
C001
17
20
15
10
15
0
10
20
30
40
Supply Voltage (V)
C003
5
Cload = 1.8nF
0
0
100
200
300
400
500
Frequency (kHz)
C001
Figure 7. Propagation Delay vs. Supply Voltage
Figure 8. Operating Supply Current vs. Frequency
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TYPICAL CHARACTERISTICS (continued)
4.5
350
EN = IN = Vdd
EN = IN = GND
4.3
4.1
Idd (mA)
Startup Current (µA)
300
250
3.9
200
Vdd = 7V
3.7
Vdd = 18V
Cload = 1.8nF
fsw = 100kHz
150
-50
0
50
100
150
Temperature (Ü&
3.5
C003
-50
0
50
100
150
7HPSHUDWXUH Û&
C006
Figure 9. Start-Up Current vs. Temperature
Figure 10. Operating Supply Current vs. Temperature
(output switching)
9.6
12
Turn-On
UVLO Rising
UVLO Falling
Turn-Off
11
Input Threshold (V)
Vdd UVLO Threshold (V)
9.2
8.8
10
9
8
7
8.4
6
-50
0
50
100
150
Temperature ( Ü&
8
-50
0
50
100
C002
150
7HPSHUDWXUH Û&
C007
Figure 11. UVLO Threshold Voltage vs. Temperature
10
Figure 12. Input Threshold vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
2.4
25
Enable
ROH
Disable
2.2
Output Pull-Up Resistance (Ÿ)
Enable Threshold (V)
2
1.8
1.6
1.4
1.2
20
15
10
Vdd = 18V
1
0.8
5
-50
0
50
100
150
-50
0
7HPSHUDWXUH Û&
50
100
C009
C010
Figure 13. Enable Threshold vs. Temperature
Figure 14. Output Pull-Up Resistance vs. Temperature
1.2
0.6
IN=HIGH
ROL
IN=LOW
Operating Supply Current (mA)
1
Output Pull-Down Resistance (Ÿ)
150
7HPSHUDWXUH Û&
0.8
0.6
0.5
0.4
0.3
0.4
Vdd = 18V
Vdd = 18V
0.2
0.2
-50
0
50
100
150
-50
0
50
100
150
7HPSHUDWXUH Û&
7HPSHUDWXUH Û&
C012
C011
Figure 15. Output Pull-Down Resistance vs. Temperature
Figure 16. Operating Supply Current vs. Temperature
(output in DC on/off condition)
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TYPICAL CHARACTERISTICS (continued)
16
30
Turn-On
Turn-Off
15
Rise Time (ns)
Propagation Delay (ns)
25
20
14
13
Vdd = 18V
Cload = 1.8nF
15
12
Vdd = 18V
10
11
-50
0
50
100
-50
150
0
7HPSHUDWXUH Û&
50
100
C013
C014
Figure 18. Rise Time vs. Temperature
9
10
8
8
Supply Current (mA)
Fall Time (ns)
Figure 17. Input-to-Output Propagation Delay vs.
Temperature
7
6
Vdd = 18V
Cload = 1.8nF
6
4
Cload = 10nF
fsw = 20kHz
5
2
4
0
-50
0
50
100
150
0
7HPSHUDWXUH Û&
10
20
30
40
Supply Voltage (V)
C015
Figure 19. Fall Time vs. Temperature
12
150
7HPSHUDWXUH Û&
C016
Figure 20. Operating Supply Current vs. Supply Voltage
(output switching)
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TYPICAL CHARACTERISTICS (continued)
70
140
60
120
Fall Time (ns)
Rise Time (ns)
50
100
80
40
30
60
20
Cload = 10nF
Cload = 10nF
40
10
0
10
20
30
40
0
Supply Voltage (V)
10
20
30
40
Supply Voltage (V)
C017
Figure 21. Rise Time vs. Supply Voltage
C018
Figure 22. Fall Time vs. Supply Voltage
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APPLICATION INFORMATION
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation will be often encountered since the
PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or p- n-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this since they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC27532 is very flexible in this role with a strong current drive capability and wide supply voltage range up
to 35 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and -5-V (relative to Source)
SiC FET applications, 15-V and -15-V(relative to Emitter) IGBT applications and many others. As a singlechannel driver, the UCC27532 can be used as a low-side or high-side driver. To use as a low-side driver, the
switch ground is usually the system ground so it can be connected directly to the gate driver. To use as a highside driver with a floating return node however, signal isolation is needed from the controller as well as an
isolated bias to the UCC27532. Alternatively, in a high-side drive configuration the UCC27532 can be tied directly
to the controller signal and biased with a non-isolated supply. However, in this configuration the outputs of the
UCC27532 need to drive a pulse transformer which then drives the power-switch to work properly with the
floating source and emitter of the power switch. Further, having the ability to control turn-on and turn-off speeds
independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining system
reliability. These requirements coupled with the need for low propagation delays and availability in compact, lowinductance packages with good thermal capability makes gate driver devices such as the UCC27532 extremely
important components in switching power combining benefits of high-performance, low cost, component count
and board space reduction and simplified system design.
14
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Table 1. UCC27532 Features and Benefits
FEATURE
BENEFIT
High source and sink current capability, 2.5 A and
5 A (asymmetrical).
High current capability offers flexibility in employing UCC27532 device to drive a
variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.
Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V.
Flexibility in system design.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection.
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free
operation at power-up and power-down.
High UVLO of 8.9V typical ensures that power switch is not on in high-impedance
state which could result in high power dissipation or even failures.
Outputs held low when input pin (IN) in floating
condition.
Safety feature, especially useful in passing abnormal condition tests during safety
certification
Split output structure (OUTH, OUTL).
Allows independent optimization of turn-on and turn-off speeds using series gate
resistors.
Strong sink current (5 A) and low pull-down
impedance (0.65 Ω).
High immunity to high dV/dt Miller turn-on events.
CMOS compatible input threshold logic with wide
2.1-V hysteresis.
Excellent noise immunity.
Input capable of withstanding -6.5 V.
Enhanced signal reliability in noisy environments that experience ground bounce on
the gate driver.
VDD Under Voltage Lockout
The UCC27532 device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of
the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than
VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs
LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops in the VDD bias voltage when the system commences switching and there is a sudden
increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si
MOSFETs, IGBTs, and emerging SiC FETs.
VDD Threshold
VDD
IN
OUT
Figure 23. Power Up
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Input Stage
The input pin of UCC27532 device is based on a standard CMOS compatible input threshold logic that is
dependent on the VDD supply voltage. The input threshold is approximately 55% of VDD for rise and 45% of
VDD for fall. With 18-V VDD, typical high threshold = 9.4 V and typical low threshold = 7.3 V. The 2.1-V
hysteresis offers excellent noise immunity compared to traditional TTL logic implementations, where the
hysteresis is typically less than 0.5 V. For proper operation using CMOS input, the input signal level should be at
a voltage equal to VDD. Using an input signal slightly larger than the threshold but less than VDD for CMOS
input can result in slower propagation delay from input to output for example. This device also features tight
control of the input pin threshold voltage levels which eases system design considerations and guarantees stable
operation across temperature. The very low input capacitance , typically 20 pF, on these pins reduces loading
and increases switching speed.
The device features an important safety function wherein, whenever the input pin is in a floating condition, the
output is held in the low state. This is achieved using GND pull-down resistors on the non-inverting input pin (IN
pin), as shown in the device block diagram.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since
the device features just one GND pin which may be referenced to the power ground, this may interfere with
the differential voltage between Input pins and GND and trigger an unintended change of output state.
Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage
• 2.1-V input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is
highly recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
Enable Function
The Enable (EN) pin of the UCC27532 has an internal pull-up resistor to an internal reference voltage so leaving
Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also
be driven by low-voltage logic to enable and disable the driver.
16
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Output Stage
The output stage of the UCC27532 device is illustrated in Figure 24. The UCC27532 device features a unique
architecture on the output stage which delivers the highest peak source current when it is most needed during
the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage
experiences dV/dt). The device output stage features a hybrid pull-up structure using a parallel arrangement of
N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant
when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak
sourcing current enabling fast turn on.
VDD
R OH
R NMOS, Pull Up
OUTH
Input Signal Anti Shoot Through
Circuitry
Narrow Pulse at
each Turn On
OUTL
R OL
Figure 24. UCC27532 Gate Driver Output Stage
The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of
the P-Channel device only, since the N-Channel device is turned-on only during output change of state from low
to high. Thus the effective resistance of the hybrid pull-up stage is much lower than what is represented by ROH
parameter. The pull-down structure is composed of a N-Channel MOSFET only. The ROL parameter (see
ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true impedance of
the pull-down stage in the device. In UCC27532, the effective resistance of the hybrid pull-up structure is
approximately 3 x ROL.
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The UCC27532 is capable of delivering 2.5-A source, 5-A Sink (asymmetrical drive) at VDD = 18 V. Strong sink
capability in asymmetrical drive results in a very low pull-down impedance in the driver output stage which boosts
immunity against the parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and
FET power switches .
An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current
charging the CGD Miller capacitance during this high dV/dt is shunted by the pull-down stage of the driver. If the
pull-down impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can
result in spurious turn on. This phenomenon is illustrated in Figure 25.
VDS
VIN
Miller Turn -On Spike in V GS
C GD
Gate Driver
RG
COSS
ISNK
CGS
ROL
VTH
VGS of
MOSFET
ON OFF
VIN
VDS of
MOSFET
Figure 25. Low Pull-Down Impedance in UCC27532
(output stage mitigates Miller turn-on effect)
The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS
output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode
clamps may be eliminated.
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Power Dissipation
Power dissipation of the gate driver has two portions as shown in equation below:
PDISS = PDC + PSW
(1)
The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections etc and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shootthrough). The UCC27532 features very low quiescent currents (less than 1 mA) and contains internal logic to
eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the total power dissipation
within the gate driver can be safely assumed to be negligible. In practice this is the power consumed by driver
when its output is disconnected from the gate of power switch.
The power dissipated in the gate driver package during switching (PSW) depends on the following factors:
• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOH drop-out)
• Switching frequency
• Use of external gate resistors
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
1
EG = CLOAD VDD2
2
where
•
CLOAD is load capacitor and VDD is bias voltage feeding the driver.
(2)
There is an equal amount of energy dissipated when the capacitor is discharged. During turn off the energy
stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given
by the following:
PG = CLOAD VDD2 fsw
where
•
ƒSW is the switching frequency
(3)
The switching load presented by a power FET and IGBT can be converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between
the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC,
to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that
must be dissipated when charging a capacitor. This is done by using the equivalence, Qg = CLOADVDD, to provide
the following equation for power:
PG = CLOAD VDD2 fsw = Qg VDD fsw
(4)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned
on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other
half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is
employed between the driver and MOSFET and IGBT, this power is completely dissipated inside the driver
package. With the use of external gate drive resistors, the power dissipation is shared between the internal
resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power
dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation
during switching is calculated as follows:
æ
ö
ROFF
RON
PSW = 0.5 ´ Qg ´ VDD ´ fsw ç
+
÷
ç (ROFF + RGATE ) (RON + RGATE ) ÷
è
ø
where
•
ROFF = ROL and RON (effective resistance of pull-up structure) = 3 x ROL
(5)
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Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is summarized in the ‘Thermal Information’ section of the
datasheet. For detailed information regarding the thermal information table, please refer to Application Note from
Texas Instruments entitled “IC Package Thermal Metrics” (SPRA953A).
PCB Layout
Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device
operation and design robustness. The UCC27532 gate driver incorporates short propagation delays and powerful
output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power
switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even
higher (2.5-A and 5-A peak current is at VDD = 18 V). Very high di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended
when designing with these high-speed drivers.
• Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the driver Output pins and the gate of the power switch device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD
during turn-on of power switch. The use of low inductance SMD components such as chip resistors and chip
capacitors is highly recommended.
• The turn-on and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be
minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established
in these loops at two instances – during turn-on and turn-off transients, which induces significant voltage
transients on the output pins of the driver device and gate of the power switch.
• Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux
cancellation
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM
controller etc at one, single point. The connected paths should be as short as possible to reduce inductance
and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC27532DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
7532
UCC27532DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
7532
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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