UCC28019DRG4

UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 8-Pin Continuous Conduction Mode (CCM) PFC Controller FEATURES DESCRIPTION 1 • • • • • • • • • 8-pin Solution Without Sensing Line Voltage Reduces External Components Wide-Range Universal AC Input Voltage Fixed 65-kHz Operating Frequency Maximum Duty Cycle of 97% Output Over/Under-Voltage Protection Input Brown-Out Protection Cycle-by-Cycle Peak Current Limiting Open Loop Detection Low-Power User Controlled Standby Mode APPLICATIONS • • • • • CCM Boost Power Factor Correction Power Converters in the 100 W to >2 kW Range Server and Desktop Power Supplies Telecom Rectifiers Industrial Electronics Home Electronics CONTENTS • • • • • Electrical Characteristics 3 Device Information 10 Application Information 12 Design Example 23 Additional References 43 The UCC28019 8-pin active Power Factor Correction (PFC) controller uses the boost topology operating in Continuous Conduction Mode (CCM). The controller is suitable for systems in the 100 W to >2 kW range over a wide-range universal ac line input. Startup current during under-voltage lockout is less than 200 µA. The user can control low power standby mode by pulling the VSENSE pin below 0.77 V. Low-distortion wave-shaping of the input current using average current mode control is achieved without input line sensing, reducing the Bill of Materials component count. Simple external networks allow for flexible compensation of the current and voltage control loops. The switching frequency is internally fixed and trimmed to better than 5% accuracy at 25°C. Fast 1.5-A gate peak current drives the external switch. Numerous system-level protection features include peak current limit, soft over-current detection, open-loop detection, input brown-out detection, output over-voltage protection/under-voltage detection, a no-power discharge path on VCOMP, and overload protection on ICOMP. Soft-Start limits boost current during start-up. A trimmed internal reference provides accurate protection thresholds and regulation set-point. An internal clamp limits the gate drive voltage to 12.5 V. TYPICAL APPLICATION DIAGRAM VOUT EMI Filter LINE INPUT – Bridge Rectifier + 1 GND 2 ICOMP 3 ISENSE 4 VINS GATE 8 VCC 7 VSENSE 6 VCOMP 5 Auxilary Supply Rload UCC28019 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 ORDERING INFORMATION (1) OPERATING TEMPERATURE RANGE, TA PART NUMBER PACKAGE (1) UCC28019D SOIC 8-Pin (D) ead (Pb)-Free/Green UCC28019P Plastic DIP 8 Pin (P) Lead (Pb)-Free/Green –40°C to 125°C SOIC (D) package is available taped and reeled by adding "R" suffix the the above part number, reeled quantities are 2500 devices per reel. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Input voltage range Input current range Junction temperature, TJ Lead temperature, TSOL (1) VCC –0.3 to 22 GATE –0.3 to 16 VINS, VSENSE, VCOMP, ICOMP –0.3 to 7 ISENSE –24 to 7 VSENSE, ISENSE –1 to 1 Operating –55 to 150 Storage –65 to 150 Soldering, 10s UNIT V mA °C 300° Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability. DISSIPATION RATINGS (1) PACKAGE (1) THERMAL IMPEDANCE TA = 25°C POWER RATING (W) JUNCTION TO AMBIENT (°C/W) TA = 85°C POWER RATING (W) SOIC-8 (D) 160 0.65 0.25 PDIP-8 (P) 110 1 0.36 Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a general guide. See TI document SPRA953 Thermal Metrics. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN VCC input voltage from a low-impedance source TJ MAX UNIT VCCOFF(max) + 1 V 21 V –40 125 °C Operating junction temperature ELECTROSTATIC DISCHARGE (ESD) PROTECTION over operating free-air temperature range (unless otherwise noted) PARAMETER RATING Human Body Model (HBM) Charged Device Model (CDM) 2 Submit Documentation Feedback UNIT 2 kV 500 V Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS Unless otherwise noted, VCC = 15 VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Bias Supply IVCC(start) Pre-start current VCC = VCCON – 0.1 V 25 100 200 IVCC(stby) Standby current VSENSE = 0.5 V 1.0 2.1 2.9 IVCC(on_load) Operating current VSENSE = 4.5 V, CGATE = 4.7 nF 4 7 10 10.0 10.5 11.0 µA mA Under Voltage Lockout (UVLO) VCCON Turn on threshold VCCOFF Turn off threshold UVLO Hysteresis 9 9.5 10 0.8 1.0 1.2 61.7 65.0 68.3 59 65 71 V Oscillator fSW TA = 25°C Switching frequency, –40°C ≤ TA ≤ 125°C kHz PWM DMIN Minimum duty cycle VCOMP = 0 V, VSENSE = 5 V, ICOMP = 6.4 V DMAX Maximum duty cycle VSENSE = 4.95 V tOFF(min) Minimum off time VSENSE = 3 V, ICOMP = 1 V 0% 94% 97% 99.3% 100 250 600 ns System Protection VSOC ISENSE threshold, soft over current (SOC) , -0.66 -0.73 -0.79 VPCL ISENSE threshold, peak current Limit (PCL) , -1.00 -1.08 -1.15 VOLP VSENSE threshold, open loop protection (OLP), ICOMP = 1 V, ISENSE = 0 V, VCOMP = 1 V 0.77 0.82 0.86 Open loop protection (OLP) internal pull-down current VSENSE = 0.5 V 100 250 4.63 4.75 4.87 5.12 5.25 5.38 VUVD VSENSE threshold, output under-voltage detection (UVD), VOVP VSENSE threshold, output over-voltage protection (OVP), VINSBROWNOUT_th Input brown-out detection (IBOP) high-to-low threshold 0.76 0.82 0.88 VINSENABLE_th Input brown-out Detection (IBOP) low-to-high threshold 1.4 1.5 1.6 IVINS_0 VINS bias current 0 ±0.1 V ISENSE = -0.2 V V nA V VINS = 0 V ICOMP threshold, external overload protection 0.6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 µA V 3 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, VCC = 15 VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current Loop gmi Transconductance gain TA = 25°C 0.75 Output linear range 0.95 1.15 ICOMP voltage during OLP VSENSE = 0.5 V VREF Reference voltage -40°C ≤ TA ≤ 125°C gmv Transconductance gain mS µA 50 3.7 4.0 4.3 V 4.90 5.00 5.10 V 31.5 42 52.5 µS 21 30 38 Voltage Loop Maximum sink current under normal operation VSENSE = 6 V, VCOMP = 4 V Source current under soft start VSENSE = 4 V, VCOMP = 0 V –21 -30 -38 Maximum source current under EDR operation VSENSE = 4 V, VCOMP = 0 V –100 –170 –250 VSENSE = 4 V, VCOMP = 4 V –60 –100 –140 4.63 4.75 4.87 V 100 250 nA 0.2 0.4 V Enhanced dynamic response, VSENSE low threshold, falling VSENSE input bias current 1 V ≤ VSENSE ≤ 5 V VCOMP voltage during OLP VSENSE = 0.5 V, IVCOMP = 0.5 mA 0 µA GATE Driver GATE current, peak, sinking (1) GATE current, peak, sourcing (1) 4 (1) CGATE = 4.7 nF 2.0 CGATE = 4.7 nF –1.5 A GATE rise time CGATE = 4.7 nF, GATE = 2 V to 8 V 40 60 GATE fall time CGATE = 4.7 nF, GATE = 8 V to 2 V 25 40 GATE low voltage, no load GATE = 0 A 0 0.05 GATE low voltage, sinking GATE = 20 mA 0.3 0.8 GATE low voltage, sourcing GATE = -20 mA –0.3 –0.8 GATE low voltage, sinking VCC = 5 V, GATE = 5 mA 0.2 0.75 1.2 GATE low voltage, sinking VCC = 5 V, GATE = 20 mA 0.2 0.9 1.5 GATE high voltage VCC = 20 V, CGATE = 4.7 nF 11 12.5 14 GATE high voltage VCC = 11 V, CGATE = 4.7 nF 9.5 10.5 11.0 GATE high voltage VCC = VCCOFF + 0.2 V, CGATE = 4.7 nF 8.0 9.0 10.2 ns V Not tested. Characterized by design. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS Unless otherwise noted, VCC = 15 VDC, 0.1 µF from VCC to GND, TJ = TA = 25°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE UVLO THRESHOLDS vs TEMPERATURE 4.0 12.0 VSENSE = VINS = 3V No Gate Load 11.0 VCC Turn ON (VCCON) 3.0 IVCC - Supply Current - mA VCCON/VCCOFF - UVLO Threshold - V 3.5 10.0 2.5 2.0 IVCC Turn OFF IVCC Turn ON 1.5 1.0 VCC Turn OFF (VCCOFF) 9.0 0.5 0 8.0 0 -60 -35 -10 15 40 65 90 115 5 140 10 15 20 VCC - Bias Supply Voltage - V TJ - Temperature - °C Figure 1. Figure 2. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 10 0.5 VCC = VCCON - 0.1 V 9 7 IVCC(start) - Supply Current - mA IVCC - Supply Current - mA 8 Operating, GATE Load = 4.7 nF IVCC(on_load) 6 5 4 Standby IVCC(stby) 3 2 0.4 0.3 0.2 Pre-Start (IVCC(start)) 0.1 1 0 0 -60 -35 -10 15 40 65 90 115 140 -60 TJ - Temperature - °C Figure 3. -35 -10 15 40 65 90 TJ - Temperature - °C 115 140 Figure 4. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 5 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs BIAS SUPPLY VOLTAGE 75 75 73 73 71 71 fSW - Switching Frequency - kHz fSW - Switching Frequency - kHz OSCILLATOR FREQUENCY vs TEMPERATURE 69 Switching Frequency 67 65 63 61 59 69 67 65 63 61 59 57 57 55 55 -60 -35 -10 15 40 65 90 115 Switching Frequency 140 12 10 TJ - Temperature - °C 14 Figure 5. 50 1.8 48 1.6 46 1.4 44 gmv - Gain - µA/V gmi - Gain - mA/V VOLTAGE ERROR AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE Gain 1.2 1.0 0.8 Gain 42 40 38 0.6 36 0.4 34 0.2 32 0 30 -60 -35 -10 15 40 65 90 115 140 -60 TJ - Temperature - °C -35 -10 15 40 65 90 115 140 TJ - Temperature - °C Figure 7. 6 20 Figure 6. CURRENT AVERAGING AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE 2.0 18 16 VCC - Bias Supply Voltage - V Figure 8. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) VSENSE THRESHOLD vs TEMPERATURE VSENSE THRESHOLD vs TEMPERATURE 5.50 2.0 VOVP / VUVD- VSENSE Threshold - V VOLP – VSENSE Threshold - V 1.8 1.6 1.4 1.2 1.0 Open Loop Protection (VOLP) 0.8 0.6 0.4 5.25 Over-Voltage Protection (VOVP) 5.00 4.75 Under-Voltage Protection (VUVD) 0.2 4.50 0 -60 -35 -10 15 40 65 90 TJ - Temperature - °C 115 -60 140 -35 -10 Figure 9. 1.8 -0.1 1.6 -0.2 VSOC - ISENSE Threshold - V VINSENABLE_TH / VINSBROUWNOUT_TH – VINS Threshold - V 0 VINS Enable (VINSENABLE_TH) 1.2 1.0 0.8 Input Brown-Out Protection (VINSBROWNOUT_TH) -0.5 -0.6 -0.9 0 -1.0 15 40 65 90 TJ - Temperature - °C 115 140 Soft Over-Current Protection (SOC) -0.7 0.2 -10 140 -0.4 -0.8 -35 115 -0.3 0.4 -60 140 Figure 10. 2.0 0.6 115 ISENSE THRESHOLD vs TEMPERATURE VINS THRESHOLD vs TEMPERATURE 1.4 15 40 65 90 TJ - Temperature - °C -60 Figure 11. -35 -10 15 40 65 90 TJ - Temperature - °C Figure 12. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 7 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) MINIMUM OFF TIME vs TEMPERATURE GATE DRIVE SWITCHING vs TEMPERATURE 600 50 VSENSE = 3 V ICOMP = 1 V 500 40 450 35 400 30 350 300 tOFF(min) 25 15 200 10 105 5 100 0 -35 -10 15 40 65 90 115 Fall Time 20 250 -60 CGATE = 4.7 nF VGATE = 2 V - 8 V 45 t - Time - ns t - Time - ns 550 Rise Time -60 140 -35 -10 TJ - Temperature - °C 15 Figure 13. 50 90 115 140 115 140 GATE LOW VOLTAGE WITH DEVICE OFF vs TEMPERATURE 2.0 CGATE = 4.7 nF VGATE = 2 V - 8 V VCC = 5 V IVCC = 20 mA 1.8 40 VGATE – Gate Low Voltage - V 1.6 35 t - Time - ns 65 Figure 14. GATE DRIVE SWITCHING vs BIAS SUPPLY VOLTAGE 45 40 TJ - Temperature - °C 30 Rise Time 25 20 Fall Time 15 10 1.4 1.2 VGATE 1.0 0.8 0.6 0.4 5 0.2 0 10 12 14 16 18 VCC - Bias Supply Voltage - V 20 0 -60 -35 -10 15 40 65 90 TJ - Temperature - °C Figure 15. 8 Figure 16. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE vs TEMPERATURE 5.50 VREF - Reference Voltage - V VCC = 15V 5.25 Reference Voltage 5.00 4.75 4.50 -60 -35 -10 15 40 65 90 TJ - Temperature - °C 115 140 Figure 17. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 9 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 DEVICE INFORMATION Connection Diagram UCC28019 Top View (SOIC-8, PDIP-8) GATE 8 2 ICOMP VCC 7 3 ISENSE VSENSE 6 VINS VCOMP 5 1 GND 4 Pin Descriptions Terminal Functions TERMINAL NAME # GATE 8 GND 1 ICOMP 2 I/O O FUNCTION Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. 2.0-A sink and 1.5-A source capability. Output voltage is clamped at 12.5 V. Ground: Device ground reference. O Current loop compensation: Transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.6 V. I Inductor current sense: An input for the voltage across the external current sense resistor, which represents the instantaneous current through the PFC boost inductor. This voltage is averaged to eliminate the effects of noise and ripple. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. Use a 220-Ω resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin. ISENSE 3 VCC 7 Device supply: External bias supply input. Under Voltage Lock Out (UVLO) disables the controller until VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off (UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage. 5 O Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE voltage reaches 95% of its nominal regulation level. When the Enhanced Dynamic Response (EDR) is engaged, additional current is applied to VCOMP to reduce the charge time. EDR additional current is inhibited during soft-start. Soft-start is programmed by the capacitance on this pin. I Input ac voltage sense: Input Brown Out Protection (IBOP) detects when the system ac-input voltage is above a user-defined normal operating level, or below a user-defined “brown-out” level. A filtered resistor-divider network connects from this pin to the rectified-mains node. At startup the controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft-start. The controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft-start. I Output voltage sense: An external resistor-divider network connected from this pin to the PFC output voltage provides feedback sensing for output voltage regulation. A small capacitor from this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8V. An internal 100nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin disconnection. Output over-voltage protection (OVP) disables the GATE output when VSENSE exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load step causes VSENSE to fall below 95% of the reference voltage. VCOMP VINS 4 VSENSE 10 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 EMI Filter LBST LINE INPUT – Bridge Rectifier DBST VOUT + RVINS1 QBST CIN RFB1 RGATE COUT RVINS2 RSENSE RLOAD RFB2 10k ICOMP 2 CICOMP Current Amplifier + FAULT gmi VCC PWM Comparator KPC(s) ICOMP Gate Driver S Q R Q + 4V GAIN M1, K1 Fault IBOP PWM RAMP M2 UVLO Fault Logic GATE OLP Min Off Time 65kHz Oscillator PCL 8 S Q R Q OVP Clock M2 M1 SOC RISENSEfilter Pre-Drive and Clamp Circuit VCOMP UVLO EDR 7 + ISENSE 40k 40k -1x CISENSEfilter Q S Q R VCCON 10.5V Peak Current Limit (PCL) 3 300ns Leading Edge Blanking VPCL 1.08V PCL UVLO + VCC Auxilary Supply CVCC VCCOFF 9.5V 1 GND + + + OVERVOLTAGE 5.25V OVP Soft Over Current (SOC) SOC VSOC 0.73V + OLP/STANDBY 0.82V + UNDERVOLTAGE 4.75V + 5V OLP/STANDBY + VINS 20k EDR Input Brown-Out Protection (IBOP) 4 + CVINS S Q R Q VINENABLE_th 1.5V 5V VINBROWNOUT_th 0.82V SS EDR IBOP + VSENSE gmv FAULT Voltage Error Amplifier 6 CVSENSE 100µA VCOMP 5 RCV CCV2 CCV1 4V Figure 18. Block Diagram Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 11 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 APPLICATION INFORMATION UCC28019 Operation The UCC28019 is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28019 requires few external components to operate as an active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz, ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum are below the EN55022 conducted-band 150-kHz measurement limit. Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85 VAC to 265 VAC mains input range from zero to full output load. The usable system load ranges from 100 W to 2 kW and may be extended in special situations. Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under extremely light load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-D requirements of IEC 1000-3-2 despite the higher harmonics. The outer voltage loop regulates the output voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain parameters for maintaining a low-distortion steady-state input current waveshape. 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): UCC28019 UCC28019 www.ti.com SLUS755B – APRIL 2007 – REVISED DECEMBER 2007 Power Supply The UCC28019 operates from an external bias supply. It is recommended that the device be powered from a regulated auxiliary supply. This device is not intended to be used from a bootstrap bias supply. A bootstrap bias supply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up the voltage on VCC until current can be supplied from a bias winding on the boost inductor. The minimal hysteresis on VCC would require an unreasonable value of hold-up capacitance. During normal operation, when the output is regulated, current drawn by the device includes the nominal run current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor with a minimum value of 0.1 µF is recommended from VCC to GND with short, wide traces. VCC VCCON 10.5V VCCOFF 9.5V IVCC IVCC(ON) IVCC(stby)