UCC28704DBVR-1

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 UCC28704 High-Efficiency Off-Line CV and CC Flyback Controller with Primary-Side Regulation (PSR) 1 Features 3 Description • The UCC28704 Off-line flyback controller is a highly integrated, 6-pin primary-side regulated PWM controller for designing high efficiency AC-to-DC power supplies with low standby power consumption to comply with global efficiency standards. The controller has ultra-low current consumption at startup to enable designs with 4.85 V, the device operates in constant current mode. When load is in step-down transient demanding frequency lower than 4 kHz, first, the device stays at 4 kHz for up to 500 ms, or the output voltage reaches about 10% over the VOCV within 500 ms, then the device adjusts the switching frequency to be lower than 4 kHz as needed. More details can be found in Load Transient Response. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 15 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) 7.3.4 Primary-Side Constant Current (CC) Regulation Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at IPP(max). Referring to Figure 16 below, the primary peak current (IPP), turns-ratio (NS/NP), secondary demagnetization time (tDMAG), and switching period (tSW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 7. By regulating the secondary rectifier conduction duty cycle, the output average current is constant for given IPP and transformer turns-ratio. When the load increases, the secondary-side rectifier conduction duty cycle keep increasing. Once it reaches preset value of 0.475, the converter switching frequency is then reduced to maintain 0.475 secondary-side duty cycle. Therefore, the output current is kept constant. Because the current is kept constant, the increasing load results in lower output voltage. Converter can shut down in this condition if the output voltage drops below CCUV protection level, or UCC28704 VDD drops below its UVLO turn-off threshold. i IPP ISP x NS/NP tON t tDMAG tSW Figure 16. Transformer Currents IOUT IPP NP tDMAG u u 2 NS tSW (7) As shown in Figure 17 below, CV mode operation is from IO = 0 to IOCC; at IO = IOCC, the operation enters CC mode and VO starts to drop as the load resistance becomes further lower while IO is maintained at IOCC until Vo reaches the CCUV threshold. Details of the CCUV operation are given in Constant Current Under-Voltage Protection. Figure 17 shows the output at board-end and at cable-end. The cable compensation nominally compensates 300 mV for a 5V-output at the IOCC level. Vo (Board-End) = VOCV x (1+ 0.06 x IO/IOCC) VOCV VO_CCUV at Board-End Output Voltage VO Vo at Cable-End Fixed Cable Compensation VO_CCUV at Cable-End 0 Output Current IO IOCC Figure 17. Typical Target Output V-I Characteristic 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Feature Description (continued) 7.3.5 Valley-Switching and Valley-Skipping The UCC28704 utilizes valley switching to reduce switching losses in the MOSFET, reduce induced-EMI, and minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load conditions unless the VDS ringing diminished. Referring to Figure 18 below, the UCC28704 operates in a valley-skipping mode in most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest available VDS voltage. VDS 0V VDRV t 0V Figure 18. Valley-Skipping Mode The UCC28704 forces a controlled minimum switching period corresponding to the power supply operating frequency. In each switching cycle, after the minimum period is expired, the UCC28704 looks for the next resonant valley on the auxiliary winding. The controller initiates a new power cycle at this valley point which corresponds to a reduced voltage level on the power MOSFET. If at the point in time when the minimum period expires ringing on the transformer winding has decayed such that no further resonant valleys can be detected a new power cycle is initiated following a fixed time, tZTO. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 17 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) 7.3.6 Start-Up Operation Upon application of input voltage to the converter, the start up resistance connected to VDD from the bulk capacitor voltage (VBULK) charges the VDD capacitor. During charging of the VDD capacitor, the device supply current is less than 1.5 µA. When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled and the converter starts switching. The peak-primary currents with initial three cycles are limited to IPP(min). This allows sensing any initial input or output faults with minimal power delivery. When confirmed that the input voltage is above the programmed converter turn-on voltage and with no faults detected, the start-up process proceeds and normal power conversion follows. The converter remains in discontinuous conduction mode operation during charging of the output capacitor(s), maintaining a constant output current until the output voltage is in regulation. Initial power-on to the UCC28704 device is achieved by one of the two approaches that are described in Initial Power-On with a Start-Up Resistor and Initial Power-On with A Depletion-Mode FET. 7.3.6.1 Initial Power-On with a Start-Up Resistor A common used initial power-on approach for UCC28704 is to use a start-up resistor, RSTR, to tie VDD to VBLK, as show in Figure 19. With this approach, the VDD pin is connected to a bypass capacitor to ground and a startup resistance to the input bulk capacitor (+) terminal. The VDD turn-on UVLO threshold is 21 V (VVDD(on))and turn-off UVLO threshold is 7.7 V (VVDD(off)), with an available operating range up to 35 V. The USB charging practice requires the output current to operate in constant-current mode from 5 V to typical about 3 V; this is easily achieved with a nominal VDD of approximately 15 V. The additional VDD headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD capacitor in high-load conditions. Also, the wide VDD range provides the advantage of selecting a relatively small VDD capacitor and high-value start-up resistance to minimize no-load stand-by power loss in the start-up resistor. The RSTR value has effect to power-on delay time and no-load standby power losses. Both are usually part of the design specifications. Increase RSTR reduces standby power losses while increases power-on delay time. A typical range of RSTR is from 10 MΩ to 15 MΩ as initial design start point for off-line AC-to-DC adapters where power-on delay time usually requires less than two seconds. Due to the limited voltage rating, RSTR is normally implemented by two or three resistors in series. VBLK CB1 + D1 T1 CB2 NP NS VREG COUT RPL VOUT RSTR VAC UCC28704 D2 VAUX 2 NA VDD CDD Q1 RS1 6 RS2 1 RNTC -t° DRV 3 CS 4 VS RLC NTC/SU RCS GND 5 Figure 19. Power-On with Start-Up Resistor 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Feature Description (continued) 7.3.6.2 Initial Power-On with A Depletion-Mode FET The UCC28704 NTC/SU pin can control an external depletion-mode FET to provide more efficient start-up. This provides a fast start-up time with eliminating the loss associated with the start-up circuit. Therefore, the standby power at no load can be minimized. This gives an alternative method to power on the device initially. As shown in Figure 20, the depletion mode FET HV start-up circuit consists of QST1, QST2, CST, RILIM, and RST1 to RST3. Before VDD reaches VVDD(on), NTC/SU stays low, QST1 turns on, which enables the quick charge of CDD thereby achieving a shorter power-on delay time. After VDD ≥ VVDD(on), NTC/SU starts sourcing 105 µA to turn on QST2 then turns off QST1. This stops QST1 providing current to UCC28704 and minimizes the loss in the start-up circuit. In normal operation when IPP < IPP(max), the device enters wait state in each switching cycle, see Figure 14 for wait state time. During wait state, NTC/SU stops sourcing 105 µA; which turns off QST2 and can potentially cause QST1 to turn on. Hence CST is added to ensure that QST1 is off even during wait state. For reference, RST1 = RST2 = 2 MΩ, RST3 = 100 kΩ, CST = 1 nF, RILIM = 365 kΩ, as an example. To select a depletion-mode FET for QST1, BSS126 or similar can be an option. VBLK CB1 + D1 T1 CB2 NP NS VREG COUT RPL VOUT RLIM QST1 VAC RST1 VAUX UCC28704 D2 2 NA VDD CDD Q1 RS1 6 RST2 DRV 3 CS 4 VS RLC RS2 CST 1 QST2 NTC/SU RST3 RCS GND 5 RNTC -t° Figure 20. Power-On with a Depletion-Mode FET Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 19 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) 7.3.7 Fault Protection There is comprehensive fault protection incorporated into the UCC28704. Protection functions include: • Output Over-Voltage • Input Under-Voltage • Primary Over-Current Fault • CS Pin Open Fault • CS Pin Short-to-GND Fault • VS Pin Fault • External NTC Over-Temperature • Device Internal Over-Temperature • Constant Current Under Voltage Output Shutdown (CCUV) for Soft-Short Protection Output Over-Voltage: The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on VS exceeds 4.67 V, 115% of the nominal regulating level, for three consecutive switching cycles an OV fault is asserted. Once asserted the device stops switching, initiating a UVLO reset and re-start fault cycle. During the fault, the VDD bias current remains at the run current level, discharging the VDD pin to the UVLO turn-off threshold, VVDD(off). After that, the device returns to the start state, VDD now charging to VVDD(on) where switching is initiated. The UVLO sequence repeats as long as the fault condition persists. Input Under-Voltage: The line input run and stop thresholds are determined by current information at the VS pin during the MOSFET on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current through RS1, out of the VS pin, is monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line voltage. From the start state, the sensed VS current, IVSL, must exceed the run current threshold, IVSL(run) (typical 220 µA), within the first three cycles after switching starts as VDD reaches VVDD(on). If it does not, then switching stops and the UVLO reset and re-start fault cycle is initiated. Once running, IVSL must drop below the stop level, IVSL(stop) (typically 80 µA), for three consecutive cycles to initiate the fault response. Primary Over-Current: The UCC28704 always operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS pin is 0.75 V to 0.188 V. If the voltage on CS exceeds the 1.5-V over-current level, any time after the internal leading edge blanking time and before the end of the transformer demagnetization, for three consecutive cycles the device shuts down and the UVLO reset and re-start fault cycle begins. CS Pin Open: The CS pin has a 2-µA minimum pull-up that brings the CS pin above the 1.5-V OC fault level if the CS pin is open. This causes the primary over-current fault after three cycles. CS Pin Short to GND: On the first, and only the first cycle at start-up, the device checks to verify that the VCST(min) threshold is reached at the CS pin within 4 µs of DRV going high. If the CS voltage fails to reach this level then the device terminates the current cycle and immediately enters the UVLO reset and re-start fault sequence. VS Pin: Protection is included in the event of component failures on the VS pin. If the high-side VS divider resistor opens the controller stops switching. VDD collapses to its VVDD(off) threshold, a start-up attempt follows with a single DRV on-time when VDD reaches VVDD(on). The UVLO cycle will repeat. If the low-side VS divider resistor is open then an output over-voltage fault occurs. NTC Over-Temperature: UCC28704 uses the NTC/SU pin to program thermal shutdown threshold with an external NTC thermistor on this pin. The NTC shutdown threshold is 0.95 V with an internal 105-µA current source which results in a 9.05-kΩ thermistor shutdown threshold. If the NTC/SU pin voltage is below 0.95 V at the end of the secondary current demagnetization time for three consecutive cycles switching stops and the UVLO reset and re-start fault sequence is initiated. Device Internal OTP: The internal over-temperature protection threshold is 150°C. If the junction temperature of the device reaches this threshold the device initiates the UVLO reset and re-start fault cycle. If the temperature is still high at the end of the UVLO cycle, the protection cycle repeats. Constant Current Under-Voltage: Output shutdown (CCUV) for soft-short protection. Constant Current UnderVoltage Protection provides detailed description for this fault and fault response. 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Feature Description (continued) 7.3.8 Constant Current Under-Voltage Protection The constant current output under voltage shutdown (CCUV) feature is to provide protection for USB connectors from over-heat or burn-out due to soft-short circuit fault. A partial or soft-short can happen due to the presence of foreign objects at the terminals of the USB upstream facing port, UFP, for example, smartphones with USB Micro-B or USB Type-C connectors. When this happens along with the converter operates in CC mode with enough VDD voltage (VDD > VVDD(off)) available from auxiliary winding, the converter can sustain operation at this condition resulting in a potential USB burn-out condition which is named as soft-short fault to distinguish from a hard-short circuit fault. Traditional over-current protection and short-circuit protection cannot tell a soft-short fault. The UCC28704 provides protection when soft-short circuit fault occurs with the corresponding converter V-I characteristics as shown in Figure 21. As shown in Figure 22, the CCUV feature of UCC28704 detects the operation of the converter under this condition when the controller is operating in CC mode and when the output voltage drops out of regulation, reaching the CCUV threshold. If the controller detects that the VS pin voltage is below VCCUV threshold continuously for 120 ms, then it initiates a CCUV fault and sets the CCUV latch. Once the CCUV latch is set, the controller goes through 3 cycles of VDD-UVLO without any PWM operation and clears the latch on the 4th VDD UVLO power-up. If the CCUV condition still exists, then the controller enters into CCUV fault after 120 ms and repeats the UVLO cycles. This 120-ms time delay allows converter normal start up without triggering the CCUV protection. The flyback design should allow output voltage rise above CCUV protection level under normal operating conditions within 120ms or the CCUV fault may be triggered. +/-5% 5.25 V 5.0 4.75 V Board-End Cable-End Output Voltage (V) 4.0 3.0 3.0 V 2.7 V 2.0 1.0 0 IOCC Output Current (A) Figure 21. Typical Target Output V-I Curves Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 21 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) VBULK CC UV Fault ± Shutdown and Auto - Restart VDD(on) VDD VDD(off) 2.5 mA IVDD 2 mA 1.5 µA 1.5 µA 1.5 µA 1.5 µA 1.5 µA t CCUV_ FAULT_ TIMER xxxxxxxx xxxxxxxx 120 ms DRV CCUV_ FAULT_ LATCH IOCC DRV xxxxx xxxxx VOUT = VOCV VOUT _ CCUV VOUT IOUT Figure 22. Timing Diagram of CCUV and Output Re-Start 22 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Feature Description (continued) 7.3.9 Load Transient Response The UCC28704 can provide excellent transient performance for most load steps. However the response of PSR controller is always limited by the operating frequency of the converter, since the controller only samples or reads the output voltage once every switching cycle. At zero external load, or standby, the operating frequency is set by any preload together with the bias power needed. This frequency, fSW(standby), sets a maximum incremental response delay. The preload can always be adjusted, at the expense of standby power, to increase the standby frequency. The actual response delay depends on the relative timing of the load step within the switching cycle. Thus for a given load step, IOUT(step), the output deviation can be as large as: IOUT(step) 'VOUT COUT u fSW(s tandby) (8) In the case of repeating load transients the situation is aggravated. Whenever the load steps from a modest current level to zero, there is a period of time when there is a slight over-shoot in the output voltage and the control loop saturates and force the converter operating at to its minimum switching frequency, fSW(min), or 1 kHz regardless what preload setting is. If the next positive load step occurs during this time the output deviation will be larger, remembering that fSW(standby) must be > fSW(min). A special transient response algorithm in this controller dynamically adjusts the minimum controlled switching frequency, such that during a mid to high current level condition the loop's minimum switching frequency is raised to fSW(lim), typically 4 kHz. This raised minimum switching frequency is maintained following a load step-down change until the output voltage rises momentarily to 10% above its normal regulating level or has stayed above its normal regulating level for 500 ms. During this time the response to a load step-up change benefits from the decreased response delay afforded by the 4-kHz switching frequency. This is illustrated in Figure 23. Application Curves provides test results and further description in regarding to this technique. NOTE In applications where standby power is not critical the minimum operating frequency of the loop can be kept higher than 4 kHz. In these cases controller will continuously maintain a 4-kHz minimum frequency. Transient response from standby Periodic Transient Response VOUT(nom) x 1.1 VOUT(nom) VOUT IOUT fSW(min) = 4 kHz fSW(min) = 4 kHz fSW(standby) fSW(min) = 1 kHz fSW fSW(standby) fSW(min) Standby Zero Load Steady State Periodic Load Steps Load = 0, 4 kHz > fSW(standby) VOUT Recovers to nom Level, fSW(min) < fSW(standby) Standby Zero Load Steady State Figure 23. Dynamic Load Response Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 23 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 7.4 Device Functional Modes The UCC28704 operates in different modes according to input voltage, VDD voltage, and output load conditions: • At start-up, when VDD is less than the turn-on threshold, VVDD(on) , the device is simply waiting for VDD to reach this threshold while the VDD capacitor is getting charged. • When VDD exceeds VVDD(on), the device starts switching to deliver power to the converter output. The initial 3 switching cycles control the primary-peak current to IPP(min). This allows sensing any initial input or output faults with minimal power delivery. When confirmed with input voltage above predetermined level and no fault conditions, start up process proceeds and normal power conversion follows. The converter will remain in discontinuous current mode operation during charging of the output capacitor(s), maintaining a constant output current until the output voltage reaches its regulation point. – CV mode means that the converter keeps the output voltage constant. When the load current is less than the current limit level, the converter operates in CV mode to keep the output voltage at the regulation level over the entire load and input line ranges. – CC mode means that the converter keeps the output current constant. When the output voltage is below the regulation level, the converter operates in CC mode to limit the output current. – In CC mode, when the output voltage starts to drop below regulation and if it reaches below the CCUV threshold VCCUV, sensed at the VS pin, the controller declares a CCUV fault and disables PWM. The controller initiates a shutdown-restart operation. This protection mode helps avoid USB terminals from getting over-heated and thereby preventing a burn-out condition, which is also called soft-short protection. Detailed description is in Constant Current Under-Voltage Protection. • When operating in CV mode where IPP reaches IPP(max), the UCC28704 operates continuously in the run state. In this state, the VDD bias current is always at IRUN plus the average gate-drive current. • When operating in CV mode where IPP is less than IPP(max), the UCC28704 operates in the wait state between switching cycles and in the run state during a switching cycle. In the wait state, the VDD bias current is reduced to IWAIT after demagnetizing time of each switching cycle to improve efficiency at light loads. This helps reduce light-load power losses, particularly for achieving higher efficiency at 10% and 25% load conditions. • When a dynamic load change occurs in CV mode, the UCC28704 provides an enhanced transient response to reduce load step caused VOUT dip in periodic load change operation. Detailed description is in Load Transient Response. • The device operation can be stopped by the events listed below: – If VDD drops below the VVDD(off) threshold, the device stops switching, its bias current consumption is lowered to ISTART until VDD rises above the VVDD(on) threshold. The device then resumes switching. – If a fault condition is detected, the device stops switching and its bias current consumption becomes IFAULT. This current level discharges VDD to VVDD(off) where the bias current changes from IFAULT to ISTART until VDD rises above the VVDD(on) threshold. – By pulling down NTC/SU pin to below VNTCTH, the device responds similar to that of an NTC fault wherein PWM is disabled and converter is shutdown. On releasing the pull-down on NTC, normal operation into CV mode will be restored. • If a fault condition persists, the operation sequence described above in repeats until the fault condition or the input voltage is removed. Refer to Fault Protection for fault conditions and post-fault operation. 24 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The UCC28704 device is a PSR controller optimized for isolated-flyback AC-to-DC single-output supply applications, typically in the range from 5 W to 25 W, providing constant-voltage (CV) mode control and constant current (CC) mode control for precise output regulation; and to help meet USB-compliant adaptors and charger requirements as well as help meeting DOE Level VI or CoC V5 Tier 2 efficiency performance. The device uses the information obtained from auxiliary winding sensing (VS) to control the output voltage without requiring optocoupler/TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and makes the design more cost effective. 8.2 Typical Application Figure 24 illustrates a typical circuit diagram for AC-to-DC adapter applications. It is a flyback converter with primary-side regulation (PSR) controlled by UCC28704. Such applications widely exist in ac-dc adapters for smartphones, tablet-computers, and e-readers and so forth. The following sub-sections provide critical design formulas. VBLK CB1 + D1 T1 NP NS VREG COUT RPL VOUT RSTR VAC UCC28704 D2 VAUX 2 NA VDD CDD Q1 RS1 6 RS2 1 RNTC -t° DRV 3 CS 4 VS RLC NTC/SU RCS GND 5 Figure 24. Typical Application Circuit Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 25 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Typical Application (continued) 8.2.1 Design Requirements The following table illustrates a typical subset of high-level design requirements for a particular converter of which many of the parameter values are used in the various design equations in this section. Many other necessary design parameters, such as fSW(MAX) and VBULK(min) for example, may not be listed in such a table. These values may be selected based on design experience or other considerations, and may be iterated to obtain optimal results. Table 1. UCC28704 Design Parameters PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VIN AC-line input voltage 85 115/230 265 VRMS fLINE Line frequency 47 50/60 63 Hz PSTBY No-load input power 43 50 mW 5 5.25 VIN = typ, IO = 0A OUTPUT CHARACTERISTICS (MEASUREMENT AT 150-mΩ CABLE-END) VO DC output voltage VIN = typ, IO = 0 to IOR VRIPPLE Output voltage ripple VIN = typ, IO = IOR IOR Output rated current VIN = min to max VIN = typ, IO > IOR 4.75 80 2.0 IOCC Output constant current VCCUV CC UV shutdown interception VIN= typ, IO = IOCC ηAVG Average efficiency VIN= typ, average of 25%, 50%, 75%, and 100% Load 80% η10 Light-load efficiency VIN= typ, 10% load 75% 2.7V < VO < 5V 2.1 2.2 V mV A 2.3 2.7 A V SYSTEMS CHARACTERISTICS fsw Switching frequency TON-Delay 26 Power-on delay time 1 VIN = min IO= IOR (constant resistor load) Submit Documentation Feedback 65 kHz 1.8 s Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 8.2.2 Detailed Design Procedure This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the UCC28704 controller. Please refer to the Figure 24 for circuit details and section Device Nomenclature for variable definitions used in the applications equations below. 8.2.2.1 VDD Capacitance, CDD The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the UCC28704. The total output current available to the load and to charge the output capacitors is the constantcurrent regulation target. The equation below assumes the output current of the flyback is available to charge the output capacitance until the minimum output voltage VOCC is achieved. The gate-drive current depends on particular MOSFET to be used. If with an estimated 1.0 mA of gate-drive current, CDD is determined by Equation 9. C u VOCC IRUN 1.0mA u OUT I OCC CDD VDD(on),min VDD(off),max (9) 8.2.2.2 VDD Start-Up Resistance, RSTR Once the VDD capacitance is known, the start-up resistance from VBULK to achieve the power-on delay time (tSTR) target can be determined. RSTR ISTART 2 u VIN(min) VDD(on) u CDD tSTR (10) 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input rms voltage, and minimum AC input frequency are used to determine the input capacitance requirement. Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target. An initial estimate of 84% can be assumed for the full-load efficiency for a 5-V/2-A design. VOCV u IOCC PIN K (11) Equation 12 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance. CBULK § § VBULK(min) · · 1 ¸¸ u arcsin ¨ PIN u ¨ 0.5 ¨ 2 u VIN(min) ¸ ¸ S ¨ © ¹¹ © 2 2 2VIN(min) VBULK(min) u fLINE (12) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 27 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 8.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time. Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. DMAX can be determined using Equation 13. §t · DMAX 1 ¨ R u fMAX ¸ DMAGCC © 2 ¹ (13) Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC28704 at 0.475. The total voltage on the secondary winding needs to be determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V USB charger applications, a turns ratio range of 12 to 15 is typically used for a 10-W design. DMAX u VBULK(min) NPS(max) DMAGCC u VOCV VF VOCBC (14) NPS is determined also with other design factors such as primary MOSFET, secondary rectifier diode, as well as secondary MOSFET if synchronous rectifier is used. Once an optimum turns-ratio is determined from a detailed transformer design, use this ratio for the following parameters. The UCC28704 controller constant-current regulation is achieved by maintaining DMAGCC = 0.475 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current limit. Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 2-A charger example, bias power of 0.5% is a good estimate. An overall transformer efficiency of 94.5% is a good estimation of assuming 2% leakage inductance, 3% core and winding loss, and 0.5% bias power. RCS is used to program the primary-peak current with Equation 15: VCCR u NPS u KXFMR RCS 2 u IOCC (15) The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency, output and transformer efficiency are included in Equation 16. Initially determine transformer primary current. Initially the transformer primary current should be determined. Primary current is simply the maximum current sense threshold divided by the current sense resistance. VCST(max) IPP(max) RCS (16) LP 2 u VOCV VF VOCBC u IOCC 2 KXFMR u IPP(max) u fMAX (17) The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC28704. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs. The VOCC lower than CCUV level is not achievable because the CCUV protection is going to be triggered first. VDD(off) VFA NAS VOCC VF (18) 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 8.2.2.5 Transformer Parameter Verification The transformer turns-ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these should be reviewed. The UCC28704 controller requires a minimum on time of the MOSFET (tON) and minimum DMAG time (tDMAG(min)) of the secondary rectifier in the high line, minimum-load condition. The selection of fMAX, LP and RCS affects the minimum tON and tDMAG. The secondary rectifier and MOSFET voltage stress can be determined by the equations below. VREV VIN(max) u 2 NPS VOCV VOCBC (19) For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included. VDSPK VIN(max) u 2 VOCV VF VOCBC u NPS VLK (20) The following equations are used to determine for the minimum tON target of 0.3 µs and minimum de-mag time, tDMAG(min), target of 1.7 µs. The minimum tDMAG(min) target needs to be typically 2.45 µs when a synchronous rectifier is used on the secondary-side instead of a Schottky diode rectifier. Additional details are provided in Design Considerations in Using with Synchronous Rectifiers. IPP(max) LP tON(min) u K AM VIN(max) u 2 (21) tDMAG(min) tON(min) u VIN(max) u 2 NPS u VOCV VF (22) 8.2.2.6 VS Resistor Divider, Line Compensation, and NTC The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1 is initially determined based on the transformer auxiliary to primary turns-ratio and the desired input voltage operating threshold. RS1 VIN(run) u 2 NPA u IVSL(run) (23) The low-side VS pin resistor is selected based on desired VO regulation voltage. IVSL(run) is VS pin run current with a typical value 220 µA for a design. RS1 u VVSR RS2 NAS u VOCV VF VVSR (24) The UCC28704 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected gate drive and MOSFET turn-off delay. Assume a 50-ns internal delay in the UCC28704. KLC u RS1 u RCS u (tD tGATE _ OFF ) u NPA RLC LP (25) The NTC function on NTC/SU-pin is to program with a NTC resistor for the desired over-temperature shutdown threshold. The shut-down threshold is 0.95 V with an internal 105-μA current source which results in a 9.05-kΩ thermistor shut-down threshold. The SU function on NTC/SU-pin is described in Initial Power-On with A Depletion-Mode FET. Pulling down this pin to GND stops switching and can be used for remote enable and disable control. This pin should be left floating if not used. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 29 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 8.2.2.7 www.ti.com Standby Power Estimate Assuming no-load standby power is a critical design parameter, determine the estimated no-load power based on target converter maximum switching frequency and output power rating. The following equation estimates the stand-by power of the converter. POUT u fMIN PSB _ CONV # K u K 2AM u fMAX (26) For a typical USB charger application, the bias power during no-load is approximately 2.1 mW. This is based on 21-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias power estimated at 2.1 mW. Preload resistor value is estimated in Equation 27 : RPL 2 VOCV PSB _ CONV 2.1mW (27) Typical start-up resistance values for RSTR range from 10 MΩ to 15 MΩ to achieve less than 2-s start-up time. The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 VDC. PRSTR (VBULK VDD )2 RSTR (28) For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the start-up resistance and converter stand-by power loss. PSB PSB _ CONV PRSTR PSNBR (29) 8.2.2.8 Output Capacitance The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a load-step transient of 0 mA to 500 mA . Equation 30 assumes that the switching frequency can be at the UCC28704 minimum of fSW(min). COUT § 1 ITRAN ¨ ¨ fSW(min) © 'VO · 50Ps ¸ ¸ ¹ (30) Equation 5 should be observed together with Equation 30 for stability consideration when determine COUT. Another consideration of the output capacitor(s) is the ripple voltage requirement. The output capacitors and their total ESR are the main factors to determine the output voltage ripple. Equation 31 provides a formula to determine required ESR value RESR, and Equation 31 provides a formula to determine required capacitance. The total output ripple is the sum of these two parts with scale factors and 10mV to consider other noise as shown in Equation 33, RESR COUT VRIPPLE 1 IPP(max) u NPS u VRIPPLE _ R 2 LP u IPP(max) 4 u (VOCV VCBC ) (31) u 1 VRIPPLE _ C 0.81u VRIPPLE _ R 1.15 u VRIPPLE _ C 10mV (32) (33) Example: if require VRIPPLE = 70 mV, assume 0.81 × VRIPPLE_R = 1.15 × VRIPPLE_C = 30 mV, then RESR = 4.05 mΩ, and COUT = 643 µF, with assumption of LP = 700 µH, IPP(max) = 0.713 A, NPS = 13, VOCV = 5 V, VCBC = 0.3 V. 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 8.2.2.9 Design Considerations in Using with Synchronous Rectifiers Special design considerations need to be observed when using synchronous rectifiers (SR) with the UCC28704. Figure 14 depicts the de-mag time partition. When using UCC28704 with SR, a portion of the de-mag time needs to be reserved for tbw, as shown in Figure 25, which is the body diode conduction time when SR MOSFET turns off before the de-mag time ends. tLK_RESET tBW VS ring p-p (scaled) RS2 / (RS1 + RS2) 0V tDM_BLANK tDMAG tSW Figure 25. Auxiliary Waveform Details The critical parameter dictating the maximum switching frequency when UCC28704 is used with an SR is determined based on tDMAG(min). The tDMAG(min) needs to be typically 2.45 µs including the SR bump width (tBW) is 750 ns. The 750-ns (tBW) is required for the internal circuit to filter out the SR bump change caused by MOSFET body diode conduction that is sensed on the VS pin waveform. The corresponding switching frequency measured at starting point of constant current operation should not be greater than 55 kHz. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 31 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 85.0% 6.0 80.0% 5.0 75.0% 4.0 Vout (V) 10W (5V/2A) Efficiency 8.2.3 Application Curves Board-End (115Vac) Board-End (230Vac) 0.15: Cable-End (115Vac) 0.15: Cable-End (230Vac) 70.0% 65.0% 3.0 Board-End Cable-End (150m:) 2.0 1.0 60.0% 10% 20% 30% 40% 50% 60% 70% Output Power 80% 90% 100% D026 0.0 0.0 Figure 26. Efficiency VDD VDD(on) (1) (2) (3) (4) 0.2 0.5 0.8 1.0 1.2 Iout (A) 1.5 1.8 2.0 2.2 D027 Figure 27. Output V-I Curves 120 ms VDD(off) VOUT IOUT 10 ms VOUT 2A fsw fsw > 4 kHz IOUT 4 kHz DRV Figure 28. Soft-Short Protection 1.1 x VOCV Figure 29. Response to Load Step-Down VOUT VOCV (V) < 4 kHz 5.45 V 4.44 V 10 ms IOUT 2A 0A 200 ms Figure 31. Typical Output Load Transient Response Figure 30. Typical VOUT Start Up at No Load 32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Figure 26 shows efficiency test result based on a 5-V/2-A, 10-W adapter using UCC28704. The efficiency performance exceeds CoC V5 Tier 2 (79% for average and 69.7% for a 10%-load) and DOE Level VI (78.7% for average) measured at 150-mΩ cable-end. As comparison, the measured result at board-end shown in Figure 26. Figure 27 shows typical VI curves from the same 10-W board. The board-end output voltage has cable compensation to achieve cable-end output voltage with very well-regulated result in constant voltage mode operation range. In constant current mode operation, the result depicts a good constant current operation from the vertical line of current along with the output voltage drop until reaches CCUV. Notice that the CCUV difference at board-end and at cable-end is about 300 mV that is the same as cable compensation voltage at full load. Figure 28 illustrates the timing diagram when the operation is in CCUV. The response of the controller to a softshort circuit is shown wherein VOUT reaches to less than the VCCUV threshold. The converter is in CC mode and any additional load tending higher than IOCC causes VOUT to drop below regulation due to the soft-short. As VOUT is able to sustain VDD above its UVLO and the soft-short circuit condition persists continuously for 120 ms, the CCUV fault is initiated. The waveform shows the 3 VDD UVLO cycles that the controller goes through after the fault and it attempts to restart on the 4th VDD UVLO cycle with the response repeating due to the sustained soft short-circuit fault. The 120 ms is to blank any possible noise interference which may cause unnecessary CCUV protection to interrupt a normal operation. Figure 29 provides the test result to explain the enhanced load transient scheme that is described in Load Transient Response. When the load steps down and demands a lower switching frequency, the controller clamps the switching frequency at 4 kHz until either the output has gone above its regulation level for more than 500 ms or has reached more than 10% of its VOCV. This enables the converter to have a better response to an ensuing load step up from the reduced response time. If either of the condition is met, then the controller starts to adjust the fSW below 4 kHz if the converter operation demands such a frequency. Associated to this enhancement, the output voltage may experience a 10% overshoot as shown in Figure 29 during a load step-down or as shown in Figure 30 during a no-load start up. Figure 31 shows the output load transient with load step change between 0-A and 2-A full load. 8.3 Do's and Don'ts • • • • • • • During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown threshold. Also, at no-load, keep the average switching frequency greater than 1.5 × fSW(min) typical to avoid a rise in output voltage. RLC needs to be adjusted based on no-load operation accounting for both low-line and high-line operation.. Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS to GND causes the output voltage to increase, while leakage current from VDD to VS can cause output voltage to increase. If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher to minimize reduction of capacitance due to DC-bias voltage and temperature variation. Do not use leaky components if low stand-by input power consumption is a design requirement. Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and disrupt regulation. Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the waveform by the VS divider ratio. Do follow Equation 5, Equation 30, Equation 31 to Equation 33 for COUT. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 33 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 9 Power Supply Recommendations The UCC28704 is intended for AC-to-DC adapters and chargers with universal input voltage range of 85 VRMS to 265 VRMS, 47 Hz to 63 Hz, using flyback topology. It can also be used in other applications and converter topologies with different input voltages. Be sure that all voltages and currents are within the recommended operating conditions and absolute maximum ratings of the device. 10 Layout 10.1 Layout Guidelines In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout. In Figure 32, a typical 5-V/2-A USB adapter design schematic is shown in Figure 32. • Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in Figure 24) close to the VS pin. • Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop (b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority. As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b). • The RLC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt) coupled onto this resistor, it is better to place RLC closer to the controller and avoid nearby the MOSFET. • To improve thermal performance increase the copper area connected to GND pins. T1 VBLK CB1 + CB2 NP (a) L RSTR VAC RSN1 N 2 + RPL VOUT - RSN2 Optional, short across if not used Q1 VDD RG1 CDD RS1 6 RS2 (e) COUT UCC28704 D2 VAUX NS (C) DSN1 DIN NA CSN1 D1 DRV 3 CS 4 (B) VS (d) 1 RNTC -t° NTC/SU RLC Isolation Boundary RCS CY GND 5 Figure 32. 10-W, 5-V/2-A USB Adapter Schematics 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 10.2 Layout Example Figure 33 demonstrates a 10-W, 5-V/2-A, layout with trade-offs to minimize the loops while effectively placing components and tracks for low noise operation on a single-layer printed circuit board. In addition to the consideration of minimal loops, one another layout guideline is always to use the device GND as reference point. This applies to both power and signal to return to the device GND pin (pin 5). CO1 D1 Loop (e) Transformer Isolation Boundary Loop (c) Loop (a) + VOUT Y-Cap Loop (d) Loop (b) UCC28704 CB2 Input Rectifier DIN Figure 33. Layout Example Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 35 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.1.1.1 Capacitance Terms in Farads CBULK total input capacitance of CB1 and CB2. CDD minimum required capacitance on the VDD pin. COUT minimum output capacitance required. 11.1.1.2 Duty Cycle Terms DMAGCC secondary diode conduction duty cycle in CC, 0.475. DMAX maximum MOSFET on-time duty cycle. 11.1.1.3 Frequency Terms in Hertz fLINE minimum line frequency. fMAX target full-load maximum switching frequency of the converter. fMIN minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device. fSW(lim) switching frequency in transient after a load step-down change fSW(min) minimum switching frequency (see the Electrical Characteristics table) fSW(max) maximum switching frequency (see the Electrical Characteristics table) fSW(standby) switching frequency before load change at light load condition 11.1.1.4 Current Terms in Amperes IOCC converter output constant-current target. IOR converter rated output current. IPP(max) maximum transformer primary current. ISTART start-up bias supply current (see the Electrical Characteristics table). ITRAN required positive load-step current. IVSL(run) VS pin run current (see the Electrical Characteristics table). IWAIT VDD bias current during the Wait-state . (see the Electrical Characteristics table). 11.1.1.5 Current and Voltage Scaling Terms KAM maximum-to-minimum peak primary current ratio (see the Electrical Characteristics table). KCo stability factor of 100, used in calculations for COUT. KLC current-scaling constant (see the Electrical Characteristics table). 36 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 Device Support (continued) 11.1.1.6 Transformer Terms LP transformer primary inductance. LS transformer secondary inductance. NAS transformer auxiliary-to-secondary turns ratio. NPA transformer primary-to-auxiliary turns ratio. NPS transformer primary-to-secondary turns ratio. NA tnumber of turns of transformer auxiliary winding. NP tnumber of turns of transformer primary winding. NS tnumber of turns of transformer secondary winding. 11.1.1.7 Power Terms in Watts PIN converter maximum input power. POUT full-load output power of the converter. PRSTR VDD start-up resistor power dissipation. PSB total stand-by power. PSB_CONV PSB minus start-up resistor and snubber losses. 11.1.1.8 Resistance Terms in Ω RCS primary current programming resistance RESR total ESR of the output capacitor(s). RPL preload resistance on the output of the converter. RS1 high-side VS pin resistance. RS2 low-side VS pin resistance. RSTR Start-up resistor connected between bulk voltage and VDD 11.1.1.9 Timing Terms in Seconds tD current-sense delay. tDMAG(min) minimum secondary rectifier conduction time. tGATE_OFF primary-side main MOSFET turn-off time. tON(min) minimum MOSFET on time. tR period of the resonant ringing after tDMAG. tSTR power-on delay time due to charge-up time needed for VDD capacitance CDD. tZTO tZTO: zero-crossing timeout delay without zero-crossing detected on VS (see the Electrical Characteristics table). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 37 UCC28704 SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Device Support (continued) 11.1.1.10 Voltage Terms in Volts VBLK or VBULK bulk capacitor voltage. VBULK(max) highest bulk capacitor voltage for stand-by power measurement. VBULK(min) minimum voltage on CB1 and CB2 at full power. VBULK(run) converter start-up (run) bulk voltage. VCBC cable compensation voltage at the output of board-end at full load. VCCR constant-current regulating voltage (see the Electrical Characteristics table). VCCUV VS threshold for constant-current output voltage shutdown (see the Electrical Characteristics table). VCST(max) CS pin maximum current-sense threshold (see the Electrical Characteristics table). VCST(min) CS pin minimum current-sense threshold (see the Electrical Characteristics table). VVDD(off) UVLO turn-off voltage (see the Electrical Characteristics table). VVDD(on) UVLO turn-on voltage (see the Electrical Characteristics table). VF secondary rectifier forward voltage drop at near-zero current. VFA auxiliary rectifier forward voltage drop. VLK estimated leakage inductance energy reset voltage. VOCV regulated output voltage of the converter. VOCC target lowest converter output voltage in constant-current regulation. VRIPPLE output peak-to-peak ripple voltage at full-load. VVSR CV regulating level at the VS input (see the Electrical Characteristics table). 11.1.1.11 AC Voltage Terms in VRMS VIN(max) maximum input voltage to the converter. VIN(min) minimum input voltage to the converter. VIN(run) converter input start-up (run) voltage. 11.1.1.12 Efficiency Terms η converter overall efficiency. η10 efficiency at 10% load. ηAVG arithmetic average of efficiency at load level 25%, 50%, 75%, and 100% . ηXFMR transformer primary-to-secondary power transfer efficiency. 38 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 UCC28704 www.ti.com SLUSCA8A – FEBRUARY 2016 – REVISED FEBRUARY 2016 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: Using the UCC28704-1EVM-724, Evaluation Module, SLUUBF1 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: UCC28704 39 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC28704DBVR-1 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7041 UCC28704DBVT-1 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7041 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of