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UCC28730
SLUSBL5A – FEBRUARY 2015 – REVISED JUNE 2019
UCC28730 Zero-Power Standby PSR Flyback Controller
With CVCC and Wake-Up Monitoring
1 Features
3 Description
•
The UCC28730 isolated-flyback power supply
controller provides Constant-Voltage (CV) and
Constant-Current (CC) output regulation without the
use of an optical coupler, and wake-up signal
detection to improve transient response to large load
steps. A minimum switching frequency of 30 Hz
facilitates achieving less than 5 mW of no-load
power. This device processes information from the
primary power switch and an auxiliary flyback winding
for precise control of output voltage and current. The
wake-up monitoring works with a secondary-side
alarm device such as the UCC24650 to deliver rapid
response to heavy load steps using minimal output
capacitance.
Enables Zero-Power (1.2 µs is achieved.
t ON (min ) =
tDMAG (min )
LP
VIN (max ) × ¾2
×
IPP (max )
K AM
(18)
t ON (min ) × VIN (max ) × ¾2
=
NPS × :VOCV + VF ;
(19)
8.2.2.5 Output Capacitance
With ordinary flyback converters, the output capacitance value is typically determined by the transient response
requirement for a specific load step, ITRAN, sometimes from a no-load condition. For example, in some USB
charger applications, there is requirement to maintain a transient minimum VO of 4.1 V with a load-step of 0 mA
to 500 mA. Equation 20 below assumes that the switching frequency can be at the UCC28730 minimum of
fSW(min).
COUT (No _Wake )
1
+ 150 Jsp
ITRAN l
fSW (min )
R
VO¿
(20)
This results in a COUT value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum
switching frequency. However, the wake-up feature allows the use of a much smaller value for COUT because the
wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the
output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730
with a wake-up signal when it detects a -3% droop in output voltage.
COUT R
1.2 × ITRAN
:dVOUT ¤dt;
where
•
(dVOUT/dt) is the slope at which the UCC24650 must detect the VOUT droop. Use a slope factor of 3700 V/s or
lower for this calculation.
(21)
The UCC28730 incorporates internal voltage-loop compensation circuits so that external compensation is not
necessary, provided that the value of COUT is high enough. The following equation determines a minimum value
of COUT necessary to maintain a phase margin of about 40 degrees over the full-load range. KCo is a
dimensionless factor which has a value of 100.
COUT R K Co ×
IOCC
VOCV × fMAX
(22)
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Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement,
VRIPPLE(max), which is reviewed based on the maximum output load, the secondary-peak current, and the
equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are
the change in VOUT due to the charge and discharge of COUT between each switching cycle and the step in VOUT
due to the ESR of COUT. TI recommends an initial allocation of 33% of VRIPPLE(max) to ESR, 33% to COUT, and the
remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and
other random contributors. In Equation 23, a margin of 50% is applied to the capacitor ESR requirement to allow
for aging. In Equation 24, set ΔVCQ = 0.33 x VRIPPLE(max) to determine the minimum value of COUT with regard to
ripple voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be
adjusted accordingly.
ESR Q
COUT
0.33 × VRIPPLE (max )
× 0.50
IPP (max ) × NPS
(23)
IOCC
R
¿VCQ × fMAX
(24)
Choose the largest value of the previous COUT calculations for the minimum output capacitance. If the value of
COUT becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to
as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.
8.2.2.6 VDD Capacitance, CVDD
A capacitor is required on VDD to provide:
1. Run-state bias current during start-up while VDD falls toward UVLO, until VOCC is reached,
2. Wait-state bias current between steady-state low-frequency power cycles and
3. Wait-state bias current between minimum-frequency power cycles while VOUT recovers from a transient
overshoot.
Generally, the value to satisfy (3) also satisfies (2) and (1), however the value for (1) may be the largest if the
converter must provide high output current at a voltage below VOCC during power up.
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation, VOCC. At that point, the auxiliary winding can
sustain the bias voltage to the UCC28730 above the UVLO shutdown threshold. The total current available to
charge the output capacitors and supply an output load and is the constant-current regulation target, IOCC.
Equation 25 assumes that all of the output current of the flyback is available to charge the output capacitance
until the minimum output voltage is achieved. For margin, there is an estimated 1 mA of average gate-drive
current added to the run current and 1 V added to the minimum VDD.
COUT × VOCC
IOCC
R
VVDD (on ) F kVVDD (off ) + 1 Vo
:IRUN + 1 mA; ×
CVDD
(25)
At light loads, the UCC28730 enters a Wait-state between power cycles to minimize bias power and improve
efficiency. Equation 26 estimates the minimum capacitance needed to obtain a target maximum ripple voltage on
VDD (VVDD(maxΔ) < 1 V, for example) during the Wait state, which occurs at the lowest possible switching
frequency.
CVDD R
IWAIT
VVDD (max ¿) × fSW (min )
(26)
Choose the largest value of the previous CVDD calculations for the minimum VDD capacitance.
8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter. Also, the highside divider resistor, RS1, determines the line voltage at which the controller enables continuous DRV operation.
RS1 is initially determined based on the transformer primary to auxiliary turns ratio and the desired input voltage
operating threshold.
R S1 =
26
¾2 × VIN (run )
NPA × IVSL (run )
(27)
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SLUSBL5A – FEBRUARY 2015 – REVISED JUNE 2019
The low-side VS divider resistor, RS2, is selected based on the desired constant-voltage output regulation target,
VOCV.
R S2 =
R S1 × VVSR
NAS × :VOCV + VF ; F VVSR
(28)
The UCC28730 can maintain tight constant-current regulation over input line by utilizing the line compensation
feature. The line compensation resistor value, RLC, is determined by various system parameters and the
combined gate-drive turn-off and MOSFET turn-off delays, tD. Assume a 50-ns internal propagation delay in the
UCC28730.
R LC =
K LC × R S1 × R CS × NPA × t D
LP
(29)
The UCC28730 provides adjustable cable compensation of up to approximately +8% of VOCV by connecting a
resistor between the CBC terminal and GND. This compensation voltage, VOCBC, represents the incremental
increase in voltage, above the nominal no-load output voltage, needed to cancel or reduce the incremental
decrease in voltage at the end of a cable due to its resistance. The programming resistance required for the
desired cable compensation level at the converter output terminals can be determined using the equation below.
As the load current changes, the cable compensation voltage also changes slowly to avoid disrupting control of
the main output voltage. A sudden change in load current will induce a step change of output voltage at the end
of the cable until the compensation voltage adjusts to the required level. Note that the cable compensation does
not change the overvoltage protection (OVP) threshold,VOVP (see Electrical Characteristics), so the operating
margin to OVP is less when cable compensation is used. If cable compensation is not required, CBC may remain
unconnected.
R CBC =
VCBC (max )
× 3 k3 F 28 k3
VVSR
VOCBC ×
:VOCV + VF ;
(30)
8.2.2.8 VS Wake-Up Detection
The amplitude of the wake-up signal at the VS input must be high enough to be detected. This signal, which
originates on the secondary winding, is limited by the impedances of the wake-up signal driver and the L-C
resonant tank of the transformer windings. The signal is further attenuated by the VS divider resistors. To
maximize the wake-up signal amplitude, the pulse width, tWAKE, of the wake-up signal should be at least 1/4wavelength of the switched-node resonant frequency, fRES. The resonant frequency depends on the primary
magnetizing inductance and the total equivalent capacitance at the switching node, that is, the primary-side
MOSFET drain node. The switched-node capacitance, CSWN, includes the MOSFET COSS, the transformer
winding capacitance, and all other stray circuit capacitance attached to the MOSFET drain. Use Equation 31 to
determine fRES. Conversely, if fRES is known by experience or measurement, CSWN can be derived from
Equation 31.
1
fRES =
tN¥LP × CSWN
(31)
Since the wake-up pulse width is typically fixed by the driver device, such as the UCC24650, maximum signal
strength is obtained when Equation 32 is true. Since LP is generally fixed by other system requirements, only
CSWN can be reduced to increase fRES, if necessary.
fRES R
1
4 × t WAKE
(32)
Equation 33 is used to ensure that there is sufficient amplitude at the VS input to reliably trigger the wake-up
function, where RWAKE_TOT is the total secondary-side resistance of the wake-up signal driver and any series
resistance. An over-drive of 15 mV is added to the wake-up threshold level for margin.
LP
¨
R
CSWN
2
R WAKE _TOT × NPS
f
VOUT × NAS
F 1j
R
+
kVWU (low ) 15mVo × @R S1 + 1A
(33)
S2
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8.2.3 Application Curves
The following figures indicate the transient response of a 5-V, 10-W flyback converter which receives a pulsed
step-load of 2 A while operating in the no-load stand-by condition. Figure 27 indicates the no-load stand-by input
power consumption achieved by this converter over the full AC input range. Zero-Power operation is achieved
while retaining fast transient response to a full load step.
VOUT with 5-V offset
5.1 V ±5% COUT = 540 µF
Output Ripple
214-mV Droop
2-A Load Step
2-A Load Step
Switching Pulses
Switching Pulses
Figure 24. 2-A Load Step During Stand-by Operation
Figure 25. Transient Response Detail for 2-A Load Step
5
VOUT with 5-V offset
4.5
Input Power (mW)
4
2-A Load Step
3.5
3
2.5
2
1.5
1
0.5
Wake-Up Pulse
0
85
Switching Pulses
Figure 26. Wake-Up Pulse Triggering Response from
UCC28730 Primary-Side Controller
28
135
185
Input Voltage (VAC)
235
265
D003
Figure 27. No-Load Input Power Consumption for a 5-V,
10-W Converter
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8.3 Do's and Don'ts
•
•
•
•
•
During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown
threshold. Also, at no-load, keep the average switching frequency, , greater than 2 x fSW(min) to avoid a
rise in output voltage.
Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS
to GND causes the output voltage to increase, while leakage current from HV or VDD to VS causes output
voltage to decrease.
If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher
to minimize reduction of capacitance due to dc-bias voltage and temperature variation.
Do not use leaky components if less than 5-mW stand-by input power consumption is a design requirement.
Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and
disrupt regulation. Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the
waveform by the VS divider ratio.
9 Power Supply Recommendations
The UCC28730 is intended for AC-to-DC adapters and chargers with input voltage range of 85 VAC(rms) to 265
VAC(rms) using flyback topology. It can also be used in other applications and converter topologies with different
input voltages. Be sure that all voltages and currents are within the recommended operating conditions and
absolute maximum ratings of the device.
The DRV output normally begins PWM pulses approximately 55 µs after VDD exceeds the turn-on threshold
VVDD(on). Avoid excessive dv/dt on VDD. Positive dv/dt greater than 1 V/µs may delay the start of PWM .
Negative dv/dt greater than 1 V/µs on VDD which does not fall below the UVLO turn-off threshold VVDD(off) may
result in a temporary dip in the output voltage.
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10 Layout
10.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following
guidelines for PCB layout.
1. Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in Figure 24
through Figure 27) close to the VS pin.
2. TI recommends to connect the HV input to a non-switching source of high voltage, not to the MOSFET drain,
to avoid injecting high-frequency capacitive current pulses into the device.
3. Arrange the components to minimize the loop areas of the switching currents as much as possible. These
areas include such loops as the transformer primary winding current loop, the MOSFET gate-drive loop, the
primary snubber loop, the auxiliary winding loop and the secondary output current loop.
10.2 Layout Example
The partial layout example of Figure 28 demonstrates an effective component and track arrangement for lownoise operation on a single-layer printed circuit board. Actual board layout must conform to the constraints on a
specific design, so many variations are possible.
AUX
Winding
PRI
Winding
TRANSFORMER
CVDD1
DVDD
G
CVDD2
RVDD
RS1
VDD
D
To Bulk Cap +
S
To Bulk Cap ±
Q1
HV
RCS1
RS2
VS
UCC28730
RCBC
CBC
DRV
RG
GND
CS
RLC
0-
RCS2
RCS3
Jumper
To Bulk Capacitor +
Figure 28. UCC28730 Partial Layout Example
30
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For design tools see the UCC28730 Design Calculator and UCC28730 & UCC24650 PSpice Transient Model.
11.1.2 Device Nomenclature
11.1.2.1 Capacitance Terms in Farads
• CBULK: total input capacitance of CB1 and CB2
• CVDD: minimum required capacitance on the VDD pin
• COUT: minimum required output capacitance
11.1.2.2 Duty-Cycle Terms
• DMAGCC: secondary diode conduction duty-cycle constant while in CC mode, = 0.432
• DMAX: maximum allowable MOSFET on-time duty-cycle
• NHC: Number of half-cycles of the AC line frequency during a line drop-out
11.1.2.3 Frequency Terms in Hertz
• fLINE: minimum line frequency
• fMAX: target full-load maximum switching frequency of the converter
• fMIN: actual minimum switching frequency of the converter
• fSW(max): maximum switching frequency capability of the controller (see Electrical Characteristics)
• fSW(min): minimum switching frequency capability of the controller (see Electrical Characteristics)
11.1.2.4 Current Terms in Amperes
• IOCC: converter output constant-current target
• IPP(max): maximum transformer primary peak current
• ISTART: VDD bias current before start-up (see Electrical Characteristics)
• ITRAN: required positive load-step current
• IWAIT: VDD bias current during the Wait-state (see Electrical Characteristics)
• IVSL(run): VS pin run current (see Electrical Characteristics)
11.1.2.5 Current and Voltage Scaling Terms
• KAM: ratio of maximum to minimum primary current peak amplitude (see Electrical Characteristics)
• KLC: current scaling constant for line compensation (see Electrical Characteristics)
• KCo: stability factor of 100, used in calculations for COUT
11.1.2.6 Transformer Terms
• LP: transformer primary inductance
• NAS: transformer auxiliary to secondary turns ratio
• NPA: transformer primary to auxiliary turns ratio
• NPS: transformer primary to secondary turns ratio
11.1.2.7 Power Terms in Watts
• PIN: maximum input power of the converter at full-load
• POUT: output power of the converter at full-load
• PSTBY: total input power of the converter in stand-by condition
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Device Support (continued)
11.1.2.8 Resistance Terms in Ω
• RCS: primary-current programming resistance
• RESR: total ESR of the output capacitor(s)
• RPL: pre-load resistance on the output of the converter
• RS1: high-side resistance on VS input
• RS2: low-side resistance on VS input
11.1.2.9 Timing Terms in Seconds
• tD: total current-sense delay including MOSFET turn-off delay; add 50 ns to MOSFET delay
• tDMAG(min): minimum secondary rectifier conduction time (transformer demagnetization time)
• tON(min): minimum MOSFET on time
• tR: period of the resonant ringing after tDMAG
11.1.2.10 DC Voltage Terms in Volts
• VBULK: maximum bulk-capacitor voltage for standby power measurement
• VBULK(min): minimum valley voltage on bulk capacitor(s) at full power
• VOCBC: target cable compensation voltage at the output terminals
• VCBC(max): maximum voltage at the CBC pin at maximum output current (see Electrical Characteristics)
• VCCR: constant-current regulating factor voltage (see Electrical Characteristics)
• VCST(max): CS pin maximum current-sense threshold (see Electrical Characteristics)
• VCST(min): CS pin minimum current-sense threshold (see Electrical Characteristics)
• VVDD(off): UVLO turn-off threshold voltage (see Electrical Characteristics)
• VVDD(on): UVLO turn-on threshold voltage (see Electrical Characteristics)
• VVDD(maxΔ): maximum drop in VDD voltage between switching cycles during Wait state
• VOΔ: output voltage drop allowed during an output load transient
• VDSPK: peak MOSFET drain-to-source voltage at high line
• VF: secondary rectifier forward voltage drop at near-zero current
• VFA: auxiliary rectifier forward voltage drop
• VLK: estimated reset voltage of primary leakage inductance energy
• VOCV: regulated output voltage of the converter
• VOCC: target lowest output voltage in constant-current regulation
• VREV: peak reverse voltage on the secondary rectifier
• VRIPPLE: output peak-to-peak ripple voltage at full-load
• VVSR: constant-voltage regulating level at the VS input (see Electrical Characteristics)
• ΔVCQ: allowable change in COUT voltage due to load discharge between switching cycles
11.1.2.11 AC Voltage Terms in Volts
• VIN(max): maximum AC input voltage to the converter
• VIN(min): minimum AC input voltage to the converter
• VIN(run): converter start-up (run) input voltage
11.1.2.12 Efficiency Terms
• ηSB: estimated efficiency of the flyback converter at no-load condition. For reference, 50% to 70% is a good
initial estimate range for a 5-V, 2-A output.
• η: overall efficiency of the converter at full rated output power
• ηXFMR: power transfer efficiency of the transformer
32
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Choosing Standard Recovery Diode or Ultra-Fast Diode in Snubber
• Control Challenges for Low Power AC/DC Converters
• Troubleshooting TI PSR Controllers
• UCC24650 200-V Wake-Up Monitor for Fast Transient PSR
• Using the UCC28730EVM-552 10-W Adaptor Module With PSR and Wake-Up Monitor
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28730D
ACTIVE
SOIC
D
7
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28730
UCC28730DR
ACTIVE
SOIC
D
7
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28730
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of