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UCC28910
UCC28911
SLUS769D – JULY 2013 – REVISED DECEMBER 2016
UCC28910, UCC28911 High-Voltage Flyback Switcher
with Primary-Side Regulation and Output Current Control
1 Features
3 Description
•
The UCC28910 and UCC28911 are high-voltage
flyback switchers that provide output voltage and
current regulation without the use of an optical
coupler. Both devices incorporate a 700-V power FET
and a controller that process operating information
from the flyback auxiliary winding and power FET to
provide a precise output voltage and current control.
The integrated high-voltage current source for startup
that is switched off during device operation, and the
controller current consumption is dynamically
adjusted with load. Both enable the very low stand-by
power consumption.
1
•
•
•
•
•
•
•
Constant-Voltage (CV) and Constant-Current (CC)
Output Regulation Without Optical-Coupler
±5% Output Voltage Regulation Accuracy
±5% Output Current Regulation With AC Line and
Primary Inductance Tolerance Compensation
700-V Start-Up and Smart Power Management
Enables 560 mm2) connected on GND pin to have
90°C/W as junction to ambient thermal resistance.
Maximum continuous power with open frame design at 50°C ambient, with adequate copper area connected on GND pin and /or
adequate air flow to have 50°C/W as junction to ambient thermal resistance.
7 Pin Configuration and Functions
D (SOIC) Package
7 Pins
(Top View)
GND
1
8
DRAIN
GND
2
GND
3
6
VDD
IPK
4
5
VS
Pin Functions
PIN
NAME
NO.
DRAIN
8
I/O (1)
P
DRAIN, the drain of the internal power FET, but also the input for the high-voltage current source used to
start up the device.
G
The ground pins (GND) are both the reference pins for the controller and the low-side return for the drive
output. Special care should be taken to return all AC decoupling as close as possible to this pin and
avoid any common trace length with analog signal return paths.
IPK is used to set the maximum peak current flowing in the power FET that is proportional to the
maximum output current.
1
GND
2
DESCRIPTION
3
IPK
4
O
N/A
7
N/A
This pin is not present to provide enough distance between high voltage pin (DRAIN) and VDD pins.
VDD
6
P
VDD is the supply pin to the controller. A carefully placed bypass capacitor to GND is required on this
pin.
VS
5
I
Voltage Sense (VS) is used to provide voltage and timing feedback to the controller. Normally this pin is
connected to a voltage divider between an auxiliary winding and ground. The value of the upper resistor
of this divider is used to program low line thresholds.
(1)
P = Supply, G = Ground, I = Input, O = output
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UCC28911
SLUS769D – JULY 2013 – REVISED DECEMBER 2016
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7.1 Detailed Pin Description
7.1.1 VDD (Device Voltage Supply)
The VDD pin is connected to a bypass capacitor to ground and typically to a rectifier diode connected to the
auxiliary winding. The VDD turn on UVLO threshold is 9.5 V (VDDON typical) and turn off UVLO threshold is 6.5 V
(VDDOFF typical). The pin is provided with an internal clamp that prevents the voltage from exceeding the
absolute maximum rating of the pin. The internal clamp cannot absorb currents higher than 10 mA (see IVDD(clp) in
Absolute Maximum Ratings). To avoid damaging the device, when the clamp flowing current exceeds 6 mA
(IDDCLP_OC typical) the device stops switching. The VDD pin operating range is then from 7 V (VDDOFF maximum)
up to 26 V (VDDCLAMP minimum). The USB charging specification requires that the output current operates in
constant current mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of
approximately 17 V. Set NAS (auxiliary-to-secondary windings turn ratio) to 17 V / (VOUT + VF) where VF is the
voltage drop on the output diode at low current. The additional VDD headroom up to the clamp allows for VDD to
rise due to the leakage energy delivered to the VDD in high-load conditions.
The current consumption of the device depends upon the operating condition. The graph below shows the
current consumption as a function of normalized converter output power.
IDD Current Vs Normalized converter output power
0.01
IDD (mA)
IRUN
IDD( P)
1 10
3
IWAIT
4
1 10
4
1 10
1 10
3
0.01
0.1
1
P
POUT / POUTmax
Figure 1. VDD Current Consumption
7.1.2 GND (Ground)
The device is provided with three pins, shorted together, that are used as external ground reference to the
controller for analog signal reference. The three pins also function to pull out the heat caused by the power
dissipation of the internal power FET. Place the VDD bypass capacitor close to GND and VDD with short traces
to minimize noise on the VS and IPK signal pins.
4
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SLUS769D – JULY 2013 – REVISED DECEMBER 2016
Detailed Pin Description (continued)
7.1.3 VS (Voltage Sense)
The VS pin is connected to a resistor divider from the auxiliary winding to ground. The VS input provides three
functions.
1. It provides output voltage information to the voltage control Loop. The output voltage feedback information is
sampled at the end of the transformer secondary current demagnetization time to provide an accurate
representation of the output voltage.
2. It also provides timing information to achieve valley switching and the duty cycle of the secondary
transformer current is determined by the waveform on the VS pin.
3. It samples the bulk capacitor input voltage providing under-voltage shutdown.
The data provided in 1. and 2. are sensed during the MOSFET off-time; 3. is performed during the MOSFET ontime when the auxiliary-winding voltage is negative.
Connected between VS pin and the auxiliary winding there is the resistance RS1. During MOSFET on-time the
auxiliary voltage is negative and proportional to the converter input voltage. The voltage on VS pin is clamped to
GND and through the resistance RS1. During the on-time, the current sourced from the VS pin, proportional to
converter input voltage and inversely proportional to resistance RS1, is sensed by the device. For the undervoltage function, the enable threshold on VS current is 210 μA and the disable threshold is 75 μA.
The resistor values for RS1 and RS2 can be determined by the equations below.
RS1
VRMS _ EN u 2
NPA u IVSLRUN
where
• NPA is the transformer primary to auxiliary turns ratio,
• VRMS_EN is the AC RMS voltage to enable turn on of the controller,
• IVSLRUN is the line sense current (210 μA typical).
VVSR u RS1 u NPA
RS2
(VOUT VF ) u NPS (VVSR u NPA )
(1)
where
• VOUT is the converter output voltage in V,
• VF is the output rectifier forward drop at low current in V,
• NPS is the transformer primary to secondary turns ratio RS1 is the VS divider high side resistance in
Ohms,
• VVSR is the regulating level of VS pin.
(2)
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UCC28911
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Detailed Pin Description (continued)
7.1.4 IPK (Set the Maximum DRAIN Current Peak)
A resistance (RIPK) connected between IPK pin and GND sets the maximum value of the power FET peak
current, ID_PK(max). A current, ISENSE, proportional to the power FET current, comes out from the IPK pin during
power FET on time. The voltage across RIPK is fed to the PWM comparator and establish to switch off the power
FET according to the following equation:
VCSTE(max)
ID _ PK(max)
RIPK
where
•
VCSTE(max) is the equivalent current sense threshold (see Electrical Characteristics table).
(3)
If the IPK pin is shorted to GND (RIPK = 0), the peak current is automatically set to ID_PEAK(max), 600 mA for
UCC28910, or 700 mA for UCC28911.
A test is performed at device start up to check whether the IPK pin is shorted to GND or the RIPK is present. If
RIPK is less than RIPK_SHORT (maximum), the device interprets it as a short (RIPK = 0) and the DRAIN peak current
is set to ID_PEAK(max). Otherwise, if RIPK is greater than RIPK(min) (minimum), the device sets the peak current
DRAIN according to the previous equation. A value of RIPK that is in between the before said values is not
allowed since the value of the peak current may be selected using either of the two sense resistances: the
internal sense resistance and RIPK.
7.1.5 DRAIN
The DRAIN pin is connected to the DRAIN of the internal power FET. This pin also provides current to the high
voltage current source at start up.
6
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SLUS769D – JULY 2013 – REVISED DECEMBER 2016
8 Specifications
8.1 Absolute Maximum Ratings
(unless otherwise noted)
(1) (2)
VDRAIN
DRAIN voltage
IDRAIN
Negative drain current
MIN
MAX
UNIT
Internally
limited (3)
700
V
–100
VDD
Supply voltage
IVDD(clp)
Maximum VDD clamp current
VVS
Voltage range
Internally
limited (3)
VIPK
Voltage range
−0.5
IVS
Peak VS pin current (current out of the pin)
−1.2
Pulsed drain current
, UCC28911
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
TJ
Operating junction temperature range
(3)
(4)
10
mA
7
V
5.0
V
mA
(4)
TLEAD
(2)
V
Pulsed drain current (4), UCC28910
IDRAIN
(1)
mA
Internally
limited (3)
−55
950
mA
1200
mA
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified pin. These ratings apply over the operating
ambient temperature ranges unless otherwise noted.
Do not drive with low impedance voltage source.
Maximum pulse width = 100 μs.
8.2 Storage Conditions
Tstg
Storage temperature
MIN
MAX
UNIT
−65
150
°C
VALUE
UNIT
8.3 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.4 Recommended Operating Conditions (1) (2)
MIN
VVDD
Voltage on VDD terminal during operation
IVS
Current out of the terminal
ID(peak_max)
Maximum drain peak current
TJ
Operating junction temperature
(1)
(2)
NOM
VDDOFF
MAX
VVDD(clp)
1
UNIT
V
mA
UCC28910
600
mA
UCC28911
700
mA
-40
125
°C
Unless otherwise noted, all voltages are with respect to GND.
In case of thermal shut down, if TA > 100°C, the device does not restart because of the TJ(hys) Electrical Characteristics.
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UCC28911
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8.5 Thermal Information
UCC28910
THERMAL METRIC (1)
UCC28911
D
D
7 Pin SOIC
7 Pin SOIC
UNITS
θJA
Junction-to-ambient thermal resistance
102.2
102.2
θJCtop
Junction-to-case (top) thermal resistance
39.1
39.1
θJB
Junction-to-board thermal resistance
54.7
54.7
ψJT
Junction-to-top characterization parameter
5.4
5.4
ψJB
Junction-to-board characterization parameter
54.7
54.7
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted), VVDD = 15 V, TA = -40°C to 125°C, TA = TJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY INPUT
IRUN
Supply current, run
IRUNQ
Quiescent supply current
VVS = 3.9 V, fSW = fSW(max)
UCC28910
2.3
2.9
3.4
mA
VVS = 3.75 V, fSW = fSW(max)
UCC28911
2.3
2.9
3.4
mA
VVS = 3.9 V, fSW = 0 Hz
UCC28910
1.90
2.35
2.80
mA
VVS = 3.75 V, fSW = fSW(max)
UCC28911
1.90
2.35
2.80
mA
270
370
µA
IWAIT
Wait supply current
VVS = 4.1 V, fSW = fSW(min),
TJ = 25°C
UCC28910
UCC28911
250
330
µA
IWAITQ
Quiescent wait supply
current
VVS = 4.1 V, fSW = 0 Hz,
TJ = 25°C
UCC28910
200
280
µA
UCC28911
190
240
µA
0 V ≤ VVDD ≤ 5.6 V,
VDRAIN = 0 V
UCC28910
65
90
µA
0 V ≤ VVDD ≤ 5.6 V,
VDRAIN = 0 V, TJ = 25°C
UCC28911
65
80
µA
fSW = 0 Hz
UCC28910
190
260
µA
fSW = 0 Hz, TJ = 25°C
UCC28911
190
240
µA
ISTART
Supply current before start
IFAULT
Supply current after fault
UNDER-VOLTAGE LOCKOUT
VDDON
VDD turn-on threshold
VVDD low to high
9.0
9.5
10.0
V
VDDOFF
VDD turn-off threshold
VVDD high to low
6.0
6.5
7.0
V
VDDHV(on)
HV current source start
VVDD high to low
4.8
5.2
5.6
V
ΔVUVLO
UVLO hysteresis
VDDON – VDDOFF
2.8
3.0
3.2
V
–300
–100
µA
STARTUP CURRENT SOURCE
ICH1
Startup current with VDD
shorted to GND
ICH2
Sourced current for startup at
VVDD = 8 V, VDRAIN = 100 V
high VDD
–9.75
–0.40
mA
ICH3
Sourced current for startup at
VVDD = 2 V, VDRAIN = 100 V
low VDD
–13.75
–1.30
mA
8
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VVDD < 250 mV, VDRAIN = 100 V
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), VVDD = 15 V, TA = -40°C to 125°C, TA = TJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS INPUT
VVSR
Regulating level
Measured in no load condition,
TJ = 25°C
4.01
4.05
4.09
V
VVSNC
Negative clamp level
IVS = –300 μA
–190
–250
–325
mV
IVS
Input bias current
VVS = 4 V
–0.25
0.00
0.25
µA
ID(ocp)
DRAIN over current
IPK pin shorted to GND
UCC28910
725
850
925
mA
UCC28911
880
980
1090
mA
VCSTE_OCP
Equivalent VCST(OCP),
ID(ocp) x RIPK
VVS = 3.9 V
UCC28910
670
770
830
V
VVS = 3.75 V
UCC28911
800
885
975
V
VCSTE_OCP2
Equivalent VCST(OCP2)
ID(ocp2) x RIPK
VVS = 3.9 V
UCC28910
1200
V
VVS = 3.75 V
UCC28911
1400
V
VVS < 3.9 V, IPK shorted to
GND
UCC28910
13
18
24
µs
VVS = 3.75 V, IPK shorted to
GND
UCC28911
13
18
24
µs
UCC28910
4.3
6
10
µs
UCC28911
4.3
6
10
µs
PROTECTION
tONMAX(max)
tONMAX(min)
Maximum FET on time at
high load
VVS > 4.1 V, IPK shorted to
Maximum FET on time at low GND
load
VVS = 4.35 V, IPK shorted to
GND
VOVP
Over-voltage threshold
At VS input, TJ = 25°C
4.45
4.60
4.75
V
IVSL(run)
VS line sense run current
Current out of VS pin – increasing
175
215
260
µA
IVSL(stop)
VS line sense stop current
Current out of VS pin – decreasing
60
75
100
µA
KVSL
Line sense IVS ratio
IVSL(run) / IVSL(stop)
2.55
2.70
2.90
A/A
VDDCLP
VDD voltage clamp
IVDDCLP forced = 2 mA
IVDDCLP_OC
VDD clamp over current
VVDD > 25 V
TJ(stop)
Thermal shutdown
temperature
Internal junction temperature
150
°C
TJ(hys)
Thermal shutdown hysteresis Internal junction temperature
50
°C
26
28
30
4.65
6.00
7.65
V
mA
POWER FET
BVDSS
Break-down voltage
TJ = 25°C
ID = 150 mA, TJ = 25°C
RDS(on)
Power FET on resistance
ID = 150 mA, TJ = 125°C
ILEAKAGE
DRAIN pin leakage current
700
V
UCC28910
10.5
12.0
Ω
UCC28911
6.25
7.2
Ω
UCC28910
18.4
21.5
Ω
UCC28911
11.4
13.4
Ω
VDS = 400 V HV, VS = 4.2 V DC
TJ = 25°C
10
µA
VDS = 400 V HV, VS = 4.2 V DC
TJ = 125°C
20
µA
VDS = 700 V HV, VS = 4.2 V DC
TJ = 25°C
10
µA
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), VVDD = 15 V, TA = -40°C to 125°C, TA = TJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UCC28910
582
600
618
mA
UCC28911
680
700
720
mA
200
Ω
CURRENTS
ID_PEAK(max)
Maximum DRAIN peak
current
IPK pin shorted to GND, TJ =
25°C
RIPK_SHORT
IPK to GND resistance Max
to assume IPK shorted to
GND
RIPK(min)
IPK to GND minimum
resistance
VCSTE(max)
Equivalent current sense
threshold, ID_PK(max) × RIPK
VVS = 3.9 V, TJ = 25°C
UCC28910
532
540
548
V
VVS = 3.75 V
UCC28911
620
630
640
V
VCSTE(min)
Equivalent current sense
threshold, ID_PK(min) × RIPK
VVS = 4.1 V
UCC28910
160
180
200
V
VVS = 4.35 V
UCC28911
KAM
AM control ratio
VCSE(max) / VCSE(min)
KCC
CC regulation gain, tDEMAG ×
fSW
VVS < 3.9 V
UCC28910
VVS = 3.75 V
UCC28911
VCCR
CC regulation constant,
VCSET(max) × KCC
900
VVS < 3.9 V, TJ = 25°C
Ω
170
216
265
V
2.30
3.00
3.50
V/V
0.413
0.413
UCC28910
216
223
230
V
UCC28911
250
260
270
V
8.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING
fSW(max)
Maximum switching
frequency
fSW(min)
Minimum switching frequency
tZTO
Zero crossing timeout delay
tON(min)
10
Minimum on time
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VVS < 3.9 V
UCC28910
105
115
125
kHz
VVS = 3.75 V
UCC28911
105
115
125
kHz
VVS > 4.1 V
UCC28910
360
420
490
Hz
VVS = 4.35 V
UCC28911
360
420
500
Hz
VVS < 3.9 V
UCC28910
1.80
2.10
2.65
µs
VVS = 4.35 V
UCC28911
1.80
2.10
2.75
µs
IPK = 0.85 V
UCC28910
390
ns
UCC28911
420
ns
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8.8 Typical Characteristics
Unless otherwise specified, VVDD = 15 V, TA = –40°C to 125°C, TA = TJ
1.10
ID_PEAK(max) Normalized to 25qC
ID_PEAK(max) Normalized to 25qC
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.75
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
±50
0.60
1.00
0.50
0.40
0.30
0.20
6
8
10
Drain Voltage (V)
125
150
C502
0.80
0.60
0.40
TJ = 25°C
0.00
0
12
2
4
C503
1.005
1.05
VCSTE(max) Normalized to 25ƒC
1.10
0.995
0.990
0.985
0.980
8
10
12
C504
Figure 5. UCC28911 DRAIN Current vs DRAIN Voltage
1.010
1.000
6
Drain Voltage (V)
Figure 4. UCC28910 Drain Current vs Drain Voltage
VCSTE(max) Normalized to 25ƒC
100
TJ = 125°C
TJ = 125°C
0.00
4
75
0.20
TJ = 25°C
0.10
50
Figure 3. UCC28911 ID_PEAK(max) vs Temperature
1.20
Drain Current (A)
Drain Current (A)
Figure 2. UCC28910 ID_PEAK(max) vs Temperature
2
25
Temperature (ƒC)
0.70
0
0
±25
C501
1.00
0.95
0.90
0.85
0.80
0.75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±50
±25
Figure 6. UCC28910 VCSTE(max) vs Temperature
0
25
50
75
100
125
Temperature (ƒC)
C505
150
C507
Figure 7. UCC28911 VCSTE(max) vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VVDD = 15 V, TA = –40°C to 125°C, TA = TJ
1.10
VCSTE(min) Normalized to 25ƒC
VCSTE(min) Normalized to 25ƒC
1.03
1.02
1.01
1.00
0.99
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.98
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±50
1.03
1.02
1.02
VCCR Normalized to 25ƒC
VCCR Normalized to 25ƒC
25
50
75
100
125
150
C508
Figure 9. UCC28911 VCSTE(min) vs Temperature
1.03
1.01
1.00
0.99
0.98
1.01
1.00
0.99
0.98
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C509
Figure 10. UCC28910 VCCR vs Temperature
150
C510
Figure 11. UCC28911 VCCR vs Temperature
1.05
1.10
1.03
fSW(min) Normalized to 25ƒC
fSW(max) Normalized to 25ƒC
0
Temperature (ƒC)
Figure 8. UCC28910 VCSTE(min) vs Temperature
1.01
0.99
0.97
0.95
±50
±25
0
25
50
75
100
Temperature (ƒC)
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125
150
1.07
1.04
1.01
0.98
0.95
±50
±25
C511
Figure 12. fSW(max) vs Temperature
12
±25
C506
0
25
50
75
100
Temperature (ƒC)
125
150
C512
Figure 13. fSW(min) vs Temperature
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Typical Characteristics (continued)
4.15
4.75
4.10
4.70
VOVP Over Voltage (V)
VVSR Regulation Level (V)
Unless otherwise specified, VVDD = 15 V, TA = –40°C to 125°C, TA = TJ
4.05
4.00
3.95
4.65
4.60
4.55
3.90
4.50
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
±50
0
145.0
3
144.0
143.0
2
142.0
1.5
141.0
ICH2 ( A)
2.5
1
140.0
ICH1
0.5
138.0
0
0
25
50
75
100
125
100
125
150
C514
200
150
100
50
ICH2
-25
75
250
IVSLRUN and IVSLSTOP ( A)
3.5
-50
50
Figure 15. VOVP vs Temperature
146.0
139.0
25
Temperature (ƒC)
Figure 14. VVSR vs Temperature
ICH1 (mA)
±25
C513
Temperature (ƒC)
IVSLRUN
IVSLRUN
0
150
±50
C515
±25
0
25
50
75
IVSLSTOP
IVSLSTOP
100
125
Temperature (ƒC)
150
C516
Figure 16. ICH1 and ICH2 vs Temperature
1.40
1.20
1.20
IWAITQ Normalized to 25ƒC
IWAIT Normalized to 25ƒC
Figure 17. IVSLRUN and IVSLSTOP vs Temperature
1.40
1.00
0.80
0.60
0.40
0.20
1.00
0.80
0.60
0.40
0.20
0.00
0.00
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
±50
±25
Figure 18. IWAIT vs Temperature
0
25
50
75
100
125
Temperature (ƒC)
C517
150
C518
Figure 19. IWAITQ vs Temperature
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9 Detailed Description
9.1 Overview
UCC28910 and UCC28911 are HV switchers dedicated to an off-line power supply in an isolated flyback
configuration. HV switcher means that each device integrates the power switch, a 700-V power FET, with the
control logic. The two devices have the same control logic and they are different only for the Power FET RDS(on)
and for the operating current levels. The control logic controls both the output voltage and the output current
without the need of an optical coupler. This control method is known as Primary-Side Regulation (PSR) and it
operates by analyzing the voltage waveform on the auxiliary winding of the transformer. This allows significant
cost saving with respect to traditional control scheme that uses an optical coupler for feedback from a secondaryside shunt regulator. The transformer auxiliary winding is also used to provide housekeeping supply power to the
control logic. The device operates in Constant Voltage mode (CV) when it is controlling the output voltage. The
device operates in Constant Current mode (CC) when the output current is controlled. The device operates in CV
mode or in CC mode according to the load condition. (See Figure 24). A control algorithm that implements both
modulation of the switching frequency and the amplitude modulation of the primary current peak, allows the
power supply to operate efficiently over the entire load range. The high-voltage current source used for startup is
kept off during normal operation thereby minimizing standby power consumption. The device also incorporates a
smart power management to minimize its current consumption from the VDD pin. This power consumption is
reduced when the converter is lightly loaded or unloaded allowing for a total input power of less than 30 mW
when converter input voltage is 265 VAC and unloaded. A number of protection features inside the device allow
for improved overall system reliability.
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9.2 Functional Block Diagram
VBULK
Primary
Winding
Auxiliary
Winding
Secondary
Winding
+
-
VOUT
Load
VDD
DRAIN
6
8
GND
1,2,3
UVLO Logic
+
VDD CLP Fault
6 mA
+
OT Fault
OC Fault
Line Fault
Power and Fault
Management
OV Fault
OT Fault
VOVP
Thermal
Sense
Fault
Jitter
RS1
fSW
Sampler
+
VVSR
IVS
Control
Law
5
Current Regulation
and VFF
Compensation
Discriminator
RS2
R
Q
+
OC
Fault
Zero Cross
Detect
Q
IDRAIN
tON(min)
VS
S
IDRAIN Sense
+
VCSTE_OCP
IVS
Line Sensing
2.1 V/0.8 V
IVS
+
Line Fault
10 k
Select
Sense
Resistor
IPK
4
Internal
RIPK
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9.3 Feature Description
UCC28911 and UCC28910 are flyback power supply switchers which provide accurate output voltage and
constant current regulation with primary-side feedback, eliminating the need for optical coupler feedback circuits.
The device has an internal 700-V power FET plus a controller which forces the converter to operate in
discontinuous conduction mode with valley switching to minimize switching losses. The modulation scheme is a
combination of frequency and primary-peak current modulation to provide optimized conversion efficiency over
the entire load range. The control law provides a wide dynamic operating range to achieve less than 30-mW
standby power.
UCC28911 and UCC28910 include features in the modulator to reduce the EMI peak energy of the fundamental
switching frequency and harmonics. Accurate voltage and constant current regulation, fast dynamic response,
and fault protection are achieved with primary-side control.
A complete charger solution can be realized with a straightforward design process, low cost and low component
count solution.
9.3.1 Primary-Side Voltage Regulation
Figure 20 illustrates a flyback converter. The voltage regulation blocks of the device are shown. The power train
operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to
primary side control.
VBULK
Primary
Winding
Secondary
Winding
+
-
VOUT
Load
(VOUT + VF) x NPS/NPA
DRAIN
8
RS1
Gate Driver
Error Amplifier
VS
Auxiliary
Winding
5
Sampler
+
VVSR
RS2
GND
Control Law
Fixes fSW and
Drain Current
Peak
S
Q
R
Q
IDRAIN
+
Discriminator
1,2,3
IDRAIN Sense
IPK
4
Zero Cross
Detect
RIPK
PWM Comparator
Reference
Figure 20. Voltage Loop Block Diagram
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Feature Description (continued)
In primary-side control, the output voltage is sensed by the auxiliary winding during the transfer of transformer
energy to the secondary. Figure 21 shows the down slope representing a decreasing total rectifier VF and the
secondary winding resistance voltage drop as the secondary current decreases to 0 A. To achieve an accurate
representation of the secondary output voltage on the auxiliary winding, the Discriminator Block (Figure 20)
reliably ignores the leakage inductance reset and ring, continuously samples the auxiliary voltage during the
down slope after the ringing is diminished, and captures the error signal at the time the secondary winding
reaches 0 current. The internal reference on VS is 4.05 V (VVSR typical); the resistor divider is selected as
outlined in the VS pin description.
VOUT
VF u
NPS
NPA
0V
VBULK
NPA
Figure 21. Auxiliary Winding Voltage
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Feature Description (continued)
The UCC28910 VS signal Discriminator Block (Figure 20) ensures accurate sampling time for an accurate
sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding
signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to Figure 22 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset
pedestal, tLK_RESET. Since this can mimic the waveform of the secondary current decay, followed by a sharp
down-slope, it is important to keep the leakage reset time less than 500 ns for IDRAIN minimum, and less than 1.5
μs for IDRAIN maximum. The second detail is the amplitude of ringing on the auxiliary winding waveform (VAUX)
following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least
200 ns before the end of the demagnetization time, tDMAG. If there is a concern with excessive ringing, it usually
occurs during light or no-load conditions, when tDMAG is at the minimum. The tolerable ripple on VS is scaled up
to the auxiliary winding voltage by RS1 and RS2, and is equal to 100 (RS1 + RS2) / RS2 mV.
During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode.
The internal operating frequency limits of the controller are 115 kHz maximum and 420 Hz minimum. The
transformer primary inductance and turns ratio sets the maximum operating frequency of the converter. The
output preload resistor and efficiency at low power determines the converter minimum operating frequency.
There is no external compensation required for the UCC2891x devices.
tLK_RESET
tSMPL
VS Ring p-p
tDMAG
Figure 22. VS Voltage
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Feature Description (continued)
9.3.2 Primary-Side Current Regulation
Timing information at the VS pin and the primary current information allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current is at ID_PK(max) = VCSTE(max) / RIPK. Referring to Figure 23, the primary-peak
current, turns ratio, secondary demagnetization time (tDMAG), and switching period (tSW) establish the secondary
average output current. When the average output current reaches the regulation reference in the current control
block, the controller operates in frequency modulation mode to control the output current at any output voltage at
or below the voltage regulation target as long as the aux winding can keep VDD above the VDD UVLO threshold
(VDDOFF).
ISEC(peak)
ID _ PK(max)
NPS
tON
t
tDMAG
tSW
IOUT
Primary Current
Secondary Current
NPS
1
u IS _ PK(max) u tDMAG u fSW
u ID _ PK(max) u DMAGCC
2
2
DMAGCC tDMAG u fSW KCC
where
Figure 23. Output Current Estimation
Output Voltage (V)
5
4
±5%
3
2
1
0.3
0.6
0.9
1.2
1.4
Output Current (A)
Figure 24. Target Output V-I Characteristic
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Feature Description (continued)
KCC is defined as the maximum value of the secondary-side conduction duty cycle (DMAGCC in Figure 23). It is set
internally by the UCC2891x and occurs during constant current control mode.
VBULK
Primary
Winding
Secondary
Winding
+
-
VOUT
Load
(VOUT + VF) x NPS/NPA
DRAIN
8
Zero Cross
Detect
RS1
Gate Driver
VS
Auxiliary
Winding
5
Current Regulation
and VFF
Compensation
Discriminator
S
Q
R
Q
IDRAIN
fSW
RS2
+
GND
1,2,3
PWM Comparator
IDRAIN Sense
IPK
4
RIPK
tDMAG
Figure 25. Output Current Control Loop Block Diagram
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Feature Description (continued)
9.3.3 Voltage Feed Forward Compensation
During normal operation the on-time is determined by sensing the power FET current and switching off the power
FET as this current reaches a threshold fixed by the feedback loop according to the load condition. The power
FET is not immediately turned off and its current, that is also the primary winding current, continues to rise for
some time during the propagation delay (tDELAY in Figure 26). Keeping the reference for the PWM comparator
constant, the value of the primary winding peak current depends on the slope of the primary winding current and
tDELAY. The slope of the primary current is proportional to the flyback stage input voltage (VBULK)
ûID_PK
V
CSTE(max)
R
IPK
ID _ PK _ TARGET
ID_PK
tDELAY
t
Figure 26. Propagation Delay Effect on the Primary Current Peak
'ID _ PK
ID _ PK
VBULK
u tdelay
LP
ID _ PK _ TARGET
(4)
VBULK
u tdelay
LP
(5)
The current loop estimates the output current assuming the primary winding peak current is equal to the
IPK_TARGET and compares this estimated current with a reference to obtain the current regulation. Considering,
ID_PEAK is different from ID_PEAK_TARGET (see Figure 26) we need to compensate the effect of the propagation
delay. The UCC28910 and the UCC28911 incorporate fully-integrated propagation-delay compensation that
modifies the switching frequency keeping the output current constant during (CC) Constant Current Mode
operation. This function is integrated in the controller and requires no external components. This feature keeps
the output current constant despite input voltage variations and primary inductance value spread.
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Feature Description (continued)
9.3.4 Control Law
During voltage regulation, the device operates in switching frequency modulation mode and primary current peak
amplitude modulation mode. The internal operating frequency limits of the device are fSW(max) and fSW(min). During
constant current regulation the device operates only in frequency modulation mode reducing the switching
frequency as the output voltage decreases. Figure 27 shows how the primary peak current and the switching
frequency change with respect to changes in load. The solid lines are primary-side peak current and the output
voltage, the dotted lines are the switching frequency and output current.
Constant Voltage (CV Mode)
Constant Current (CC Mode)
fSW(max)
ID_PK
fSW (kHz)
VCSTE(max) / RIPK
~ 44 kHz
VCSTE(max) / RIPK
~ 4.4 kHz
fSW(min)
VOUTn
VOUT
Stop/Restart
Region:
(VDD < VDDOFF)
~ 1 / 2376 ~1 / 270
~1 / 27
~1 /3
IOUT
IOUTn
1
Normalized Output Power POUT / POUT_MAX
Figure 27. Control Law Profile
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Feature Description (continued)
9.3.5 Valley Switching
The UCC28910 and the UCC28911 utilize valley switching to reduce switching losses in the MOSFET and
minimize the current spike at the FET turn on. The UCC28910 operates in valley switching in almost all load
conditions until the VDS ringing is diminished. By switching at the lowest VDS voltage the MOSFET turn on dV / dt
is minimized which is a benefit to reduce EMI.
Referring to Figure 28, devices will operate in a valley switching mode in most load conditions to switch-on at the
lowest available VDS voltage. According to the load it is established a minimum switching period. The MOSFET is
switched-on at the first valley that occurs after this minimum period is elapsed. With this control scheme the
device can be turned-on at the first valley that occurs after transformer demagnetization or it can skip some
valleys before turn-on operating in this case in the so called valley skipping mode. Valley switching is maintained
during constant current regulation to provide improved efficiency and EMI benefits in constant current operation.
If for some reason no valley is detected at the end of the tZTO time the MOSFET turns-on. In order to guarantee
discontinuous mode operation at least the first valley needs to be detected or the Mosfet is not turned-on (see
Figure 28).
VDS
Valley Skipping
Valley Skipping
t
MINP
Minimum allowed period
Minimum allowed period
tZTO
t
tZTO
tZTO
ZCD
~ 150 ns
t
Switch-On
Figure 28. Valley Skipping
In very light-load or no-load condition the VDS ringing amplitude is very low and not easy to detect, moreover with
very low ringing amplitude there would be no benefit in valley switching so in this condition the valley switching is
disabled (see Figure 29). The device switch on the MOSFET as soon the time tZTO is elapsed. The tZTO timer
starts as soon as the minimum switching period is elapsed.
No Valley Switching in Light Load
VDS
MINP
Minimum Allowed Period
Minimum Allowed Period
tZTO
tZTO
t
Figure 29. Valley Switching Disable at Light Load
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Feature Description (continued)
9.3.6 Startup Operation
The UCC28910 and UCC28911 are provided with a high-voltage current source, connected between the DRAIN
pin and the VDD pin; this current source is activated when a voltage is applied on DRAIN pin. The current source
charges the capacitor connected between VDD and GND increasing the VDD voltage. As VDD exceeds VDDON
the current source is turned off and the controller internal logic is activated and the device starts switching. If the
VDD voltage falls below the VDDOFF threshold, or a fault condition is detected, the controller stops operation and
its current consumption is reduced to ISTART or IFAULT. The high-voltage current source is turned on again when
VDD voltage goes below VDDHV(on) (see Figure 30 for reference).
The initial three cycles are limited to ID_PEAK(max) / 3. This allows sensing any input or output faults with minimal
power delivery. After the initial three cycles at ID_PEAK(max) / 3, the controller responds to the condition dictated by
the control law.
VBULK
t
VDDON
VDDOFF
VDDHV(on)
VDD
t
VDRAIN
t
Behavior with Auxiliary
Winding Disconnected
Fault
Figure 30. Start Up and Auto Re-Start Operation
The converter remains in DCM during charging of the output capacitor(s), and operates in constant current mode
until the output voltage is in regulation.
To avoid high-power dissipation inside the device, such as in the event that VDD is accidentally shorted to GND,
the current provided by the high-voltage current source is reduced (ICH1) when VDD < 1 V (typical).
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Feature Description (continued)
9.3.7 Fault Protection
There is comprehensive fault protection incorporated into the UCC2891x. Protection functions include:
• Output Over-Voltage Fault
• Input Under-Voltage Fault
• Primary Over-Current Fault
• VDD Clamp Over Current
• Thermal Shut Down
9.3.7.1 Output Over-Voltage
The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on
VS exceeds 4.6 V, which correlates to 113.5% of nominal VOUT, the device stops switching and reduces its
current consumption to IFAULT, slowly discharging the VDD capacitor to the VDDHV(on) threshold. At this time the
standard startup sequence begins. The initial three cycles of startup at low-peak DRAIN current is important to
monitor VOUT and deliver minimal power. The reset and restart, or hiccup, sequence applies for all fault
protection. The slow VDD capacitor discharge after a fault allows the high voltage current source to have a low
duty cycle to avoid over heating of the device if a fault condition is continuously present resulting in a repetitious
start up sequence.
9.3.7.2 Input Under-Voltage
The input under voltage is determined by current information on the VS pin during the MOSFET on time. The VS
pin is clamped close to GND during the MOSFET on time; at this time the current though RS1 is monitored to
determine a sample of the bulk capacitor voltage. The under voltage shutdown current on VS is 75 μA; the
enable current threshold is 210 μA. The device must sense the under-voltage condition for three consecutive
switching cycles to recognize it as a fault condition. After an under-voltage fault, the same sequence described
for output overvoltage occurs.
9.3.7.3 Primary Over-Current
The UCC28910 and the UCC28911 always operates with cycle-by-cycle primary current control. The normal
operating range for the peak DRAIN current depends on the resistance (RIPK) connected between the IPK pin
and the GND pin. The peak DRAIN current should not exceed ID_PEAK(max) even if the IPK pin is shorted to GND,
or should not exceed VCSTE / RIPK if the IPK pin is tied to GND with the resistance RIPK. There are different
reasons the DRAIN current can go out of control, for example a secondary winding short or hard saturation of the
transformer. To avoid over-stress of the power FET additional protections are added. If the DRAIN current
exceeds IDOCP (~33% higher than ID_PEAK(max)), such as when IPK pin is shorted to GND, or VCSTE_OCP / RIPK,
(VCSTE_OCP ~33% higher than VCSTE(max)), and the condition is sensed for three consecutive switching cycles, a
fault shutdown and retry sequence, detailed in the output overvoltage fault description, occurs. If the DRAIN
current exceeds a second level of current (VCSTE_OCP2 / RIPK) it is not necessary to detect the fault for three
consecutive switching cycles, the device will stop switching immediately.
9.3.7.4 VDD Clamp Over-Current
The VDD pin is provided with an internal clamp to prevent the pin voltage from exceeding the absolute maximum
rating. If the current in the clamp exceeds 6 mA (typical), in order to avoid any damage to the device and to the
system, a fault condition is assumed and the device stops operation.
9.3.7.5 Thermal shutdown
The internal thermal shutdown threshold is 150°C (typical) with a hysteresis of 50°C (typical). If an overtemperature is detected the device stops switching and its current consumption is reduced to IFAULT. The VDD
voltage will decrease to VDDHV(on) where the high voltage current source is activated and the VDD voltage will rise
again until VDD(on) where the internal logic is re-activated. If the temperature of the device is not dropped below
approximately 100°C (150°C- 50°C) no switching cycles occurs and the fault condition is maintained and the
current consumption is again IFAULT. For diagnostic purpose, when a thermal shut down occurs a short voltage
pulse, whose amplitude is around 2 V, is transmitted on the IPK pin. Thermal shut down feature is not intended to
protect the device itself but mainly to control the damage caused by the device thermally overstressed.
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Feature Description (continued)
9.3.8 EMI Dithering
Generally, power supply designs need to pass EMI standard such as EN55022. When the device-controlled
Flyback design is used as the auxiliary power supply in a larger system, such as motor drive or home appliance,
the EMI filter for the entire system should be enough to filter out the EMI noise created by the Flyback converter.
However, when the Flyback is a standalone power supply, the EMI noise becomes a concern.
The EMI noise is normally managed by adding necessary EMI filtering or circuit techniques such as the parasitic
capacitor control, snubbering, or transformer EMI noise cancelation windings. Besides these, in both the
UCC28910 and UCC28911 devices, the MOSFET switching speed is controlled so that the EMI noise can be
minimized. Furthermore, EMI dithering technique is also implemented.
The EMI receiver uses a 9-kHz bandwidth detector to measure the noise energy within that bandwidth. If a power
supply switching frequency is slightly changed with time, so that the switching frequency energy can be spread
outside 9-kHz band, the measured EMI noise can be smaller. This technique makes it easier to pass the EMI
standard. This switching frequency change technique is often called EMI dithering or jittering.
The EMI dithering scheme used in these devices effectively change the switching frequency outside of 9-kHz
EMI receiver band, while minimize the output voltage ripple caused by the EMI dithering effect. The frequency
modulation is based on a 12-cycle repeat rate. In each 12 switching cycles, there are three groups of 4 switching
cycle, with three frequency deviations and three peak current settings. Figure 31 illustrates a group of 4 switching
cycles, the center frequency and desired peak current. Figure 32 illustrates a group of reduced switching
frequency (–7.5 kHz) with increased peak current (+3.5%) and a group of increased switching frequency (+7.5
kHz) with decreased peak current (–3.5%). The 7.5 kHz frequency deviation is selected to spread the switching
frequency noise energy outside of 9-kHz EMI detector bandwidth. In turn, this frequency reduces the measured
EMI noise.
+ 7.5%
+7.5 kHz
Peak
current
deviation
4/fSW .
0 kHz
Peak
current
deviation
±7.5kHz
0%
4/fSW .
±7.5%
+ 3.5%
12/fSW .
Switching
frequency
deviation
0%
±3.5%
12/fSW .
Time
Figure 31. EMI Dithering During CV Mode
Operation
Figure 32. EMI Dithering During CC Mode
Operation
The UCC28910 and UCC28911 devices control the Flyback converter during DCM operation only. The frequency
change with fixed peak current may result in output voltage ripple because of the fluctuation of the energy
delivery. By adjusting the peak current and frequency at the same time allows minimum variation on the energy
delivery and reduces the output voltage ripple. During CC mode operation, the switching frequency is controlled
to deliver the constant output current. Therefore, only the peak current is modulated to achieve equivalent EMI
dithering.
The EMI dithering is disabled in the light load when the device enters a WAIT state.
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9.4 Device Functional Modes
According to the input voltage, the VDD voltage, and the load conditions, the device can operate in different
modes:
1. At start-up with VDRAIN > 20 V, VDD = 0 V, the HV voltage current source is ON and starts to charge the
capacitor connected to the VDD pin. With VDD < 1 V the current provided is limited < 500 µA and VDD rises
slowly.
2. When VDD exceeds 1 V (VDD < VDDON) the HV current source provides higher current and VDD rises
faster.
3. When VDD exceeds VDDON the device starts switching and delivers power to its output. According to its
load, the converter operates in CV mode or in CC mode.
(a) CV mode means that the converter keeps the output voltage constant. This operating mode takes place
when RLOAD > VOCV / IOCC where VOCV is the target for output voltage and IOCC is the maximum converter
output current. In this condition the converter output voltage VOUT = VOCV and the converter output
current IOUT < IOCC.
(b) CC mode means that the converter keeps the output current constant. This operating mode takes place
when RLOAD < VOCV / IOCC. In this condition the converter output voltage VOUT < VOCV and the converter
output current IOUT = IOCC.
4. Device operations can be stopped because of the events listed below:
(a) If VDD drops below VDDOFF, the device stops switching and its current consumption is lowered to ISTART.
Because the converter is not switching, no energy is delivered from the auxiliary winding, the HV current
source is off, then the VDD capacitor is discharged with ISTART current.
(b) If a fault is detected device stops switching and its current consumption is lowered to IFAULT that slowly
discharges the VDD capacitor down to VDDOFF where the current consumption is ISTART < IFAULT and the
VDD capacitor continues to discharge.
5. After the device stops switching, because of 4a or 4b, the VDD voltage drops, when it goes below VDDHV(on),
the HV current source is turned on recharging the VDD capacitor up to VDDON.
6. When a fault condition is permanently present, the device operates in auto restart-mode. This means that a
fault condition is detected, the device stops operation as described in 4b, then VDD drops down to VDDHV(on)
when the device start-up sequence takes place. At device turn-on, the fault is again detected and the cycle
repeats.
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10 Applications and Implementation
10.1 Application Information
The UCC28910 and UCC28911 devices are HV switcher that integrates an HV power FET plus a controller that
uses primary-side-regulated (PSR), supporting magnetically-sensed output voltage regulation via the transformer
bias winding. This sensing eliminates the need for a secondary-side reference, error amplifier and optical-isolator
for output voltage regulation. The devices deliver accurate output voltage static load and line regulation, and
accurate control of the output current. The magnetic sampling scheme allows operation only in discontinuous
conduction mode (DCM) so the device is not allowed to turn on the Power FET if it doesn’t sense a ZCD event. A
ZCD event is when auxiliary winding voltage crosses zero from high to low after transformer demagnetization is
completed. The modulator adjusts both frequency and peak current in different load regions to maximize
efficiency throughout the operating range. The smart management of the control logic power consumption and
the HV current source, used for startup that is off during operation and have very low leakage current, allow
designing converters with very low standby input power. The less than 30mW can be easily achieved with these
devices.
10.2 Typical Application
10.2.1 Battery Charger, 5 V, 6 W
This design example describes the UCC28910FBEVM-526 design and outlines the design steps required to
design a constant-voltage, constant-current flyback converter for a 5-V/6-W charger. Discontinuous conduction
mode (DCM) with valley switching is used to reduce switching losses. A combination of switching frequency and
peak primary current amplitude modulation is used to keep conversion efficiency high across the full load and
input voltage range. Figure 33 below details the output V-I characteristic. Low system parts count and built in
advanced protection features result in a cost-effective solution that meets stringent world-wide energy efficiency
requirements.
Output Voltage (V)
5
4
±5%
3
2
1
EVM Target
0.3
0.6
0.9
1.2
1.4
Output Current (A)
Figure 33. Target Output V-I Characteristic
28
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J1
88 VAC TO 265 VAC
47 Hz TO 63 Hz
I IN MAX. = 200 mA
LINE
NEUTRAL
2
1
RF1
NEUTRAL
FKN1WSJR-52-4R7
LINE
4
~
1
+
2
~
3
D1
DF06M
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768772102
1mH
C2
10μF
400V
R3
1.50k
D2
SMBJ170A-TR
170V
1
4
3
2
R4
15.0k
R6
100k
VS
VDD
DRAIN
UCC28910D
IPX
GND
GND
GND
U1
R5
1.50k
C3
100pF
5
6
8
C4
0.1μF
HV
D3
1N4937-E3
C5
10μF
R7
33.0
R8
30.0k
D4
BAV21W-7-F
600V
i
R10
430.0k
R9
100.0k
7
6
SEC
9
8
T1
750313739
4
AUX
2
1
PRI
5
R11
180
C6
2200pF
SL44-E3/57T
D5
C7
1200μF
C8
0.1μF
-VOUT
R12
6.8k
+VOUT
2
1
J2
+VOUT
-VOUT
+5V 1.2A
www.ti.com
L2
6.8k
R2
C1
6.8μF
6.8k
R1
768772102
1mH
L1
CAUTION! HIGH VOLTAGE
UCC28910
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SLUS769D – JULY 2013 – REVISED DECEMBER 2016
Typical Application (continued)
Figure 34. UCC28910FBEVM-526 Schematic
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Typical Application (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
VIN
Input voltage
90
115/230
265
V
fLINE
Frequency
47
50/60
64
Hz
PNL
No load power
VIN = VNOM IOUT = 0 A
15
20
mW
VINUVLO
Brownout voltage
IOUT = INOM
70
V
VINOV
Brownout recovery voltage
80
V
IIN
Input current
0.2
A
VIN = VMIN, IOUT = max
OUTPUT CHARACTERISTICS
VOUT
Output voltage
VIN =VMIN to VMAX, IOUT = 0 V to INOM
4.75
5.00
5.25
V
IOUT(max)
Maximum output current
VIN = VMIN to VMAX
1.14
1.20
1.26
A
IOUT(min)
Minimum output current
Vin = Vmin to VMAX
ΔVOUT
Output voltage ripple
VIN = VMIN to VMAX, IOUT = 0 V to INOM
POUT
Output power
VIN = VMIN to VMAX
0
A
150
mV
SYSTEM CHARACTERISTICS
η
Average efficiency
25%, 50%, 75%, 100% of IOUT
75%
ENVIRONMENTAL
Conducted EMI
Meets CISPR22B/EN55022B
10.2.1.2 Detailed Design Procedure
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter based on
UCC28910 switcher. Refer to the Figure 35 for component names and network locations. The design procedure
equations use terms that are defined below.
L1
R1
C4
DOUT
R5
T1
DZ1
CSN
R4
D1
C2
C1
RSN
COUT
RPRL VOUT
UCC2891x
RIN
L2
1
GND DRAIN
2
GND
3
GND
4
IPK
8
D3
R3
VDD
6
VS
5
C3
RIPK
RS1
RS2
R2
Figure 35. Standard Flyback Converter Based on UCC2891x
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10.2.1.2.1 Power Handling Curves
The power handling curves give the maximum output power that can be handled by the devices versus the
ambient temperature. These curves give the maximum output power achievable considering that the losses
inside the device can cause rise of the junction temperature up to 125°C. The thermal resistance junction to
ambient were provided with considerations to two different values. Thermal resistances values of 50°C /W and of
100°C / W were considered.
The device handling capability depends on the overall design and input and output voltage. Figure 36 and
Figure 38 refer to a wide-range input voltage (90 VAC; 264 VAC) converter; Figure 37 and Figure 39 refer to a
European range input voltage (180 VAC; 265 VAC). The dotted line curves refer to 12-V output voltage AC-to-DC
converter, the continuous line curves refer to 5-V output voltage converter.
Figure 36 and Figure 37 show the power handling capabilities of UCC28910 and Figure 38 and Figure 39 show
the power handling capabilities of UCC28911.
Table 2. Maximum Output Power (1)
PART NUMBER
180 VAC to 265 VAC
Adapter
(1)
(2)
(3)
(2)
90 VAC to 265 VAC
Open Frame
(3)
Adapter (2)
UNITS
Open Frame
(3)
UCC28910
6.5
9.5
6
7.5
W
UCC28911
8
12
7.5
10
W
Table 2 is obtained considering 125°C as maximum junction temperature. For lower operating maximum junction temperature, the
maximum output power should be lower.
Typical continuous power in enclosed adapter at 50°C ambient, with adequate ( > 560 mm2) copper area connected on GND pin to have
90°C/W as junction to ambient thermal resistance.
Maximum continuous power with open frame design at 50°C ambient, with adequate copper area connected on GND pin and/or
adequate air flow to have 50°C/W as junction to ambient thermal resistance.
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The curves provided show the maximum power obtained through optimized designs.
A lower-efficiency design requires the converter to process more input power to deliver the same amount of
power to the load. Therefore, less power handling capability is expected for lower-efficiency designs.
14
10
Adapter POUT_MAX
VOUT = 5 V
VOUT = 12 V
Open Frame POUT_MAX
VOUT = 5 V
VOUT = 12 V
8
POUT_MAX (W)
7
6
Adapter POUT_MAX
VOUT = 5 V
VOUT = 12 V
Open Frame POUT_MAX
VOUT = 5 V
VOUT = 12 V
12
10
POUT_MAX (W)
9
5
4
3
8
6
4
2
2
1
0
20
40
60
80
100
Ambient Temperature (qC)
120
0
20
140
Figure 36. [90; 264] VRMS Input Voltage Range,
(maximum input power vs ambient temperature of
UCC28910)
120
140
D523
16
Adapter POUT_MAX
VOUT = 5 V
VOUT = 12 V
Open Frame POUT_MAX
VOUT = 5 V
VOUT = 12 V
10
Adapter POUT_MAX
VOUT = 5 V
VOUT = 12 V
Open Frame POUT_MAX
VOUT = 5 V
VOUT = 12 V
14
12
POUT_MAX (W)
12
POUT_MAX (W)
60
80
100
Ambient Temperature (qC)
Figure 37. [180; 264] VRMS Input Voltage Range,
(maximum input power vs ambient temperature of
UCC28910)
14
8
6
4
10
8
6
4
2
2
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
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0
20
40
60
80
100
Ambient Temperature (qC)
D524
Figure 38. 90 VRMS, 264 VRMS Input Voltage Range,
(maximum output power vs ambient temperature of
UCC28911)
32
40
D522
120
140
D525
Figure 39. 180 VRMS, 264 VRMS Input Voltage Range,
(maximum output power vs ambient temperature of
UCC28911)
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10.2.1.2.2 Input Stage Design and Bulk Capacitance
The input stage consists of:
1. Input fuse resistor (RIN) is generally used to:
(a) Limit the inrush current on the input capacitor when the line voltage is applied.
(b) Disconnect the line in case of input over current.
2. A bridge diode or a single-wave rectifier diode used to rectify the main voltage.
3. A bulk capacitor (capacitors C1 and C2) that stores the energy and reduces input voltage ripple.
4. A line filter (L1, L2, R1, and R2) to reduce EMI generated by switching.
The minimum input capacitance voltage, the input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
The maximum converter input power can be estimated from the output voltage in voltage constant mode, VOCV,
the converter's output current when operating in constant current more, IOCC, and the full-load efficiency target, η.
VOCV u IOCC
PIN
K
(6)
The following equation provides an accurate solution for input capacitance based on a target minimum bulk
capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the
target capacitance.
2 u PIN
CBULK
fLINE(min)
§ 1
§ VBULK(min)
1
u¨
u arccos ¨
¨
¨ RCT 2 u S
© 2 u VIN(min)
©
2
2
2 u VIN(min)
VBULK(min)
··
¸¸
¸¸
¹¹
(7)
In the case where the input rectifier is a single diode (half wave rectifier) , and for applications with bridge input
rectifier (full wave rectifier), as in the schematic of Figure 31.
The voltage VBULK(min) is generally selected around 65% to 60% of √2 x VIN(min). VBULK(min) is determined by the
selection of the high-voltage input capacitors.
For the considered example we have:
VOCV u IOCC 5V u 1.2 A
PIN
8.33 W
K
0.72
CBULK
2 u 8.33 W -° 1
u®
57Hz
¯° 2
§ 80 V · ½°
1
u arccos ¨
¸¾
2uS
© 124 V ¹ ¿°
2 u (88 V)2
(80 V)2
(8)
11.7 PF
(9)
Taking into account that electrolytic capacitance, with 20% of tolerance, the values selected for C1 and C2 are:
C1 = 6.8 μF and C2 = 10 μF.
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10.2.1.2.3 Transformer Turns Ratio
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time. Initially
determine the maximum available total duty cycle of the on-time and secondary conduction time based on target
switching frequency and DCM resonant time. For DCM resonant time, assume tR = 1 / 500 kHz if you do not
have an estimate from previous designs. For the transition mode operation limit, the period required from the end
of secondary current conduction to the first valley of the VDS voltage is half of the DCM resonant period, or 1 μs
assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.
§t
·
DMAX 1 ¨ R u fSW(max) ¸ K CC
© 2
¹
(10)
Where KCC is the regulation gain in constant current control mode and is equal to the secondary diode
conduction duty cycle when the converter is operating at maximum output current.
Once DMAX is known, the maximum turn ratio of the primary-to-secondary can be determined with the equation
below.
DMAX u VBULK(min)
NPS(max)
KCC u VOCV VF
(11)
The total voltage on the secondary winding needs to be determined; the sum of VOCV and the secondary rectifier
VF. The voltage VBULK(min) is generally selected around 65% or 60% of the peak of low-line. VBULK(min) is
determined by the selection of the high-voltage input capacitors.
For the 5-V USB charger applications NPS values from 13 to 17 are typically used.
For our example the maximum value for primary to secondary turn ratio will be:
0.482 u 80 V
NPS(max)
17.45
0.413 u 5V 0.35 V
(12)
In this example we fix NPS = 16.5
In order to calculate the primary to auxiliary turn ratio (NPA) we use the parameter VOCC(min) that is the minimum
output voltage at which we want to guarantee the output current regulation.
NPA
NPS u
VOCC(min)
VDDOFF(max)
VF
VFAUX
(13)
In the example:
NPA
16.5 u
2 V 0.35 V
7 V 0.5 V
5.17
(14)
In Equation 13 VFAUX is the D3 diode voltage drop when conducting. The value of NPA is generally underestimated and the number of auxiliary winding turns can be reduced with respect to the value provided by
Equation 13. Optimization can be done directly on the circuit verifying the margin between the VDD's measured
value and VDDOFF(max).
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10.2.1.2.4 Output Capacitance
The output capacitance value is typically determined by the transient response requirement from no load. For
example, in USB charger applications, it is often required to maintain a minimum output voltage of 4.1 V with a
load-step transient from 0 mA to 500 mA (ITRAN). The equation below assumes that the switching frequency is at
the minimum of fSW(min).
ITRAN
COUT
VO' u fSW(min)
(15)
COUT
500mA
5 V 4.1V u 420Hz
1.3mF
(16)
Another consideration on the output capacitor(s) is the ripple voltage requirement which is reviewed based on
secondary-peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation
below.
VRIPPLE
RESR
u 0.8
ID _ PK(max) u NPS
(17)
VRIPPLE is the maximum output-voltage ripple allowed for the design. The UCC2891x devices incorporates
internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the
value of COUT is high enough. The following equation determines a minimum value of COUT necessary to maintain
a phase margin >30 degrees over the full-load range.
400 u IOCC
COUT t
VOCV u fSW(max)
(18)
10.2.1.2.5 VDD Capacitance, CVDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain
the supply voltage. The output current available to the load to charge the output capacitors is the constantcurrent regulation target. The equation below assumes the output current of the flyback is available to charge the
output capacitance until the minimum output voltage is achieved. CVDD capacitor is the C3 capacitor in the
schematic of Figure 35.
COUT u VOCC u IRUN(max)
C VDD
IOCC u 'VUVLO
(19)
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10.2.1.2.6 VS Resistor Divider
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous switching operation.
RS1 is initially determined based on transformer auxiliary to primary turn ratio and desired input voltage operating
threshold.
RS1
VINAC(min) u 2
NPA u IVSLRUN(max)
124 V
5.17 u 215 PA
112k:
(20)
In our example the selected value of RS1 was 100 kΩ.
The low-side VS pin resistor is selected based on desired output voltage regulation.
VVSR u RS1 u NPA
4 V u 100k: u 5.17
RS2
30.5k:
(VOUT VF ) u NPS (VVSR u NPA )
5 V 0.35 V u 16.5 4 V u 5.17
(21)
The value selected for RS2 resistance was 30 kΩ.
10.2.1.2.7 RVDD Resistor and Turn Ratio
The value of RVDD and the auxiliary-to-secondary turns ratio should be selected with care in order to be sure that
the VDD is always higher than the VDDOFF (7 V maximum) threshold under all operating conditions. The RVDD
resistor also limits the current that can go into the VDD pin preventing IVDDCLP_OC clamp over-current protection
from being erroneously activated.
10.2.1.2.8 Transformer Input Power
The power at the transformer input during full-load condition is given by the output power plus the power loss in
the output diode plus the power consumption of the UCC2891x control logic (VVDD × IRUN) divided by the
transformer efficiency that takes into account all the losses due to the transformer: copper losses, core losses,
and energy loss in the leakage inductances.
VOCV VF u IOCC VVDD u IRUN
PINTRX
KXFMR
(22)
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10.2.1.2.9 RIPK Value
The RIPK value sets the value of the DRAIN current peak that equals the transformer primary winding current
peak value. This value also sets the value of the output current when working in CC mode according to the
following formula:
§
¨¨ KXFMR
©
IOUT
VVDD u IRUN
PINTRX
·
1
¸¸ u NPS u u ID _ PK(max) u DMAGCC
2
¹
§
¨¨ KXFMR
©
VVDD u IRUN
PINTRX
·
1 V
¸¸ u NPS u u CCR
2
RIPK
¹
where
•
•
•
KCC is the secondary diode conduction duty cycle Electrical Characteristics
NPS is the primary-to-secondary transformer turns ratio
VCCR is the defined as VCCR = VCSTE(max) × KCC and the value is specified in the Electrical Characteristics
(23)
§
VVDD u IRUN ·
¨¨ KXFMR
¸¸
PINTRX
¹ takes into account that not all the energy stored in the transformer goes to the
The term ©
secondary side but some of this energy, through the auxiliary winding, is used to supply the device control logic.
The transfer of energy always happens with unavoidable losses. These losses are accounted for through the
transformer efficiency term (ηXFMR). For a fixed target value for IOUT, the value of RIPK can be calculated using the
following formula:
RIPK
§
¨¨ KXFMR
©
VVDD u IRUN
PINTRX
·
1 V
¸¸ u NPS u u CCR
2 IOUT
¹
(24)
For the example:
5 V 0.35 V u 1.2 A 28 V u 2.9mA
PINTRX
7.25 W
0.9
§
2 u 28 V u 2.9mA ·
1 223 V
RIPK ¨ 0.9
1.374k:
¸ u 16.5 u u
7.25
W
2
1.2 A
©
¹
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(25)
(26)
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10.2.1.2.10 Transformer Primary Inductance Value
After you have fixed the maximum switching frequency and the maximum value of the primary current peak for
your application, the primary inductance value can be fixed by the following equation:
2 u PINTRX
LP(min)
1 LP _ Tol u fTARGET(max) u I2D _ PK(max)
(27)
LP_Tol is the tolerance on the primary inductance value of the transformer. Typical values of LP_Tol are between
±10% and ±15%)
ID_PK(max) is given by:
VCCR
ID _ PK(max)
RIPK
(28)
For the example:
LP
2 u 7.25 W
§ 540 ·
1 0.1 u 105kHz u ¨
¸
© 1.37 ¹
14.5 W
2
0.9 u 105kHz u 395mA
2
# 1mH
(29)
10.2.1.2.10.1 Secondary Diode Selection
The maximum reverse voltage that the secondary diode had to sustain can be calculated by the equation below
where a margin of 30% is considered. Usually for this kind of application a Schottky diode is used to reduce the
power losses due to the lower forward voltage drop. The maximum current rating of the diode is generally
selected between two and five times the maximum output current (IOCC).
§
VIN(max) u 2 ·
¸ u 1.3
VREV ¨ VOCV
¨
¸
NPS
©
¹
(30)
VREV
§
¨¨ 5 V
©
265 u 2 ·
¸ u 1.3
16.5 ¸¹
36 V
(31)
10.2.1.2.11 Pre-Load
When no load is applied on the converter output, the output voltage rises until the OVP (over voltage protection)
of the device is tripped, because the device cannot operate at zero switching frequency. The device's minimum
switching frequency of 420 Hz will always deliver some energy to the output, causing the voltage to rise at no
load. To avoid this, an RPRL (pre-load resistance) is used. The value of this pre-load can be selected using the
following equation:
RPRL
RPRL
38
2
VOCV
§ ID _ PK(max) ·
KXFMR
u LP u 1 LP _ Tol u fMAX u ¨
¸
2
© K AM
¹
5V
VDDOFF(min) u IWAITQ(min)
(32)
2
0.9
§ 395mA ·
u 1mH u 1.1 u fSW(min) u ¨
¸
2
3
©
¹
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# 6.8k:
2
7 V u 200 PA
(33)
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10.2.1.2.12 DRAIN Voltage Clamp Circuit
The main purpose of this circuit, as in most flyback converters, is to prevent the DRAIN voltage from rising up to
the FET break-down voltage, at the FET turn-off, and destroying the FET itself. An additional task, required by
the primary-side regulation mechanism, is to provide a clean input to the VS pin by damping the oscillation that is
typically present on the DRAIN voltage due to the transformer primary leakage inductance.
To perform damping, the D2 diode (refer to Figure 40) selected should not be a fast recovery diode (0.3 μs < trr <
1 μs) so the reverse current can flow in the RLC over damped circuit. This RLC circuit is formed by the transformer
primary-leakage inductance (LLKP), the resistance R4, and the capacitance C4. To ensure proper damping the
resistance R4 has to satisfy the following condition:
R4 ! 2 u
LLKP
C4
(34)
The capacitance C4 should not be too high so it does not require too much energy to be charged. Typical values
for C4 are between 100 pF and 1 nF.
The resistance, R5, has been added to discharge the C4 capacitance so at the next switching cycle diode D2 is
activated providing enough current and storage to have a reverse-recovery current large enough for proper
oscillation damping.
VBULK
C4
R5
DZ1
Transformer
Primary
Winding
R4
D2
VDRAIN
VDRAIN
Figure 40. DRAIN Clamp Circuit Options
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10.2.2 Application Curves
5.5
5.3
5.2
4.5
Output Voltage (V)
Output Voltage (V)
5.0
4.0
3.5
85 V
115 V
3.0
140 V
2.5
115 V
5.0
175 V
265 V
265 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
UL
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Output Current (A)
C017
Figure 41. Output V-I Characteristic
C018
Figure 42. Output V-I Characteristic Output Current
Regulation
5.5
85
5.0
75
4.5
65
85 V
4.0
115 V
3.5
140 V
175 V
3.0
230 V
Efficiency (%)
Output Voltage (V)
LL
4.7
Output Current (A)
55
45
35
2.5
265 V
25
2.0
LL
15
UL
1.5
1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32
Output Current (A)
40
230 V
4.8
230 V
1.5
140 V
4.9
175 V
2.0
85 V
5.1
115 VAC
230 VAC
5
0
1
2
3
4
5
6
Output Power (W)
C019
7
C020
Figure 43. Output V-I Characteristic Output Voltage
Regulation
Figure 44. Efficiency vs POUT Diagram
Figure 45. Ripple with 5-V, 1.2-A Output, 85 VAC Input,
20 mV/div, 5 µs/div
Figure 46. Ripple with 5-V,1.2-A Output, 265-VAC Input,
20 mV/div 5 µs/div
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Figure 47. EMI Test Results per EN55022, Class B. 115 VAC
Input
Figure 48. EMI Test Results per EN55022, Class B. 230-VAC
Input
10.2.2.1 Average Efficiency Performance and Standby Power of the UCC28910FBEVM-526
Table 3 summarizes the average efficiency performance of the UCC28910FBEVM-526 and Table 4 summarizes
the standby power that is the no-load power consumption of the converter.
Table 3. Average Efficiency Performance of the UCC28910FBEVM-526
VIN (VAC)
f (Hz)
115
60
230
50
PIN (W)
IOUT (A)
VOUT (V)
POUT (W)
EFFICIENCY
(%)
7.826
1.201
4.950
5.943
75.94
5.845
0.901
4.942
4.451
76.15
3.889
0.601
4.934
2.964
76.19
1.930
0.301
4.927
1.481
76.73
7.721
1.201
4.956
5.950
77.06
5.783
0.901
4.948
4.457
77.07
3.853
0.601
4.938
2.966
76.97
1.960
0.301
4.930
1.482
75.60
AVERAGE
EFFICIENCY
(%)
76.25
76.68
Table 4. Standby Power, No-Load Power Consumption of the Converter
VIN (VAC)
f (Hz)
PIN (mW)
88
60
10
115
60
10
230
50
10
265
50
12
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10.2.3 Multi-Output Converter with UCC2891x Devices
Secondary1 Current
VOUT1
Primary Current
Secondary2 Current
UCC28910
1
GND DRAIN
2
GND
3
GND
4
IPK
VOUT2
8
VDD
6
VS
5
Figure 49. Multi-Output Flyback Converter
UCC2891x devices perform the output voltage regulation through PSR (Primary-Side Regulation). With PSR the
output voltage is sensed sampling the auxiliary winding at the end of the transformer demagnetization. With
multi-output flyback that implies multiple-secondary windings, the demagnetization time is not uniquely defined.
We have multiple demagnetization time, one for each secondary winding. If secondary windings are well coupled
together the UCC2891x samples the auxiliary winding at the end of the last demagnetization. (See Figure 50).
Auxiliary Winding Voltage
Last Demagnetization
t
Winding Currents
Primary Current
Secondary 1
Current
Secondary 2
Current
t
Figure 50. Winding Current Waveform in Multi-Output Flyback Converter
42
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In multiple output flyback converter regardless if they use primary-side regulation or secondary-side regulation,
the output voltages are not regulated at the target values in all the load ranges. This is called a cross-regulation
problem. To minimize this problem, if the two outputs refer to the same ground voltage, the output stage can be
configured as a DC stacked output, instead of staked windings (see Figure 51).
Stacked Windings
DC Stacked Outputs
Figure 51. Stacked Windings and DC Stacked Outputs
10.2.4 Do’s and Don'ts
Always design the converter to operate at maximum switching frequency (see fSW(max) in Electrical
Characteristics).
Select the RIPK to meet maximum output current requirement according to equation provided as first steps and
fine tune the value on the real circuit according to design specification.
Provide enough copper area, connected to GND pins, to provide heat sinking capabilities.
Design the converter to keep junction temperature below 125°C in the worst case condition (maximum ambient
temperature, minimum input voltage and maximum load). Estimate the junction temperature by measuring the
GND pins temperature. The GND pins temperature are between 5°C to 15°C lower than the junction
temperature.
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11 Power Supply Recommendations
UCC28910 and UCC28911 are intended for AC-to-DC adapters and chargers with input voltage range of 85
VAC(rms) to 265 VAC(rms) using Flyback topology. It can be used in other applications and converter topologies with
different input voltages. Be sure that all voltages and currents are within the recommended operating conditions
and absolute maximum ratings of the device.
To maintain output current regulation over the entire input voltage range, design the converter to operate close to
fMAX when in full-load conditions.
To improve thermal performance increase the copper area connected to GND pins.
12 Layout
12.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to follow the here below
guidelines.
1. Place the RIPK resistance as close as possible to the device with the shortest available traces.
2. Try to minimize the area of DRAIN trace, this helps in keeping EMI disturbance low.
3. A copper area connected to the GND pins improves heat sinking thermal performance.
4. A copper area connected to anode and cathode secondary diode improves heat sinking with an emphasis on
the quiet area of the diode, the diode connected to the output capacitor, this limits the EMI disturbance.
5. Place the auxiliary voltage sense resistor divider (RS1 and RS2 in Figure 52) directly on the VS pin keeping
traces as short as possible.
12.2 Layout Example
VIN_AC
CCLP
T1
DOUT
RCLP
CB2
D1
UCC28910
GND
DRAIN
GND
COUT
RIPK
GND
VDD
IPK
VS
RS1
~
~
CB1
RS2
+
-
D2
CDD
RPRL
RDD
VOUT
Figure 52. UCC28910 Layout Example
44
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Device Nomenclature
13.1.1.1 Definition of Terms
Capacitance Terms in Farads
• CBULK: total input capacitance of CB1 and CB2.
• CVDD: capacitance on the VDD terminal.
• COUT: output capacitance.
Duty Cycle Terms
• KCC: secondary diode conduction duty cycle in CC, (see Electrical Characteristics).
• DMAX: MOSFET on-time maximum duty cycle.
Frequency Terms in Hertz
• fLINE: minimum line frequency.
• fTARGET(max): target full-load maximum switching frequency of the converter.
• fMIN: minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device.
• fSW(min): minimum switching frequency (see Electrical Characteristics)
Current Terms in Amperes
• IOCC: converter output current target when operating in constant current mode.
• ID_PK(max): maximum transformer primary current peak.
• ITRAN: required positive load-step current.
• IRUN: maximum current consumption of the device (see Electrical Characteristics).
• IVSLRUN: VS terminal run current (see Electrical Characteristics).
Current and Voltage Scaling Terms
• KAM: maximum-to-minimum peak-primary current ratio (see Electrical Characteristics).
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Documentation Support (continued)
Transformer Terms
• LP: transformer primary inductance.
• NPA: transformer primary-to-auxiliary turns ratio.
• NPS: transformer primary-to-secondary turns ratio.
Power Terms in Watts
• PIN: converter maximum input power.
• PINTRX: transformer maximum input power.
• POUT: full-load output power of the converter.
• PSB: total stand-by input power.
Resistance Terms in Ω
• RIPK: primary current programming resistance.
• RESR: total ESR of the output capacitors.
• RPRL: preload resistance on the output of the converter.
• RS1: high-side VS terminal resistance.
• RS2: low-side VS terminal resistance.
Timing Terms in Seconds
• tDMAG(min): minimum secondary rectifier conduction time.
• tON(min): minimum MOSFET on time.
• tR: resonant frequency during the DCM (discontinuous conduction mode) time.
Voltage Terms in Volts
• VBULK: highest bulk capacitor voltage for stand-by power measurement.
• VBULK(min): minimum voltage on CB1 and CB2 at full power.
• VCCR: constant-current regulating voltage (see Electrical Characteristics).
• VOΔ: output voltage drop allowed during the load-step transient.
• VDSPK: peak MOSFET drain-to-source voltage at high line.
• VF: secondary rectifier, DOUT, forward voltage drop at near-zero current.
• VFA: auxiliary rectifier, D2, forward voltage drop.
• VOCV: regulated output voltage of the converter, VOUT in CV mode.
• VVDD: voltage value on VDD terminal.
• VOCC: target lowest converter output voltage in constant-current regulation.
• VREV: peak reverse voltage on the secondary rectifier, DOUT.
• VRIPPLE: output peak-to-peak ripple voltage at full-load.
• VVSR: CV regulating level at the VS input (see Electrical Characteristics).
• ΔVUVLO: VDDON – VDDOFF (see Electrical Characteristics).
AC Voltage Terms in VRMS
• VIN(max): maximum AC input voltage to the converter.
• VIN(min): minimum AC input voltage to the converter.
• VIN(run): converter input start-up (run) AC voltage.
Efficiency Terms
• η: converter overall efficiency.
• ηXFMR: transformer primary-to-secondary power transfer efficiency.
46
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Documentation Support (continued)
13.1.2 Related Documents
Using the UCC28910 EVM-526, Evaluation Module, Texas Instruments Literature Number SLUUAI4
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13.5 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC28910,
UCC28911
Click here
Click here
Click here
Click here
Click here
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28910D
ACTIVE
SOIC
D
7
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28910
UCC28910DR
ACTIVE
SOIC
D
7
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28910
UCC28911D
ACTIVE
SOIC
D
7
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28911
UCC28911DR
ACTIVE
SOIC
D
7
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28911
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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