UCC37321DG4

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 UCC2732x/UCC3732x Single 9-A High-Speed Low-Side Mosfet Driver With Enable 1 Features 2 Applications • • • • • • • 1 • • • • • • • • • Industry-Standard Pin-Out With Addition of Enable Function High-Peak Current Drive Capability of ±9 A at theMiller plateau region Using TrueDrive Efficient Constant Current Sourcing Using a Unique BiPolar and CMOS Output Stage TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and Fall Times With 10-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising 4-V to 15-V Supply Voltage Available in Thermally Enhanced MSOP PowerPAD™ Package With 4.7°C/W θjc Rated From –40°C to +105°C Pb-Free Finish (CU NIPDAU) on 8-pin SOIC and PDIP Packages Switch Mode Power Supplies DC-DC Converters Motor Controllers Class-D Switching Amplifiers Line Drivers Pulse Transformer Drivers 3 Description The UCC2732x/UCC3732x family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity, and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322). Device Information(1) PART NUMBER UCC2732x UCC3732x PACKAGE BODY SIZE (NOM) MSOP-PowerPAD (8) 3.00 mm × 3.00 mm SOIC (8) 3.91 mm × 4.90 mm PDIP (8) 6.35 mm × 9.81 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram VDD 1 8 VDD INVERTING 7 OUT VDD IN 2 ENBL 3 AGND 4 NON-INVERTING 6 OUT RENBL 100 kΩ 5 PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 4 4 4 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Power Dissipation Ratings ........................................ Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 14 9 Application and Implementation ........................ 15 9.1 Application Information............................................ 15 9.2 Typical Application ................................................. 15 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 20 11.3 Thermal Information .............................................. 20 12 Device and Documentation Support ................. 21 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2013) to Revision H • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision F (March 2012) to Revision G Page • Updated AGND pin description. ............................................................................................................................................ 3 • Changed minimum value for input voltage from –5 to –0.3 V in the Absolute Maximum Ratings table. ............................... 4 • Added CLOAD = 10 nF to Fall Time vs Supply Voltage graph ................................................................................................. 8 • Changed Changed x-axis values from 1, 10, 100 to 0.1, 1, 10 in Rise Time vs Load Capacitance graph ........................... 8 • Changed Changed x-axis values from 1, 10, 100 to 0.1, 1, 10 in Fall Time vs Output Capacitance graph .......................... 8 2 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 5 Description (continued) Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive current where it is most needed at theMiller plateau region during the MOSFET switching transition. A unique hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low supply voltages. With this drive architecture, UCC3732x can be used in industry standard 6-A, 9-A and many 12A driver applications. Latch up and ESD protection circuitries are also included. Finally, the UCC3732x provides an enable (ENBL) function to have better control of the operation of the driver applications. ENBL is implemented on pin 3, which was previously left unused in the industry standard pinout. It is internally pulled up to VDD for active high logic and can be left open for standard operation. In addition to the 8-pin SOIC (D) and 8-pin PDIP (P) package offerings, the UCC3732x also comes in the thermally enhanced but tiny 8-pin MSOP PowerPAD™ (DGN) package. The PowerPAD package drastically lowers the thermal resistance to extend the temperature operation range and improve the long-term reliability. 6 Pin Configuration and Functions P, D, and DGN Packages 8-Pin PDIP, SOIC, and MSOP With PowerPAD Top View VDD IN ENBL AGND 1 8 2 7 3 6 4 5 VDD OUT OUT PGND Pin Functions PIN NAME NO. I/O DESCRIPTION AGND 4 — The AGND and the PGND must be connected by a single thick trace directly under the device. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 8) and PGND and a separate 0.1-µF capacitor between VDD (pin 1) and AGND. The power MOSFETs must be located on the PGND side of the device while the control circuit must be on the AGND side of the device. The control circuit ground must be common with the AGND while the PGND must be common with the source of the power FETs. ENBL 3 I Enable input for the driver with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. When the device is disabled, the output state is, low regardless of the input state. IN 2 I Input signal of the driver which has logic compatible threshold and hysteresis. 6, 7 O Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET. 5 — Common ground for output stage. This ground must be connected very closely to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output switching di/dt which can affect the input threshold. 1, 8 I Supply voltage and the power input connections for this device. Two pins must be connected together externally. OUT PGND VDD Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT –0.3 16 V 0.6 A Input voltage (IN), VIN –0.3 6 V or VDD + 0.3 (3) V Enable voltage (ENBL) –0.3 6 V or VDD + 0.3 (3) V 650 mW Supply voltage, VDD Output current (OUT) DC, IOUT_DC D package Power dissipation at TA = 25°C DGN package P package Lead temperature (soldering, 10 s) 3 W 350 mW 300 °C Junction operating temperature, TJ –55 150 °C Storage temperature, Tstg –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating ConditionsRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Whichever is larger 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VDD NOM MAX 4.5 15 UNIT V 7.4 Thermal Information UCC27322 THERMAL METRIC (1) UCC27321 D (SOIC) P (PDIP) DGN (MSOPPowerPAD) UNIT 8 PINS 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 56.6 55.9 56.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.8 45.3 52.9 °C/W RθJB Junction-to-board thermal resistance 32.6 32.6 32.7 °C/W ψJT Junction-to-top characterization parameter 1.8 23.0 1.8 °C/W ψJB Junction-to-board characterization parameter 32.3 32.5 32.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 — 5.9 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 7.5 Electrical Characteristics VDD = 4.5 V to 15 V, TA = –40°C to +105°C for UCC2732x, TA = 0°C to 70°C for UCC3732x, TA = TJ, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT (IN) VIN_H, logic 1 input threshold 2 V VIN_L, logic 0 input threshold 0 V ≤ VIN ≤ VDD Input current –10 1 V 10 µA 150 300 mV 0 OUTPUT (OUT) Peak output current (1) (2) VDD = 14 V, VOH, output high level VOH = VDD – VOUT, IOUT = –10 mA VOL, output low level IOUT = 10 mA 11 25 mV Output resistance high (3) IOUT = –10 mA, VDD = 14 V 15 25 Ω Output resistance low (3) IOUT = 10 mA, VDD = 14 V 1.1 2.2 Ω Latch--up protection (1) 9 A 500 mA OVERALL IN = LOW, EN = LOW, VDD = 15 V 150 225 UCC37321 IN = HIGH, EN = LOW, VDD = 15 V UCC27321 IN = LOW, EN = HIGH, VDD = 15 V 440 650 370 550 IN = HIGH, EN = HIGH, VDD = 15 V 370 550 IN = LOW, EN = LOW, VDD = 15 V 150 225 UCC37322 IN = HIGH, EN = LOW, VDD = 15 V UCC27322 IN = LOW, EN = HIGH, VDD = 15 V 450 650 75 125 IN = HIGH, EN = HIGH, VDD = 15 V 675 1000 IDD, static operating current µA ENABLE (ENBL) VIN_H, high-level input voltage LOW to HIGH transition 1.7 2.2 2.7 VIN_L, low-level input voltage HIGH to LOW transition 1.1 1.6 2 0.25 0.55 0.90 75 100 135 Hysteresis RENBL, enable impedance (1) (2) (3) VDD = 14 V, ENBL = GND V V kΩ Ensured by design. Not tested in production. The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE (ENBL) tD3, propagation delay time (1) CLOAD = 10 nF 60 90 ns tD4, propagation delay time (1) CLOAD = 10 nF 60 90 ns tR, rise time (OUT) CLOAD = 10 nF 20 70 ns tF, fall time (OUT) CLOAD = 10 nF 20 30 ns tD1, propagation delay, IN rising (IN to OUT) CLOAD = 10 nF 25 70 ns tD2, propagation delay, IN falling (IN to OUT) CLOAD = 10 nF 35 70 ns SWITCHING TIME (2) (1) (2) See Figure 2. See Figure 1 for switching waveforms. 7.7 Power Dissipation Ratings PACKAGE SUFFIX θjc (°C/W) θja (°C/W) Power Rating (mW) TA = 70°C (1) Derating Factor Above 70°C (mW/°C) (1) SOIC-8 D 42 84 to 160 (2) 344 to 655 (2) 6.25 to 11.9 (2) PDIP-8 P 49 110 500 9 MSOP PowerPAD-8 DGN 4.7 50 to 59 1370 17.1 (1) (2) 125°C operating junction temperature is used for power rating calculations The range of values indicates the effect of the printed-circuit-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the printed-circuit-board where possible to spread the heat away form the device more effectively. For additional information on device temperature management, see the Packaging Information section of the Power Supply Control Products Data Book, (SLUD003). (a) ( b) 5V IN 0V VTH VTH tD1 tD2 VTH IN VTH tD1 tD2 tF VDD 80% 80% tR OUT 20% 80% OUT 80% tR tF 20% 0V The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 1. Switching Waveforms for (a) Inverting Input to (b) Output Times 6 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 5V ENBL VIN_L VIN_H 0V tD3 tD4 VDD 80% OUT 80% tR tF 20% 0V The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveform for Enable to Output Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 7.8 Typical Characteristics 700 700 600 ENBL = 0V IN = 5V 500 400 IDD – InputCurrentIdle – μA IDD – InputCurrentIdle – μA 600 ENBL = VDD IN = 5V 300 ENBL = 0V IN = 0V 200 400 ENBL = 0V IN = 0V 300 ENBL = VDD IN = 5V 200 ENBL = VDD , IN = 0V 100 100 ENBL = VDD , IN = 0V 0 0 2 0 4 6 8 10 12 VDD – Supply Voltage – V 14 16 0 700 700 IDD – InputCurrentIdle – μA 800 ENBL = LO IN = HI ENBL = HI IN = LO ENBL = HI IN = HI 500 400 ENBL = LO IN = LO 300 4 6 8 10 200 0 -- 50 16 ENBL = HIIGH IN =HIIGH 600 ENBL = LOW 500 IN = HIIGH 400 ENBL = LOW IN = LOW 300 ENBL = HIIGH IN = LOW 200 -- 25 0 25 50 75 100 0 -- 50 125 -- 25 TJ – Temperature – °C 0 25 50 100 75 125 TJ – Temperature – °C Figure 5. Input Current Idle vs Temperature (UCCx7321) Figure 6. Input Current Idle vs Temperature (UCCx7322) 70 70 C LOAD = 10 nF CLOAD = 10 n F 60 60 tA = – 40°C 50 tR – Fall Time – ns 50 tR – Rise Time – ns 14 100 100 40 tA = 105°C tA = 25°C 30 40 30 tA = 105°C tA = 25°C 20 20 tA = 0°C 10 10 tA = 0°C tA = –40°C 0 0 4 6 8 10 12 14 16 VDD – Supply Voltage – V Figure 7. Rise Time vs Supply Voltage 8 12 Figure 4. Input Current Idle vs Supply Voltage (UCCx7322) 800 600 2 VDD – Supply Voltage – V Figure 3. Input Current Idle vs Supply Voltage (UCCx7321) IDD – InputCurrentIdle – μA ENBL = 0V IN = 5V 500 Submit Documentation Feedback 4 6 8 10 12 VDD -- Supply Voltage -- V 14 16 Figure 8. Fall Time vs Supply Voltage Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 Typical Characteristics (continued) 40 200 VDD = 5 V VDD = 5 V 160 VDD = 10 V VDD = 10 V VDD = 15 V tR – Fall Time – ns tR – Rise Time – ns 30 VDD = 15 V 20 120 80 10 40 0 0.1 1 0 10 0.1 1 CLOAD – Load Capacitance – nF CLOAD –- Load Capacitance – nF 10 Figure 10. Fall Time vs Output Capacitance Figure 9. Rise Time vs Load Capacitance 70 70 CLOAD = 10 n F CLOAD = 10 n F tA = 105°C 60 60 tA = 25°C 50 tD2 – Delay Time -- ns tD1 -– Delay Time -- ns tA = 105°C 50 tA = 25°C 40 30 20 40 30 tA = 0°C 20 tA = –40°C tA = –40°C 10 10 tA = 0°C 0 0 4 6 8 10 12 14 16 4 VDD – Supply Voltage – V 8 10 12 14 16 VDD – Supply Voltage – V Figure 11. tD1 Delay Time vs Supply Voltage Figure 12. tD2 Delay Time vs Supply Voltage 70 70 60 60 VDD = 5 V 50 VDD = 5 V tD2 – Delay Time – ns tD1 – Delay Time –- ns 6 VDD = 10 V 40 30 20 50 40 30 VDD = 15 V VDD = 10 V 20 VDD = 15 V 10 10 0 1 10 100 CLOAD – Load Capacitance – nF Figure 13. tD1 Delay Time vs Load Capacitance Copyright © 2002–2016, Texas Instruments Incorporated 0 1 10 CLOAD – Load Capacitance – nF 100 Figure 14. tD2 Delay Time vs Load Capacitance Submit Documentation Feedback 9 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) 2.0 50 45 VDD = 15 V CLOAD = 10 n F TA = 25°C tD2 Propagation Time -- ns tRISE 35 30 25 20 15 10 tFALL tD1 1.9 VON – Input Threshold Voltage – V 40 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4. 5 V 1.4 1.3 5 0 0 5 10 VIN(peak) – Peak Input Voltage – V 1.2 --50 15 -- 25 0 25 50 75 100 125 TJ – Temperature – °C Figure 15. Propagation Times vs Peak Input Voltage Figure 16. Input Threshold vs Temperature 150 3.0 140 ENBL -- ON 2.5 130 RENBL – Enable Resistance – Ω Enable thresholdand hysteresis – V VDD = 15 V 2.0 1.5 1.0 ENBL -- OFF 120 110 100 90 80 70 0.5 60 ENBL -- HYSTERESIS 0 -- 50 -- 25 0 25 50 75 TJ – Temperature –°C 100 50 -- 50 125 --25 0 25 50 75 Figure 17. Enable Threshold and Hysteresis vs Temperature 125 Figure 18. Enable Resistance vs Temperature IN = GND ENBL = VDD VDD – Input Voltage – V 1 V/div IN = GND ENBL = V DD VDD – Input Voltage – V 1 V/div 100 TJ – Temperature – °C VDD OUT OUT 0V 0V 10 nF Between Output and GND 50 μs/div Figure 19. Output Behavior vs VDD (UCC37321) 10 Submit Documentation Feedback VDD 10 nF Between Output and GND 50 μs/div Figure 20. Output Behavior vs VDD (UCC37321) Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 Typical Characteristics (continued) IN = VDD ENBL = VDD VDD – Supply Voltage – V 1 V/div VDD – Supply Voltage – V 1 V/div IN = VDD ENBL = VDD VDD OUT VDD OUT 0V 0V 10 nF Between Output and GND 50 μs/div Figure 21. Output Behavior vs VDD (Inverting) 10 nF Between Output and GND 50 μs/div Figure 22. Output Behavior vs VDD (Inverting) IN = GND ENBL = VDD VDD OUT 0V VDD – Supply Voltage – V 1 V/div VDD – Supply Voltage – V 1 V/div IN = GND ENBL = VDD VDD OUT 0V 10 nF Between Output and GND 50 μs/div 10 nF Between Output and GND 50 μs/div Figure 23. Output Behavior vs VDD (Noninverting) Figure 24. Output Behavior vs VDD (Noninverting) Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 11 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 8 Detailed Description 8.1 Overview The UCC37321 and UCC37322 drivers serve as an interface between low-power controllers and power MOSFETs. They can also be used as an interface between DSPs and power MOSFETs. High-frequency power supplies often require high-speed, high-current drivers such as the UCC3732x family. A leading application is the need to provide a high power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device gates through a drive transformer. Synchronous rectification supplies must simultaneously drive multiple devices which can present an extremely large load to the control circuitry. The inverting driver (UCC37321) is useful for generating inverted gate drive signals from controllers that have only outputs of the opposite polarity. For example, this driver can provide a gate signal for ground referenced, N-channel synchronous rectifier MOSFETs in buck derived converters. This driver can also be used for generating a gate drive signal for a P-channel MOSFET from a controller that is designed for N-channel applications. MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high-frequency switching noise by placing the high current driver physically close to the load. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC3732x. Finally, the control device may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. 8.2 Functional Block Diagram VDD 1 8 VDD INVERTING 7 OUT VDD IN 2 ENBL 3 AGND 4 NON-INVERTING 6 OUT RENBL 100 kΩ 5 PGND 8.3 Feature Description 8.3.1 Input Stage The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltages; yet, it is equally compatible with 0 V to VDD signals. The inputs of UCC3732x family of drivers are designed to withstand 500-mA reverse current without either damage to the device or logic upset. In addition, the input threshold turnoff of the UCC3732x has been slightly raised for improved noise immunity. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (< 200 ns). The IN input of the driver functions as a digital gate, and it is not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. 12 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 Feature Description (continued) Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in Thermal Information. 8.3.2 Output Stage The TrueDrive output stage is capable of supplying ±9-A peak current pulses; it swings to both VDD and GND and can encourage even the most stubborn MOSFETs to switch. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. This unique BiPolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low supply voltages. The UCC3732x family delivers 9 A of gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region – providing improved efficiency gains. 8.3.3 Source and Sink Capabilities during Miller Plateau Large power MOSFETs present a significant load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC3732x drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging or discharging of the drain-gate capacitance with current supplied or removed by the driver device. Two circuits are used to test the current capabilities of the UCC3732x driver (see Reference (1)) . In each case external circuitry is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 25 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC37321 is found to sink 9 A at VDD = 15 V. VDD UCC37321 INPUT 1 VDD 2 VDD 8 OUT IN OUT 3 ENBL 4 DSCHOTTKY C2 1 μF 6 PGND 5 AGND 10 Ω 7 C3 100 μF + VSUPPLY 5.5 V VSNS 1 μF CER 100 μF AL EL RSNS 0.1 Ω UDG-- 01113 Figure 25. Sink Current Test Circuit The circuit in Figure 26 is used to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC37321 is found to source 9 A at VDD = 15 V. Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 13 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) VDD UCC37321 INPUT 1 VDD VDD 8 IN OUT DSCHOTTKY 2 7 C2 1μ F OUT 3 4 ENBL AGND 6 C3 100 μF 4.5 V DADJ PGND 5 VSNS 1μ F CER 100 μF AL EL RSNS 0.1 Ω UDG-- 01114 Figure 26. Source Current Test Circuit Note that the current sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In most it is advantageous that the turnoff capability of a driver is stronger than the turnon capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON. 8.3.4 Enable The UCC37321/2 provides an enable input for improved control of the driver operation. This input also incorporates logic compatible thresholds with hysteresis. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. When ENBL is high, the device is enabled and when ENBL is low, the device is disabled. The default state of the ENBL pin is to enable the device and therefore it can be left open for standard operation. The output state when the device is disabled is low regardless of the input state. See Table 1 for the operation using enable logic. ENBL input is compatible with both logic signals and slow changing analog signals. It can be directly driven or a power-up delay can be programmed with a capacitor between ENBL and AGND. 8.4 Device Functional Modes Table 1 lists the logic of this device. Table 1. Device Logic Table INVERTING UCC37321 NON-INVERTING UCC37322 14 Submit Documentation Feedback ENBL IN OUT 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information High-current gate driver devices are required in switching power applications for a variety of reasons. To enable fast switching of power devices and reduce associated power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive the gates of the switching devices. The situation may be encountered because the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the logic-level signal to the gatedrive voltage to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar, (or P- N- channel MOSFET), transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting and buffer drive functions. Gate drivers may also minimize the effect of switching noise by locating the high-current driver physically close to the power switch, drive gate-driver transformers and control floating power device gates, reducing power dissipation and thermal stress in controllers by absorbing gate-charge power losses. In summary gate drivers are extremely important components in switching power combining benefits of highperformance, low-cost, low component count, board-space reduction, and simplified system design. 9.2 Typical Application 8 VDD 1 VDD C2 OUT 6 OUT 7 Q1 R4 UCC27322D 2 INPUT 3 IN AGND 4 ENBL PGND 5 ENABLE Figure 27. Typical Application Diagram of UCC27322 and UCC37322 9.2.1 Design Requirements When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. The following design parameters should be used when selecting the proper gate driver device for an end application: input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and disable functions, propagation delay, power dissipation, and package type. See the example design parameters and requirements in Table 2. Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 15 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com Table 2. Design Parameters (1) DESIGN PARAMETER EXAMPLE VALUE Input-to-output configuration Noninverting Input threshold type CMOS Bias supply voltage levels 12 V dVDS/dt (1) 20 V/ns Enable function Yes Propagation delay < 50 ns Power dissipation < 0.45 W Package type SOIC (8) dVDS/dt is a typical requirement for a given design. This value can be used to find the peak source/sink currents needed as shown in Peak Source and Sink Currents. 9.2.2 Detailed Design Procedure 9.2.2.1 Input-to-Output Configuration The design should specify which type of input-to-out configuration should be used. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the noninverting configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the inverting configuration must be chosen. Based on this noninverting requirement of this application, the proper device out of the UCC27322 or UCC37322 should be selected. 9.2.2.2 Input Threshold Type The type of input voltage threshold determines the type of controller that can be used with the gate driver device. The UCC2732x and UCC3732x devices feature a TTL and CMOS-compatible input threshold logic, with wide hysteresis. The threshold voltage levels are low voltage and independent of the VDD supply voltage, which allows compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. See Electrical Characteristics for the actual input threshold voltage levels and hysteresis specifications for the UCC2732x and UCC3732x devices. 9.2.2.3 VDD Bias Supply Voltage The bias supply voltage to be applied to the VDD pins of the device must never exceed the values listed in Recommended Operating Conditions. However, different power switches require different voltage levels to be applied at the gate. With a wide operating range from 4.5 V to 15 V, the UCC2732x and UCC3732x can be used to drive a variety of power switches, such as Si MOSFETs (for example, Vgs = 4.5 V, 10 V, 12 V), IGBTs (VGE=15 V), and wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be applied to the gate terminals). 9.2.2.4 Peak Source and Sink Currents Generally, the switching speed of the power switch during turnon and turnoff must be as fast as possible to minimize switching power losses. The gate driver device must be able to provide the required peak current for achieving the targeted switching speeds for the targeted power MOSFET. Using the example of a power MOSFET, the system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dvDS/dt). For example, the system requirement might state that a SPP20N60C3 power MOSFET must be turned on with a Dvds/dt of 20 V/ns or higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching application and reducing switching power loss is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET turnon event (from 400 V in the OFF state to VDS(on) in ON state) must be completed in approximately 20 ns or less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (Qgd parameter in SPP20N60C3 power MOSFET data sheet is 33 nC typically) is supplied by the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power MOSFET, VGS(th)). 16 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 To achieve the targeted Dvds/dt, the gate driver must be capable of providing the Qgd charge in 20 ns or less. In other words, a peak current of 1.65 A (= 33 nC) / 20 ns) or higher must be provided by the gate driver. The UCC2732x and UCC3732x devices can provide 9-A peak sourcing/sinking current which clearly exceeds the design requirement and has the capability to meet the switching speed needed. This 9-A peak sourcing/sinking current provides an extra margin against part-to-part variations in the Qgd parameter of the power MOSFET along with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI optimizations. However, in practical designs the parasitic trace in the gate driver circuit of the PCB will have a definitive role to play on the power MOSFET switching speed. The effort of this trace inductance is to limit the di/dt of the output current pulse of the gate driver. To illustrate this effect, consider output current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (0.5 × IPEAK × time) would equal the total gate charge of the power MOSFET (Qg parameter in SPP20N60C3 power MOSFET data sheet= 87 nC typically). If the parasitic trace inductance limits the di/dt then a situation may occur in which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the Qg required for the power MOSFET switching. In other words, the time parameter in the equation would dominate and the IPEAK value of the current pulse would be much less than the true peak current capability of the device, while the required Qg is still delivered. Because of this, the desired switching speed may not be realized, even when theoretical calculations indicate the gate driver can achieve the targeted witching speed. Thus, placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver. 9.2.2.5 Enable and Disable Function Certain applications demand independent control of the output state of the driver without involving the input signal. A pin which offers enable and disable functions achieves the requirements. For these applications, the UCC2732x and UCC3732x are suitable as they feature an input pin and an Enable pin. 9.2.2.6 Propagation Delay The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC2732x and UCC3732x devices feature 25-ns turnon propagation delay and 35-ns turnoff propagation delay (typical), which ensure very little distortion and allow operation at higher frequencies. See Electrical Characteristics for the propagation and Switching Characteristics of the UCC2732x and UCC3732x devices. 9.2.2.7 Power Dissipation The UCC3732x family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the most common type of switching device used in high-frequency power conversion equipment. References (1) and (2) contain detailed discussions of the drive current required to drive a power MOSFET and other capacitive-input switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinent to calculating gate drive current requirements will be summarized here; the original document is available from the TI website. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 1. 1 E = CV2 2 where • • C is the load capacitor V is the bias voltage feeding the driver Copyright © 2002–2016, Texas Instruments Incorporated (1) Submit Documentation Feedback 17 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by Equation 2. 1 P = 2 ´ CV2f 2 where • f is the switching frequency (2) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An example using the conditions of the previous gate-drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as shown in Equation 4. P = 10 nF × (12)2 × (300 kHz) = 0.432 W (3) With a 12-V supply, this would equate, as shown in Equation 4, to a current of: P 0.432 W I= = = 0.036A V 12 V (4) The switching load presented by a power MOSFETcan be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide Equation 5 for power. P = C × V2 × f = Qg × V × f (5) Equation 5 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. 9.2.3 Application Curves IN = VDD ENBL = VDD VDD – Input Voltage – V 1 V/div VDD – Input Voltage – V 1 V/div IN = VDD ENBL = VDD VDD VDD OUT 10 nF Between Output and GND 50 μs/div Figure 28. Output Behavior vs VDD (UCC37322) 18 OUT 0V 0V Submit Documentation Feedback 10 nF Between Output and GND 50 μs/div Figure 29. Output Behavior vs VDD (UCC37322) Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 10 Power Supply Recommendations Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the operating frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated using Equation 6. IOUT = Qg × f where • f is frequency (6) For the best high-speed circuit performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI also highly recommends using surface mount components. A 0.1-µF ceramic capacitor must be placed closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 µF) with relatively low ESR should be connected in parallel to help deliver the high current peaks to the load. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels in the driver application. 11 Layout 11.1 Layout Guidelines It can be a significant challenge to avoid the overshoot, undershoot, and ringing issues that can arise from circuit layout. The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances and capacitances in the circuit. Utmost care must be used in the circuit layout. In general, position the driver physically as close to its load as possible. Place a 1-µF bypass capacitor as close to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the two VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package (pins 5 – 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the component layer; route the return current path for the output on the component side, directly over the output path. Extreme conditions may require decoupling the input power and ground connections from the output power and ground connections. The UCCx732x has a feature that allows the user to take these extreme measures, if necessary. There is a small amount of internal impedance of about 15 Ω between the AGND and PGND pins; there is also a small amount of impedance (approximately 30 Ω) between the two VDD pins. To take advantage of this feature, connect a 1-µF bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-µF bypass capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting between the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power only to pin 8. Even more decoupling can be achieved by connecting between AGND and PGND with a pair of antiparallel diodes (anode connected to cathode and cathode connected to anode). Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 19 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 11.2 Layout Example Figure 30. Layout Recommendation 11.3 Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. For a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC3732x family of drivers is available in three different packages to cover a range of application requirements. As shown in the power dissipation rating table, the 8-pin SOIC (D) and 8-pin PDIP (P) packages each have a power rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the table. The power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package. The difficulties with heat removal limit the drive available in the D or P packages. The 8-pin MSOP PowerPAD (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference (3), the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the θjc down to 4.7°C/W. Data is presented in Reference (3) to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference (4) .This allows a significant improvement in heatsinking over that available in theDor P packages, and is shown to more than double the power capability of the D and P packages. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. 20 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated UCC27321, UCC27322 UCC37321, UCC37322 www.ti.com SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Related Products PRODUCT DESCRIPTION PACKAGES UCC37323/4/5 Dual 4-A Low-Side Drivers MSOP–8 PowerPAD, SOIC–8, PDIP–8 UCC27423/4/5 Dual 4-A Low-Side Drivers with Enable MSOP–8 PowerPAD, SOIC–8, PDIP–8 TPS2811/12/13 Dual 2-A Low-Side Drivers with Internal Regulator TSSOP–8, SOIC–8, PDIP–8 TPS2814/15 Dual 2-A Low-Side Drivers with Two Inputs per Channel TSSOP–8, SOIC–8, PDIP–8 TPS2816/17/18/19 Single 2-A Low-Side Driver with Internal Regulator 5-Pin SOT–23 TPS2828/29 Single 2-A Low-Side Driver 5-Pin SOT–23 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: (1) (2) (3) (4) (5) SEM-1400, Topic 2, A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits U-137, Practical Considerations in High PerformanceMOSFET, IGBT andMCTGateDrive Circuits, by Bill Andreycak (SLUA105) Technical Brief, PowerPad Thermally Enhanced Package (SLMA002) Application Brief, PowerPAD Made Easy (SLMA004) Data Book, Power Supply Control Products, (SLUD003) 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY UCC27321 Click here Click here Click here Click here Click here UCC27322 Click here Click here Click here Click here Click here UCC37321 Click here Click here Click here Click here Click here UCC37322 Click here Click here Click here Click here Click here 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 21 UCC27321, UCC27322 UCC37321, UCC37322 SLUS504H – SEPTEMBER 2002 – REVISED JANUARY 2016 www.ti.com 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) UCC27321D ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 105 27321 Samples UCC27321DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 27321 Samples UCC27321DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 27321 Samples UCC27321DR ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 105 27321 Samples UCC27321P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 UCC27321P Samples UCC27321PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 UCC27321P Samples UCC27322D ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 105 27322 Samples UCC27322DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 27322 Samples UCC27322DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 27322 Samples UCC27322DR ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 105 27322 Samples UCC27322DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 27322 Samples UCC27322P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 UCC27322P Samples UCC27322PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 UCC27322P Samples UCC37321D ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 37321 Samples UCC37321DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37321 Samples UCC37321DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37321 Samples UCC37321DR ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 37321 Samples UCC37321P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC37321P Samples UCC37322D ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 37322 Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) UCC37322DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322DR ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 37322 Samples UCC37322P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC37322P Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of