UCC3888N

UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 OFF-LINE POWER SUPPLY CONTROLLER FEATURES • • • • • • • DESCRIPTION Transformerless Off-Line Power Supply Wide 100-VDC to 400-VDC Allowable Input Range Fixed 5-VDC or Adjustable Low-Voltage Output Output Sinks 200 mA, Sources 150 mA Into a MOSFET Gate Uses Low-Cost SMD Inductors Short Circuit Protected Optional Isolation Capability The UCC3888 controller is optimized for use as an off-line, low-power, low-voltage, regulated bias supply. The unique circuit topology utilized in this device can be visualized as two cascaded flyback converters, each operating in the discontinuous mode, both driven from a single external power switch. The significant benefit of this approach is the ability to achieve voltage conversion ratios as high as 400 V to 2.7 V with no transformer and low internal losses. The control algorithm utilized by the UCC3888 sets the switch on time inversely proportional to the input line voltage and sets the switch off time inversely proportional to the output voltage. This action is automatically controlled by an internal feedback loop and reference. The cascaded configuration allows a voltage conversion from 400 V to 2.7 V to be achieved with a switch duty cycle of 7.6%. This topology also offers inherent short circuit protection because as the output voltage falls to zero, the switch-off time approaches infinity. The output voltage is set internally to 5 V. It can be programmed for other output voltages with two external resistors. An isolated version can be achieved with this topology as described further in Unitrode Application Note U-149. TYPICAL APPLICATION 100-400 V 5-V Note: This device incorporates patented technology used under license from Lambda Electronics, Inc. UDG-96013 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2007, Texas Instruments Incorporated UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 THEORY OF OPERATION With reference to the application diagram below, when input voltage is first applied, the current through RON into TON is directed to VCC where it charges the external capacitor, C3, connected to VCC. As voltage builds on VCC, an internal undervoltage lockout holds the circuit off and the output at DRIVE low until VCC reaches 8.4 V. At this time, DRIVE goes high, turning on the power switch, Q1, and redirecting the current into TON to the timing capacitor, CT. CT charges to a fixed threshold with a current ICHG = 0.8 • (VIN – 4.5 V)/RON. Because DRIVE is high only as long as CT charges, the power switch on time will be inversely proportional to line voltage. This provides a constant (line voltage) • (switch on time) product. At the end of the on time, Q1 is turned off, and the current through RON is again diverted to VCC. Thus the current through RON, which charges CT during the on time, contributes to supplying power to the chip during the off time. The power switch off time is controlled by the discharge of CT, which, in turn, is programmed by the regulated output voltage. The relationship between CT discharge current, IDCHG, and output voltage is illustrated as follows: Region 1. When VOUT = 0, the off time is infinite. This feature provides inherent short circuit protection. However, to ensure output voltage startup when the output is not a short, a high-value resistor, RS, is placed in parallel with CT to establish a minimum switching frequency. Region 2. As VOUT rises above approximately 0.7 V to its regulated value, IDCHG is defined by ROFF, and is equal to: IDCHG = (VOUT– 0.7V) / ROFF As VOUT increases, IDCHG increases reducing off time. The operating frequency increases and VOUT rises quickly to its regulated value. Region 3. In this region, a transconductance amplifier reduces IDCHG to maintain a regulated VOUT. Region 4. If VOUT should rise above its regulation range, IDCHG falls to zero and the circuit returns to the minimum frequency established by RS and CT. The range of switching frequencies is established by RON, ROFF, RS, and CT as follows: Frequency = 1/(TON + TOFF) TON = RON• CT• 4.6 V/(VIN – 4.5 V) TOFF (max) = 1.4 • RS• CT Regions 1 and 4 TOFF = ROFF• CT• 3.7 V/(VOUT – 0.7 V) Region 2, excluding the effects of RS, which have a minimal impact on TOFF. The above equations assume that VCC equals 9 V. The voltage at TON increases from approximately 2.5 V to 6.5 V while CT is charging. To take this into account, VIN is adjusted by 4.5 V in the calculation of TON. The voltage at TOFF is approximately 0.7 V. 2 Submit Documentation Feedback UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 DESIGN EXAMPLE The UCC3888 regulates a 5 volt, 1 Watt nonisolated DC output from AC inputs between 80 and 265 volts. In this example, the IC is programmed to deliver a maximum on time gate drive pulse width of 2.2 microseconds which occurs at 80 VAC. The corresponding switching frequency is approximately 100 kHz at low line, and overall efficiency is approximately 50%. Additional design information is available in Unitrode Application Note U-149. 5-V UDG-96014 ABSOLUTE MAXIMUM RATINGS (1) VALUE ICC 8 UNIT mA Current into TON Pin 1.5 Voltage on VOUT Pin 20 V Current into TOFF Pin 250 µA Storage temperature –65 to 150 °C (1) Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. N OR J, D PACKAGE (TOP VIEW) Submit Documentation Feedback 3 UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3888, and –40°C to 85°C for the UCC2888. No load at DRIVE pin (CLOAD = 0). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General VCC Zener voltage ICC < 1.5 mA 9 9.3 V Startup current VOUT = 0 8.6 150 250 µA Operating current I(VCC) VCC = VCC(zener)– 100 mV, F = 150 kHz 1.2 2.5 mA 8 8.4 8.8 6.3 6.6 V V Under-Voltage-Lockout Start threshold VOUT = 0 Minimum operating voltage after start VOUT = 0 6 Hysteresis VOUT = 0 1.8 Amplitude VCC = 9 V 3.5 3.7 3.9 CT to DRIVE high propagation delay Overdrive = 0.2 V 100 200 CT to DRIVE low propagation delay Overdrive = 0.2 V 50 100 I = 20 mA, VCC = 9 V 0.15 0.4 I = 100 mA, VCC = 9 V 0.7 1.8 Oscillator ns Driver VOL VOH I = –20 mA, VCC = 9 V 8.5 8.8 I = –100 mA, VCC = 9 V 6.1 7.8 Rise time CLOAD = 1 nF 35 70 Fall time CLOAD = 1 nF 30 60 0.73 0.79 0.85 60 80 100 V ns Line Voltage Detection Charge coefficient: ICHG/I(TON) VCT = 3 V, DRIVE = High, I(TON) = 1 mA Minimum line voltage for fault RON = 330k Minimum current I(TON) for fault RON = 330k On time during fault CT = 150 pF, VLINE = Min – 1 V Oscillator restart delay after fault V µA 220 2 µs 0.5 ms VOUT Error Amp VOUT regulated 5 V (ADJ open) VCC = 9 V, IDCHG = I(TOFF)/2 4.5 5 5.5 Discharge ratio: IDCHG / I(TOFF) I(TOFF) = 50 µA 0.9 1 1.1 Voltage at TOFF I(TOFF) = 50 µA 0.6 0.95 1.3 Regulation gm (1) (1) Max IDCHG = 50 µA Max IDCHG = 125 µA 2.4 1.9 4.1 7 V mA/V gm is defined as DIDCHG DVOUT for the values of VOUT when VOUT is in regulation. The two points used to calculate gm are for IDCHG at 65% and 35% of its maximum value. 4 Submit Documentation Feedback UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 PIN DESCRIPTIONS ADJ: The ADJ pin is used to provide a 5-V regulated supply without additional external components. Other output voltages can be obtained by connecting a resistor divider between VOUT, ADJ and GND. Use the formula: VOUT = 2.5 V · R1 + R2 R2 where R1 is connected between VOUT and ADJ, and R2 is connected between ADJ and GND. R1 R2 should be less than 1 kΩ to minimize the effect of the temperature coefficient of the internal 30-kΩ resistors, which also connect to VOUT, ADJ, and GND. See Figure 1. CT (timing capacitor): The signal voltage at CT has a peak-to-peak swing of 3.7 V for 9 V VCC. As the voltage at CT crosses the oscillator upper threshold, DRIVE goes low. As the voltage on CT crosses the oscillator lower threshold, DRIVE goes high. DRIVE: This output is a CMOS stage capable of sinking 200 mA peak and sourcing 150 mA peak. The output voltage swing is 0 to VCC. GND (chip ground): All voltages are measured with respect to GND. TOFF (regulated output control): TOFF sets the discharge current of the timing capacitor through an external resistor connected between VOUT and TOFF. TON (line voltage control): TON serves three functions. When CT is discharging (off time), the current through TON is routed to VCC. When CT is charging (on time), the current through TON is split 80% to set the CT charge time and 20% to sense minimum line voltage, which occurs for a TON current of 220 µA. For a minimum line voltage of 80 V, RON is 330 kΩ. The CT voltage slightly affects the value of the charge current during the on time. During this time, the voltage at the TON pin increases from 2.5 V to 6.5 V. VCC (chip supply voltage): The supply voltage of the device at pin VCC is internally clamped at 9 V. The device needs an external supply, from a source such as the rectified ac line or derived from the switching circuit. Precautions must be taken to ensure that total ICC does not exceed 8 mA. VOUT (regulated output): The VOUT pin is directly connected to the power supply output voltage. When VOUT is greater than VCC, VOUT bootstraps VCC. Submit Documentation Feedback 5 UCC2888 UCC3888 www.ti.com SLUS159B – MARCH 1997 – REVISED JUNE 2007 PIN DESCRIPTIONS (continued) 1.8 V Hysteresis UDG-96015 Figure 1. Block Diagram TYPICAL CHARACTERISTICS ICHG vs Line Voltage, RON = 330 k, VCT = 3 V VLINE = 300 V VLINE = 200 V VLINE = 100 V 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC3888N OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 UCC3888NG4 OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 UCC3888N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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