UCD7100PWP

UCD7100 SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 UCD7100 Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense 1 Features 3 Description • • • • • • • • • • • • The UCD7100 device is part of the UCD7K family of digital control compatible drivers for applications that use digital control technology that requires fast local peak current limit protection. Adjustable current limit protection 3.3-V, 10-mA internal regulator DSP/µC compatible inputs Single ±4-A TrueDrive™ high current driver 10-ns typical rise and fall times with 2.2-nF loads 25-ns input-to-output propagation delay 25-ns current sense to output delay Programmable current limit threshold Digital output current limit flag 4.5-V to 15-V supply voltage range Rated from –40°C to 105°C Lead(Pb)-free packaging 2 Applications • • • • Digitally controlled power supplies DC/DC converters Motor controllers Line drivers The UCD7100 is a low-side ±4-A high-current MOSFET gate driver. It allows the digital power controllers such as UCD9110 or UCD9501 to interface to the power stage in single ended topologies. It provides a cycle-by-cycle current limit function with programmable threshold and a digital output current limit flag which can be monitored by the host controller. With a fast 25-ns cycle-by-cycle current limit protection, the driver can turn off the power stage in the unlikely event that the digital system can not respond to a failure situation in time. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCD7100 HTSSOP (14) 5.00 mm x 4.40 mm UCD7100A HTSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VIN VOUT Bias Winding Digital Controller AN1 AGND UCD7100PWP 3 3V3 PWMA 2 IN INT 5 CLF VDD PWMB VDD 14 OUT 12 6 ILIM CS 8 4 AGND Communication 2 AN2 AN3 Isolation Amplifier Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Device Comparison Table...............................................3 7 Pin Configuration and Functions...................................3 8 Specifications.................................................................. 5 8.1 Absolute Maximum Ratings........................................ 5 8.2 Handling Ratings.........................................................5 8.3 Recommended Operating Conditions.........................5 8.4 Thermal Information....................................................6 8.5 Electrical Characteristics.............................................6 8.6 Typical Characteristics................................................ 8 9 Detailed Description...................................................... 11 9.1 Overview................................................................... 11 9.2 Functional Block Diagram......................................... 11 9.3 Feature Description...................................................11 9.4 Device Functional Modes..........................................14 10 Application and Implementation................................ 15 10.1 Application Information........................................... 15 10.2 Typical Application.................................................. 15 11 Power Supply Recommendations..............................17 11.1 Supply..................................................................... 17 11.2 Reference and External Bias Supply...................... 17 12 Layout...........................................................................18 12.1 Layout Guidelines................................................... 18 12.2 Layout Example...................................................... 18 12.3 Thermal Considerations..........................................19 13 Device and Documentation Support..........................20 13.1 Device Support....................................................... 20 13.2 Third-Party Products Disclaimer............................. 20 13.3 Documentation Support.......................................... 20 13.4 Receiving Notification of Documentation Updates..20 13.5 Support Resources................................................. 20 13.6 Trademarks............................................................. 20 13.7 Glossary..................................................................20 13.8 Electrostatic Discharge Caution..............................20 14 Mechanical, Packaging, and Orderable Information.................................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2014) to Revision E (November 2021) Page • Added the UCD7100A device to Device Information .........................................................................................1 • Added the Device Comparison Table................................................................................................................. 3 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 5 Description (continued) For fast switching speeds, the UCD7100 output stage uses the TrueDrive™ output architecture, which delivers rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. It also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller. The UCD7000 driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs. UCD7100 is offered in a PowerPAD™ HTSSOP-14. 6 Device Comparison Table Table 6-1. UCD7100 Device Comparison PART NUMBER COMMENTS UCD7100 Standard manufacturing flow UCD7100A Special manufacturing flow 7 Pin Configuration and Functions VDD IN 3V3 AGND CLF ILIM NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 PVDD PVDD OUT OUT PGND PGND CS NC − No internal connection Figure 7-1. PWP 14 PINS Top View Table 7-1. Pin Functions UCD7100 HTSSOP-14 PIN NO. DFN-14 PIN NO. PIN NAME TYPE FUNCTION 1 1 VDD I Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to 15 V. Bypass the pin with at least 4.7 µF of capacitance. 2 2 IN I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise. 3 3 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22-µF of ceramic capacitance from the pin to ground. 4 4 AGND — Analog ground return. 5 5 CLF O Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising edge on the IN pin. 6 6 ILIM I Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. 7 7 NC — 8 8 CS I 9 9 PGND — No Connection. Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. Power ground return. Connect the two PGNDs together. These ground pins should be connected very closely to the source of the power MOSFET. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 3 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 Table 7-1. Pin Functions (continued) UCD7100 4 HTSSOP-14 PIN NO. DFN-14 PIN NO. PIN NAME TYPE FUNCTION 10 10 PGND — Power ground return. Connect the two PGNDs together. These ground pins should be connected very closely to the source of the power MOSFET. 11 11 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together. 12 12 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together. 13 13 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. Connect the two PVDD pins together. 14 14 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. Connect the two PVDD pins together. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 8 Specifications 8.1 Absolute Maximum Ratings MAX(1) MIN VDD Supply Voltage IDD Supply Current VOUT Output Gate Drive Voltage OUT Output Gate Drive Current OUT IOUT(sink) IOUT(source) 16 Quiescent 20 Switching, TA = 25°C, TJ = 125°C, VDD = 12 V 200 3.6 3.6 Digital I/O’s IN, CLF –0.3 3.6 Power Dissipation TA = 25°C, TJ = 125°C, (PWP-14) Lead Temperature (Soldering, 10 s) (2) 4.0 –0.3 TSOL V A –4.0 –0.3 Junction Operating Temperature mA VDD ILIM TJ (1) –1 V ISET, CS Analog Input UNIT(2) -–55 V 2.67 W 150 °C +300 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. 8.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions Supply Voltage, VDD Supply bypass capacitance MIN TYP MAX UNIT 4.25 12 14.5 V 1 Reference bypass capacitance 0.22 Operating junction temperature -40 µF 105 °C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 5 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 8.4 Thermal Information UCD7100 THERMAL METRIC(1) UNIT HTSSOP 14 PINS RθJA Junction-to-ambient thermal resistance 44.3 RθJC(top) Junction-to-case (top) thermal resistance 35.3 RθJB Junction-to-board thermal resistance 29.6 ψJT Junction-to-top characterization parameter 1.5 ψJB Junction-to-board characterization parameter 29.3 RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7 (1) °C/W For more information about traditional and new thermal metrics, see the application report, IC Package Thermal Metrics Application Report. 8.5 Electrical Characteristics VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = –40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION Supply current, OFF VDD = 4.2 V 200 400 µA Supply current Outputs not switching IN = LOW 1.5 2.5 mA LOW VOLTAGE UNDER-VOLTAGE LOCKOUT VDD UVLO ON 4.25 4.5 4.75 VDD UVLO OFF 4.05 4.25 4.45 VDD UVLO hysteresis 150 250 350 3.267 3.3 3.333 3.234 3.3 3.366 V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25°C 3V3 over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V 1 6.6 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 1 6.6 Short circuit current VDD = 4.75 to 12 V 11 20 35 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 V mV mA V INPUT SIGNAL HIGH, positive-going input threshold voltage (VIT+) 1.65 2.08 LOW negative-going input threshold voltage (VIT-) 1.16 1.5 0.6 0.8 Input voltage hysteresis, (VIT+ – VIT-) Frequency 2 V MHz CURRENT LIMIT (ILIM) ILIM internal current limit threshold ILIM = OPEN 0.466 0.50 0.536 ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 CLF output high level CS > ILIM , ILOAD = -7 mA 2.64 CLF output low level CS ≤ ILIM, ILOAD = 7 mA Propagation delay from IN to CLF IN rising to CLF falling after a current limit event 0.66 10 20 V V mV V ns CURRENT SENSE COMPARATOR 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 8.5 Electrical Characteristics (continued) VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = –40°C to 105°C, (unless otherwise noted). PARAMETER Bias voltage TEST CONDITIONS Includes CS comp offset MIN TYP MAX 5 25 50 Input bias current –1 UNIT mV uA Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV 25 40 Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV 25 50 35 75 ns CURRENT SENSE DISCHARGE TRANSISTOR Discharge resistance IN = low, resistance from CS to AGND 10 Ω OUTPUT DRIVERS Source current(1) VDD = 12 V, IN = high, OUT = 5 V 4 Sink current(1) VDD = 12 V, IN = low, OUT = 5 V 4 VDD = 4.75 V, IN = high, OUT = 0 2 VDD = 4.75 V, IN = low, OUT = 4.75 V 3 Source current(1) Sink current(1) Rise time, tR (1) A CLOAD = 2.2 nF, VDD = 12 V 10 20 Fall time, tF (1) CLOAD = 2.2 nF, VDD = 12 V 10 15 Output with VDD < UVLO VDD = 1.0 V, ISINK = 10 mA 0.8 1.2 V 20 35 ns Propagation delay from IN to OUTx, tD1 CLOAD = 2.2 nF, VDD = 12 V, CLK rising (1) ns Ensured by design. Not 100% tested in production. VIT+ INPUT VIT− tF tF tD1 90% tD2 OUTPUT 10% Figure 8-1. Timing Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 7 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 8.6 Typical Characteristics 5.0 3.36 UVLO on 4.5 3.34 UVLO on 3V3 − Reference Voltage − V VUVLO − UVLO Thresholds − V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 3.32 3.30 3.28 3.26 UVLO on 0.5 0.0 −50 3.24 −25 0 25 50 75 100 125 −50 −25 0 t − Temperature − °C Figure 8-2. UVLO Thresholds vs Temperature 125 2.5 Input Rising 22.5 2.0 VINPUT − Input Voltage − V ISHORT_CKT − Short Circuit Current − mA 100 Figure 8-3. 3V3 Reference Voltage vs Temperature 23.0 22.0 VDD = 4.75 V 21.5 VDD = 12 V 21.0 1.5 Input Falling 1.0 0.5 20.5 20.0 0.0 −50 −25 0 25 50 75 t − Temperature − °C 100 125 Figure 8-4. 3V3 Short Circuit Current vs Temperature −50 −25 0 25 50 75 100 125 TJ − Temperature − °C Figure 8-5. Input Thresholds vs Temperature 65 18.0 16.0 tR = Rise Time 55 CLOAD = 10 nF 14.0 12.0 10.0 tR − Rise Time − ns tR, tF − Rise and Fall Times − ns 25 50 75 t − Temperature − °C tF = Fall Time 8.0 6.0 45 CLOAD = 4.7 nF 35 25 CLOAD = 2.2 nF 4.0 15 2.0 CLOAD = 1 nF 0.0 5 −50 −25 0 25 50 75 100 5 125 10 12.5 15 VDD − Supply Voltage − V TJ − Temperature − °C Figure 8-6. Output Rise Time and Fall Time vs Temperature (VDD = 12 V 8 7.5 Figure 8-7. Rise Time vs Supply Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 20 45 tF − Fall Time − ns 35 tPD − Propagation Delay, Rising − ns 40 CLOAD = 10 nF 30 25 CLOAD = 4.7 nF 20 CLOAD = 2.2 nF 15 CLOAD = 10 nF 15 10 CLOAD = 4.7 nF 5 CLOAD = 2.2 nF CLOAD = 1 nF 10 CLOAD = 1 nF 0 5 5 7.5 10 12.5 5 15 7.5 Figure 8-8. Fall Time vs Supply Voltage 15 Figure 8-9. Propagation Delay Rising vs Supply Voltage 25 0.54 0.53 VCS − Current Limit Threshold − V tPD − Propagation Delay, Falling − ns 12.5 VDD − Supply Voltage − V VDD − Supply Voltage − V CLOAD = 10 nF 20 15 CLOAD = 4.7 nF 10 CLOAD = 2.2 nF 0.52 0.51 0.50 0.49 0.48 0.47 CLOAD = 1 nF 5 0.46 5 7.5 10 12.5 15 −50 −25 VDD − Supply Voltage − V 0 25 50 75 100 125 TJ − Temperature − °C Figure 8-10. Propagation Delay Falling vs Supply Voltage Figure 8-11. Default Current Limit Threshold vs Temperature 40 50 45 35 tPD − CS to CLF Propagation Delay − ns tPD − CS to OUTx Propagation Delay − ns 10 30 25 20 15 10 5 40 35 30 25 20 15 10 5 0 0 −50 −25 0 25 50 75 100 −50 125 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 8-12. CS to OUTx Propagation Delay vs Temperature Figure 8-13. CS to CLF Propagation Delay vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 9 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 35 VDD (2 V/div) tPD − Propagation Delay − ns 30 25 20 15 3V3 (2 V/div) 10 5 OUTx (2 V/div) 0 −50 −25 0 25 50 75 100 t − Time − 40 µs/div 125 TJ − Temperature − °C Figure 8-14. IN to OUT Propagation Delay vs Temperature Figure 8-15. Start-up Behavior at VDD = 12 V (Input Tied to 3V3) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div t − Time − 40 µs/div Figure 8-16. Shut Down Behavior at VDD = 12 V (Input Tied to 3V3) Figure 8-17. Start-up Behavior at VDD = 12 V (Input Shortened to GND) Output Voltage − 2 V/div VDD (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) t − Time − 40 ns/div t − Time − 40 µs/div Figure 8-18. Shut Down Behavior at VDD = 12 V (Input Shortened to GND) 10 Figure 8-19. Output Rise and Fall Time (VDD = 12 V, CLOAD = 10 NF) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 9 Detailed Description 9.1 Overview The UCD7100 is a member of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques, or applications requiring fast local peak current limit protection. The UCD7100 is a low-side ±4-A high-current MOSFET gate driver. The UCD7100 allows digital power controllers such as the UCD9110 or UCD9501 to interface to the power stage in single-ended topologies. It provides a cycle-by-cycle current limit function with programmable threshold and a digital output current limit flag, which can be monitored by the host controller. With a fast 25-ns cycle-by-cycle current limit protection, the driver can turn off the power stage in the unlikely event that the digital system cannot respond to a failure situation in time. 9.2 Functional Block Diagram 14 PVDD VDD 1 13 PVDD 3V3 Regulator & Reference UVLO 11 OUT IN 2 3V3 3 10 PGND AGND 4 25 mV Q SD Q + 9 PGND 8 CS + CLF 5 12 OUT R ILIM 6 N/C 7 9.3 Feature Description 9.3.1 Input The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise. If limiting the rise or fall times to the power device is desired, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the package. 9.3.2 Current Sensing and Protection A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. The current limit threshold is equal to the lesser of the positive inputs at the current limit comparator. The current limit threshold can be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the current limit (ILIM) pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising edge on the IN pin. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 11 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 When the CS voltage is below ILIM, the driver output will follow the PWM input. The CLF digital output flag can be monitored by the host controller to determine when a current limit event occurs and to then apply the appropriate algorithm to obtain the desired current limit profile. One of the main benefits of this local protection feature is that the UCD7K devices can protect the power stage if the software code in the digital controller becomes corrupted and hangs up. If the controller’s PWM output stays high, the local current sense circuit will turn off the driver output when an over-current condition occurs. The system would likely go into a retry mode because; most DSP and microcontrollers have on-board watchdog, brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit comparator provides the required fast protection for the power stage. The CS threshold is 25 mV below the ILIM voltage. This way, if the user attempts to command zero current (ILIM < 25 mV) while the CS pin is at ground, for example at start-up, the CLF flag latches high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin during start-up, then the CLF flag is latched high and the digital controller must poll the UCD7K device, by sending it a narrow IN pulse. If the fault condition is not present the IN pulse resets the CLF signal to low indicating that the UCD7K device is ready to process power pulses. 9.3.3 Handshaking The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the CLF goes low and the device will process input drive signals. The micro-controller should monitor the CLF flag at start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device. 9.3.4 Driver Output The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The driver outputs follows the state of the IN pin provided that the VDD and 3V3 voltages are above their respective under-voltage lockout threshold. The drive output utilizes Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed during the Miller plateau region of the switching transition providing efficiency gains. TrueDrive™ consists of pullup/ pulldown circuits using bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. This hybrid output stage also allows efficient current sourcing at low supply voltages. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. 9.3.5 Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. See Reference [1] 9.3.6 Drive Current and Power Requirements The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 Reference [1] discusses the current required to drive a power MOSFET and other capacitive-input switching devices. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E+1 2 CV2 (1) where C is the load capacitor and V is the bias voltage feeding the driver. There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P+1 2 CV2 f (2) where f is the switching frequency. This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as: P + 10 nF 122 300 kHz + 0.432 W (3) With a 12-V supply, this would equate to a current of: I + P + 0.432 W + 0.036 A V 12 V (4) The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the IDD current that is due to the device internal consumption should be considered. With no load the device current drawn is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10-nF load is close to the value expected. The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge QG, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence QG = CEFF x V to provide the following equation for power: P+C V2 f + QG V f (5) This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 13 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 Note The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. 9.4 Device Functional Modes 9.4.1 Operation with VDD < 4.25 V (minimum VDD) The devices operate with VDD voltages above 4.75 V. The maximum UVLO voltage is 4.75 V, and operates at VDD voltages above 4.75 V. The typical UVLO voltage is 4.5 V. The minimum UVLO voltage is 4.25 V. At VDD below the actual UVLO voltage, the devices do not operate, and OUT remains low. 9.4.2 Operation with IN Pin Open If the IN pin is disconnected (open), a 100 kΩ internal resistor connects IN to GND to prevent unpredictable operation due to a floating IN pin, and OUT remains low. 9.4.3 Operation with ILIM Pin Open If the ILIM pin is disconnected (open), the current limit threshold is set at 0.5 V. 9.4.4 Operation with ILIM Pin High If the signal on ILIM pin is higher than 1 V, the current limit threshold is clamped at 1 V. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information The UCD7100 is part of a family of digital compatible drivers targeting applications utilizing digital control techniques or applications that require local fast peak current limit protection. 10.2 Typical Application VIN VOUT Bias Winding Digital Controller AN1 AGND UCD7100PWP VDD 3 3V3 PWMA 2 IN INT 5 CLF PWMB VDD 14 OUT 12 6 ILIM CS 8 4 AGND Communication 2 AN2 AN3 Isolation Amplifier Figure 10-1. Typical Application 10.2.1 Design Requirements In this design example, the UCD7100 is used to drive a forward converter which is controlled by a digital controller. The switching frequency is 100 KHz, and the input current cycle-by-cycle protection threshold is set at 5 A. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 15 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 10.2.2 Detailed Design Procedure The cycle-by-cycle current protection is implemented by connecting the current sense signal to the CS pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising edge on the IN pin. (6) (7) The current limit threshold can be set to any value between 0.25 V and 1.0 V, so Rsense must be between 0.045 Ω and 0.195 Ω. For example, if Rsense is 0.15 Ω, then VILIM must be 0.775 V to protect input current at 5 A. If the digital controller has an internal digital-to-analog converter, then it can generate 0.775 V and connect to ILIM directly. For a digital controller without an internal digital-to-analog converter, it can generate a PWM signal, send the PWM signal through a low pass filter, then connect to the ILIM pin. Assuming the magnitude of the PWM pulse is 3.3 V, then the duty cycle is: (8) Output Voltage − 2 V/div 10.2.3 Application Curve t − Time − 40 ns/div Figure 10-2. Output Rise and Fall Time (VDD = 12 V, CLOAD = 10 NF) 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 11 Power Supply Recommendations 11.1 Supply The UCD7K devices accept an input range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD supply rail provides power for the output drivers. In all applications the same bus voltage supplies the two pins. It is recommended that a low value of resistance be placed between the two pins so that the local capacitance on each pin forms low pass filters to attenuate any switching noise that may be on the bus. Although quiescent VDD current is low, total supply current will be higher, depending on the gate drive output current required by the switching frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (QG), average OUT current can be calculated from: IOUT = QG x f, where f is frequency. For high-speed circuit performance, a VDD bypass capacitor is recommended to prevent noise problems. A 4.7-µF ceramic capacitor should be located close to the VDD to ground connection. A larger capacitor with relatively low ESR should be connected to the PVDD pin, to help deliver the high current peaks to the load. The capacitors should present a low impedance characteristic for the expected current levels in the driver application. The use of surface mount components for all bypass capacitors is highly recommended. 11.2 Reference and External Bias Supply All devices in the UCD7K family are capable of supplying a regulated 3.3-V rail to power various types of external loads such as a microcontroller or an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. For normal operation, place a minimum of 0.22 µF of ceramic capacitance from the reference pin to ground. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 17 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 12 Layout 12.1 Layout Guidelines In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver device layout has the analog ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections should also be made with a small enclosed loop area to minimize the inductance. 12.2 Layout Example VIN VOUT Bias Supply Bias Winding UCD7100PWP 1 VDD 3 3V3 1 VDS 2 UCD91xx with CLA Peripheral PVDD 14 VDS PVDD 13 IN 2 4 AGND 5 CLF CS OUT 12 OUT 11 6 ILIM FB 7 NC PGND 10 PGND 9 2 CS 8 CS COMMUNICATION (Programming & Status Reporting) 2 Isolation Amplifier Figure 12-1. Isolated Forward Converter 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 ~ VAC − + ~ Bias Supply VOUT UCD7100PWP 1 VDD 3 3V3 Signal Conditioning Amplifier UCD9501 Digital Controller PFC_ISENSE VDS PVDD 14 VDS PVDD 13 2 IN 4 AGND OUT 12 OUT 11 CS 5 CLF FB 6 ILIM PGND 10 PGND 9 7 NC CS 8 CS COMMUNICATION (Programming & Status Reporting) Signal Conditioning Amplifier Figure 12-2. PFC Boost Front-End Power Supply 12.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCD7K family of drivers is available in PowerPAD™ TSSOP package to cover a range of application requirements. Both have the exposed pads to relieve thermal dissipation from the semiconductor junction. As illustrated in Reference [2], the PowerPAD™ packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the ΘJC down to 4.7°C/W. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference [3]. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 19 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 13 Device and Documentation Support 13.1 Device Support 13.1.1 Development Support PRODUCT (1) (2) DESCRIPTION FEATURES UCD7201 Dual Low Side ±4-A Drivers with Common CS 3V3, CS(1) (2) UCD7230 ±4A Synchronous Buck Driver with CS 3V3, CS(1) (2) 3V3 = 3.3V linear regulator. CS = current sense and current limit function. 13.2 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 13.3 Documentation Support 13.3.1 Related Documentation 1. Texas Instruments, Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh 2. Texas Instruments, Technical Brief, PowerPad Thermally Enhanced Package 3. Texas Instruments, Application Brief, PowerPAD Made Easy 13.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.5 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.6 Trademarks TrueDrive™ and PowerPAD™ are trademarks of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 13.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 UCD7100 www.ti.com SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 21 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCD7100APWP ACTIVE HTSSOP PWP 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7100 UCD7100APWPR ACTIVE HTSSOP PWP 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7100 UCD7100PWP ACTIVE HTSSOP PWP 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7100 UCD7100PWPR ACTIVE HTSSOP PWP 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7100 UCD7100PWPRG4 ACTIVE HTSSOP PWP 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7100 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of