UCD7201PWP

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 UCD7201 Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable Common Current Sense 1 Features 3 Description • • • • • The UCD7201 is a member of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. 1 • • • • • • Adjustable Current Limit Protection 3.3-V, 10-mA Internal Regulator DSP/μC Compatible Inputs Dual ±4-A TrueDrive™ High Current Drivers 10-ns Typical Rise and Fall Times with 2.2-nF Loads 20-ns Input-to-Output Propagation Delay 25-ns Current Sense-to-Output Propagation Delay Programmable Current Limit Threshold Digital Output Current Limit Flag 4.5-V to 15-V Supply Voltage Range Rated from -40°C to 105°C The UCD7201 includes dual low-side ±4-A highcurrent MOSFET gate drivers. It allows the digital power controllers such as UCD9110 or UCD9501 to interface to the power stage in double ended topologies. It provides a cycle-by-cycle current limit function for both driver channels, a programmable threshold and a digital output current limit flag which can be monitored by the host controller. With a fast cycle-by-cycle current limit protection, the driver can turn off the power stage in the event of an overcurrent condition. 2 Applications • • • • Device Information(1) PART NUMBER Digitally Controlled Power Supplies DC/DC Converters Motor Controllers Line Drivers UCD7201 PACKAGE HTSSOP (14) BODY SIZE (NOM) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Diagram (Push-Pull Converter) VIN Bias Winding VOUT Bias Supply DIGITAL CONTROLLER UCD7201PWP NC 14 1 NC ADC1 VCC 2 3V3 GND 4 AGND PWMA 3 PWMB VDD 13 PVDD 12 IN1 OUT1 11 5 IN2 OUT2 10 INTERRUPT or CCR 6 CLF PGND 9 PWM or GPIO 7 ILIM CS 8 ADC2 ADC3 ADC4 Isolation Amplifier COMMUNICATION (Programming & Status Reporting) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8.4 Device Functional Modes........................................ 13 9 9.1 Application Information............................................ 14 9.2 Typical Applications ................................................ 14 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Example .................................................... 18 11.3 Thermal Considerations ........................................ 18 12 Device and Documentation Support ................. 19 12.1 12.2 12.3 12.4 12.5 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 Applications and Implementation ...................... 14 Device Support .................................................... Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History DATE March 2005 2 REVISION CHANGE DESCRIPTION SLUS645 Initial release of preliminary datasheet. April 2005 SLUS645A Updated packaging information. July 2005 SLUS645B Initial release of production datasheet. Updated specification and application information. October 2014 SLUS645F Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 5 Description (Continued) For fast switching speeds, the UCD7201 output stages use the TrueDrive™ output architecture, which delivers rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. It also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller. For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input line, the UCD7601 includes a 110-V high-voltage startup circuit. The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs. UCD7201 is offered in a PowerPAD™ HTSSOP-14 package. 6 Pin Configuration and Functions PWP 14 PIN Top View NC 3V3 IN1 AGND IN2 CLF ILIM 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC VDD PVDD OUT1 OUT2 PGND CS NC − No internal connection Pin Functions PIN NO. NAME I/O FUNCTION 1 NC - No Connection 2 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22 μF of ceramic capacitance from this pin to ground. 3 IN1 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise. 4 AGND - Analog ground return. 5 IN2 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise. 6 CLF O Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on the IN pin. 7 ILIM I Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. The default value while open is 0.5 V. 8 CS I Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. 9 PGND - Power ground return. The pin should be connected very closely to the source of the power MOSFET. 10 OUT2 O The high-current TrueDrive™ driver output. 11 OUT1 O The high-current TrueDrive™ driver output. 12 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. 13 VDD I Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15 V. Bypass the pin with at least 4.7 μF of capacitance, returned to AGND. 14 NC - No Connection. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 3 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) MIN VDD MAX UNIT 16 V Supply Voltage Quiescent 20 Switching, TA = 25°C, , TJ = 125°C, VDD = 12 V 200 IDD Supply Current VOUT Output Gate Drive Voltage OUT Output Gate Drive Current OUT –1 PVDD IOUT(sink ) IOUT(sour mA V 4.0 A –4.0 ce) Analog Input TJ (1) (2) ISET, CS –0.3 3.6 ILIM –0.3 3.6 Digital I/O’s IN, CLF –0.3 3.6 Power Dissipation TA = 25°C (PWP-14 package), TJ = 125°C Junction Operating Temperature UCD7201 V 2.67 W 150 °C –55 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Supply Voltage, VDD Supply bypass capacitance MIN TYP MAX UNIT 4.25 12 14.5 V 1 Reference bypass capacitance 0.22 Operating junction temperature –40 μF 105 °C 7.4 Thermal Information UCD7201 THERMAL METRIC (1) PWP UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 50.7 RθJC(top) Junction-to-case (top) thermal resistance 31.8 RθJB Junction-to-board thermal resistance 27.8 ψJT Junction-to-top characterization parameter 1.2 ψJB Junction-to-board characterization parameter 27.6 RθJC(bot) Junction-to-case (bottom) thermal resistance 4.1 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 7.5 Electrical Characteristics VDD = 12 V, 4.7-μF capacitor from VDD to GND, 0.22μF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION Supply current, OFF VDD = 4.2 V - 200 400 μA Supply current Outputs not switching IN = LOW - 1.5 2.5 mA VDD UVLO ON 4.25 4.5 4.75 VDD UVLO OFF 4.05 4.25 4.45 VDD UVLO hysteresis 150 250 350 3.267 3.3 3.333 3.234 3.3 3.366 LOW VOLTAGE UNDERVOLTAGE LOCKOUT V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25°C, ILOAD = 0 3V3 set point over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V - 1 6.6 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA - 1 6.6 Short circuit current VDD = 4.75 to 12 V 11 20 35 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 HIGH, positive-going input threshold voltage (VIT+) 1.65 - 2.08 LOW negative-going input threshold voltage (VIT-) 1.16 - 1.5 0.6 - 0.8 - - 2 V mV mA V INPUT SIGNAL Input voltage hysteresis, (VIT+ - VIT-) Frequency V MHz CURRENT LIMIT (ILIM) ILIM internal current limit threshold ILIM = OPEN 0.51 0.55 0.58 ILIM maximum current limit threshold ILIM = 3.3 V 1.05 1.10 1.15 ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 CLF output high level CS > ILIM , ILOAD = -7 mA 2.64 - - CLF output low level CS ≤ ILIM, ILOAD = 7 mA - - 0.66 Propagation delay from IN to CLF IN rising to CLF falling after a current limit event - 10 20 ns Includes CS comp offset 5 25 50 mV μA V CURRENT SENSE COMPARATOR Bias voltage Input bias current - –1 - Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40 Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50 10 35 75 ns CURRENT SENSE DISCHARGE TRANSISTOR Discharge resistance IN = low, resistance from CS to AGND Ω OUTPUT DRIVERS Source current VDD = 12 V, IN = high, OUTx = 5 V 4 Sink current VDD = 12 V, IN = low, OUTx = 5 V 4 Source current VDD = 4.75 V, IN = high, OUTx = 0 2 Sink current VDD = 4.75 V, IN = low, OUTx = 4.75 V Rise time, tR CLOAD= 2.2 nF, VDD = 12 V 10 20 Fall time, tF CLOAD = 2.2 nF, VDD = 12 V 10 15 Output with VDD < UVLO VDD =1.0 V, ISINK = 10 mA 0.8 1.2 A 3 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 ns V 5 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) VDD = 12 V, 4.7-μF capacitor from VDD to GND, 0.22μF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise noted). TYP MAX Propagation delay from IN to OUT1, tD1 PARAMETER CLOAD = 2.2 nF, VDD = 12 V, CLK rising TEST CONDITIONS MIN 20 35 Propagation delay from IN to OUT2, tD2 CLOAD = 2.2 nF, VDD = 12 V, CLK falling 20 35 UNIT ns VIT+ INPUT VIT− tF tF tD1 90% tD2 OUTPUT 10% Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 7.6 Typical Characteristics 3.36 5.0 UVLO on 4.5 3.34 UVLO off 3V3 − Reference Voltage − V VUVLO − UVLO Thresholds − V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 3.32 3.30 3.28 3.26 UVLO hysteresis 0.5 0.0 −50 3.24 −25 0 25 50 75 100 125 −50 t − Temperature − °C 25 50 75 t − Temperature − °C 100 125 160 140 22.5 IDD − Supply Current − mA ISHORT_CKT − Short Circuit Current − mA 0 Figure 3. 3V3 Reference Voltage vs Temperature Figure 2. UVLO Thresholds vs Temperature 23.0 22.0 VDD = 4.75 V 21.5 VDD = 12 V 21.0 CLOAD = 10 nF 120 100 80 CLOAD = 4.7 nF 60 40 CLOAD = 2.2 nF 20.5 20 20.0 CLOAD = 1 nF 0 −50 −25 0 25 50 75 t − Temperature − °C 100 125 0 1000 1500 Figure 5. Supply Current vs Frequency (VDD = 5 V) 280 320 240 280 IDD − Supply Current − mA CLOAD = 10 nF 200 160 CLOAD = 4.7 nF 120 80 500 f − Frequency − kHz Figure 4. 3V3 Short Circuit Current vs Temperature IDD − Supply Current − mA −25 CLOAD = 2.2 nF 240 CLOAD = 10 nF 200 160 CLOAD = 4.7 nF 120 80 40 CLOAD = 2.2 nF 40 CLOAD = 1 nF 0 0 500 1000 CLOAD = 1 nF 0 0 1500 500 1000 1500 f − Frequency − kHz f − Frequency − kHz Figure 6. Supply Current vs Frequency (VDD = 8 V) Figure 7. Supply Current vs Frequency (VDD = 10 V) Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 7 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 500 400 450 350 IDD − Supply Current − mA IDD − Supply Current − mA 400 300 CLOAD = 10 nF 250 200 CLOAD = 4.7 nF 150 100 CLOAD = 10 nF 350 300 CLOAD = 4.7 nF 250 200 150 CLOAD = 2.2 nF CLOAD = 2.2 nF 100 50 50 CLOAD = 1 nF CLOAD = 1 nF 0 0 500 0 0 1500 1000 1500 1000 500 f − Frequency − kHz f − Frequency − kHz Figure 8. Supply Current vs Frequency (VDD = 12V) Figure 9. Supply Current vs Frequency (VDD = 15 V) 2.5 18.0 CLOAD = 2.2 nF 16.0 tR, tF − Rise and Fall Times − ns Input Rising VINPUT − Input Voltage − V 2.0 1.5 Input Falling 1.0 tR = Rise Time 14.0 12.0 10.0 tF = Fall Time 8.0 6.0 4.0 0.5 2.0 0.0 0.0 −50 −25 0 25 50 75 100 −50 125 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 10. Input Thresholds vs Temperature Figure 11. Output Rise Time and Fall Time vs Temperature (VDD = 12 V) 65 45 40 55 35 45 tF − Fall Time − ns tR − Rise Time − ns CLOAD = 10 nF CLOAD = 4.7 nF 35 25 CLOAD = 10 nF 30 25 CLOAD = 4.7 nF 20 CLOAD = 2.2 nF CLOAD = 2.2 nF 15 15 CLOAD = 1 nF 10 CLOAD = 1 nF 5 5 5 8 7.5 10 12.5 15 5 7.5 10 12.5 15 VDD − Supply Voltage − V VDD − Supply Voltage − V Figure 12. Rise Time vs Supply Voltage Figure 13. Fall Time vs Supply Voltage Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 Typical Characteristics (continued) 25 tPD − Propagation Delay, Falling − ns tPD − Propagation Delay, Rising − ns 20 CLOAD = 10 nF 15 10 CLOAD = 4.7 nF 5 CLOAD = 2.2 nF CLOAD = 10 nF 20 15 CLOAD = 4.7 nF 10 CLOAD = 2.2 nF CLOAD = 1 nF CLOAD = 1 nF 5 0 5 7.5 10 12.5 15 5 7.5 10 12.5 15 VDD − Supply Voltage − V Figure 14. IN to OUTx Propagation Delay Rising vs Supply Voltage Figure 15. IN to OUTx Propagation Delay Falling vs Supply Voltage 0.59 40 0.58 35 tPD − CS to OUTx Propagation Delay − ns VCS − Current Limit Threshold − V VDD − Supply Voltage − V 0.57 0.56 0.55 0.54 0.53 0.52 30 25 20 15 10 5 0 0.51 −50 −25 0 25 50 75 100 125 −50 −25 0 TJ − Temperature − °C 25 50 75 100 125 TJ − Temperature − °C Figure 16. Default Current Limit Threshold vs Temperature Figure 17. CS to OUTx Propagation Delay vs Temperature 35 50 30 40 tPD − Propagation Delay − ns tPD − CS to CLF Propagation Delay − ns 45 35 30 25 20 15 10 25 20 15 10 5 5 0 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 18. CS to CLF Propagation Delay vs Temperature Figure 19. IN to OUT Propagation Delay vs Temperature Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 9 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div t − Time − 40 µs/div Figure 20. Start-Up Behavior at VDD = 12 V (Input Tied to 3V3) Figure 21. Shut Down Behavior at VDD = 12 V (Input Tied to 3V3) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div t − Time − 40 µs/div Figure 23. Shut Down Behavior at VDD = 12 V (Input Shortened to GND) Output Voltage − 2 V/div Figure 22. Start-Up Behavior at VDD = 12 V (Input Shortened to GND) t − Time − 40 ns/div Figure 24. Output Rise and Fall Time (VDD = 12 V, CLOAD = 10 nF) 10 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 8 Detailed Description 8.1 Overview The UCD7201 is a member of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. The UCD7201 is a low-side ±4-A high-current MOSFET gate driver. It allows the digital power controllers such as UCD9110 or UCD9501 to interface to the power stage in double ended topologies. It provides a cycle-by-cycle current limit function for both driver channels, a programmable threshold and a digital output current limit flag which can be monitored by the host controller. With a fast cycle-by-cycle current limit protection, the driver can turn off the power stage in the event of an overcurrent condition. 8.2 Functional Block Diagram NC 1 3V3 2 IN1 3 AGND 4 IN2 5 CLF 6 3V3 Regulator UVLO NC 13 VDD 12 PVDD 11 OUT1 10 OUT2 9 PGND 8 CS + and Reference 14 + Q SD 25 mV R Q ILIM R 7 8.3 Feature Description 8.3.1 Reference / External Bias Supply All devices in the UCD7K family are capable of supplying a regulated 3.3-V rail to power various types of external loads such as a microcontroller or an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. For normal operation, place 0.22-μF of ceramic capacitance between the 3V3 pin to the AGND pin. 8.3.2 Input Pin The input pins are high impedance digital inputs capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise. If limiting the rise or fall times to the power device is desired then an external resistance may be added between the output of the driver and the load device, which is generally the gate of a power MOSFET. 8.3.3 Current Sensing and Protection A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 11 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) The current limit threshold may be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the current limit (ILIM) pin. If the ILIM pin is left floating, the internal current limit threshold will be 0.5 volts. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on either of the IN pins. When the CS voltage is below ILIM, the driver output follows the PWM input. The CLF digital output flag can be monitored by the host controller to determine when a current limit event occurs and to then apply the appropriate algorithm to obtain the desired current limit profile (i.e. straight time, fold back, hickup or latch-off). A benefit of this local protection feature is that the UCD7K devices can protect the power stage if the software code in the digital controller becomes corrupted. If the controller’s PWM output stays high, the local current sense circuit turns off the driver output when an over-current event occurs. The system would then likely go into retry mode because most DSP and microcontrollers have on-board watchdog, brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit comparator provides the required fast protection for the power stage. The CS threshold is 25 mV below the ILIM voltage. If the user attempts to command zero current while the CS pin is at ground the CLF flag will latch high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin will always be greater than the CS pin for the handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin during start-up, then the CLF flag will be latched high and the digital controller must poll the UCD7K device, by sending it a narrow IN pulse. If a fault condition is not present the IN pulse will reset the CLF signal to low indicating that the UCD7K device is ready to process power pulses. 8.3.4 Handshaking The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the CLF goes low and the device will process input drive signals. The micro-controller should monitor the CFL flag at start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device. 8.3.5 Driver Output The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and swings to both PVDD and PGND. The driver outputs follow the state of the IN pin provided that the VDD and 3V3 voltages are above their respective under-voltage lockout threshold. The drive output utilizes Texas Instruments' TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition providing efficiency gains. TrueDrive™ consists of pullup pulldown circuits with bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. This hybrid output stage also allows efficient current sourcing at low supply voltages. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. 8.3.6 Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. See Reference [1] 12 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 Feature Description (continued) 8.3.7 Drive Current and Power Requirements The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. Reference [1] discusses the current required to drive a power MOSFET and other capacitive-input switching devices. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: 1 E = ´ CV 2 (1) 2 where C is the load capacitor and V is the bias voltage feeding the driver. There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P = CV 2 ´ f (2) where f is the switching frequency. This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. With VDD = 12 V, CLOAD = 2.2 nF, and f = 300 kHz, the power loss can be calculated as: P = 2.2nF ´ 122 ´ 300kHz = 0.095W (3) With a 12-V supply, this would equate to a current of: P 0.095W I= = = 7.9mA V 12V (4) 8.3.8 Operational Waveforms Figure 22 shows the circuit performance achievable with the output driving a 10-nF load at 12-V VDD. The input pulsewidth (not shown) is set to 200 ns to show both transitions in the output waveform. Note the linear rising and falling edges of the switching waveforms. This is due to the constant output current characteristic of TrueDrive™ stage as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. 8.4 Device Functional Modes 8.4.1 Operation with VDD < 4.25 V (Minimum VDD) The devices operate with VDD voltages above 4.75 V. The maximum UVLO voltage is 4.75 V and operates at VDD voltages above 4.75 V. The typical UVLO voltage is 4.5 V. The minimum UVLO voltage is 4.25 V. At VDD below the actual UVLO voltage, the devices do not operate, OUT1 and OUT2 remain low. 8.4.2 Operation with IN Pin Open If the IN1 or IN2 pin is disconnected (open), a 100 kΩ internal resistor connects IN1 or IN2 to GND to prevent unpredictable operation due to a floating IN1 or IN2 pin, OUT1 or OUT2 remains low. 8.4.3 Operation with ILIM Pin Open If the ILIM pin is disconnected (open), the current limit threshold is set at 0.55 V. 8.4.4 Operation with ILIM Pin High If the signal on ILIM pin is higher than 1.1 V, the current limit threshold is clamped at 1.1 V. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 13 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The UCD7201 is member of the UCD7K family of digital compatible drivers targeting applications utilizing digital control techniques or applications that require local fast peak current limit protection. 9.2 Typical Applications 9.2.1 Half-Bridge Converter Figure 25 shows the UCD7201 in a half-bridge converter design. The digital controller is performing the output voltage compensation and all supervisory functions. The isolation amplifier is made up of a linear opto-coupler configured for a gain of 1/10, so the output voltage is transformed to a level comparable with the ADC of the digital controller. VOUT VIN Bias Winding CS XFMR Bias Supply DIGITAL CONTROLLER ADC1 UCD7201PWP NC 14 1 NC VCC 2 3V3 GND 4 AGND PVDD 12 VDD 13 PWMA 3 IN1 OUT1 11 PWMB 5 IN2 OUT2 10 6 CLF PGND 9 7 ILIM CS 8 ADC2 INTERRUPT or CCR PWM or GPIO Gate Drive Transformer (3 winding) ADC3 ADC4 Isolation Amplifier COMMUNICATION (Programming & Status Reporting) Figure 25. Half-Bridge Converter 9.2.1.1 Design Requirements In this design example, the input current is sensed by a current transformer (CT), the cycle-by-cycle protection threshold is set at 5 A. 9.2.1.2 Detailed Design Procedure The cycle-by-cycle current protection is implemented by connect the current sense signal to CS pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising edge on the IN pin. 14 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 Typical Applications (continued) The current limit threshold can be set to any value between 0.25 V and 1.0 V, select the right turns ratio of the CT and right resistor at the output of CT, such that the CT output is within this range. Assuming the CT output is 0.775V when input current is 5A, if the digital controller has internal digital-to-analog converter, then it can generate 0.775 V and connect to ILIM directly. For digital controller without internal digital-to-analog converter, it can generate PWM signal, send PWM signal through a low pass filter, then connect to ILIM pin. Assuming the magnitude of the PWM pulse is 3.3V, then the duty cycle is: 0.775 D= 3.3 (5) Output Voltage − 2 V/div 9.2.1.3 Application Curves t − Time − 40 ns/div Figure 26. Output Rise and Fall Time (VDD = 12 V, CLOAD = 10 nF) 9.2.2 Intermediate Bus Converter Figure 27 shows the UCD7201 in an analog only implementation of an intermediate bus converter. The ILIM pin of the UCD7201 is exponentially increased at start-up, which minimizes overshoot on the output voltage. The UCC28089 is a push-pull controller with fixed dead-time. The UCC28089 operates at a fixed duty cycle close to 100% so the circuit acts like a DC transformer linearly transforming the input voltage via the turns ratio of the transformer. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 15 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) VIN Bias Supply Bias Winding VOUT UCC28089 1 NC VDD 16 1 SYNC UCD7201 NC 14 2 3V3 2 DIS GND 13 3 CT 4 CS 4 AGND PVDD 12 VDD 13 OUTA 15 3 IN1 OUT1 11 OUTB 14 5 IN2 OUT2 10 6 CLF PGND 9 7 ILIM CS 8 Figure 27. Intermediate Bus Converter 9.2.2.1 Design Requirements In this design example, the input current is sensed by a current shunt, the cycle-by-cycle protection threshold is set at 5 A. 9.2.2.2 Detailed Design Procedure Ipeak × Rsense = VILIM – 0.025 (6) VILIM - 0.025 Rsense = Ipeak (7) The current limit threshold can be set to any value between 0.25 V and 1.0 V, so Rsense need to be between 0.045 Ω and 0.195 Ω. Let’s choose Rsense as 0.15 Ω. VILIM need to be 0.775 V in order to protect input current at 5 A. Since the controller is analog, it cannot program the VILIM, however, VILIM can be implemented by a voltage divider connect the pin 2 of UCD7201. Since the voltage on pin 2 is 3.3 V, so the voltage divider needs to be: Rbottom ´ 3.3 = 0.775 Rbottom + Rtop (8) 9.2.3 Application Curves See Figure 26. 16 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 10 Power Supply Recommendations The UCD7K devices accept a supply range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD supply rail provides power for the output drivers. In all applications the same bus voltage supplies the two pins. It is recommended that a low value of resistance be placed between the two pins so that the local capacitance on each pin forms low pass filters to attenuate any switching noise that may be on the bus. Although quiescent VDD current is low, total supply current depends on the gate drive output current required for capacitive load and switching frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (QG), average OUT current can be calculated from: IOUT = QG x f, where f is frequency. For the best high-speed circuit performance, VDD bypass capacitors are recommended to prevent noise problems. A 4.7-μF ceramic capacitor should be located closest to the VDD and the AGND connection. In addition, a larger capacitor with relatively low ESR should be connected to the PVDD and PGND pin, to help deliver the high current peaks to the load. The capacitors should present a low impedance characteristic for the expected current levels in the driver application. The use of surface mount components for all bypass capacitors is highly recommended. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 17 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com 11 Layout 11.1 Layout Guidelines In a power driver operating at high frequency, it is critical to minimize stray inductance to minimize overshoot/undershoots and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. It is advantageous to connect the driver device close to the MOSFETs. It is recommended that the PGND and the AGND pins be connected to the PowerPad™ of the package with a thin trace. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3 V. The use of schottky diodes on the outputs to PGND and PVDD is recommended when driving gate transformers. 11.2 Layout Example Figure 28. UCD7100 Layout Example 11.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCD7K family of drivers is available in PowerPAD™ TSSOP and QFN/DFN packages to cover a range of application requirements. Both have an exposed pad to enhance thermal conductivity from the semiconductor junction. As illustrated in Reference [2], the PowerPAD™ packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the TJC down to 2.07°C/W. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference [3]. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The PowerPad™ should be connected to the quiet ground of the circuit. 18 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 UCD7201 www.ti.com SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support TEMPERATURE RANGE UCD7100 FEATURES 3V3, CS (1) Single Low Side ±4-A Driver with Independent CS Dual Low Side ±4-A Drivers with Independent CS 3V3, CS UCD7230 ±4-A Synchronous Buck Driver with CS 3V3, CS (1) UCD7500 Single Low Side ±4-A Driver with CS and 110-V High Voltage Startup UCD7601 3v3, CS, HVS110 Dual Low Side ±4-A Drivers with Independent CS and 110-V High Voltage Startup Dual Low Side ±4-A Drivers with Common CS and 110-V High Voltage Startup UCD9110 Digital Power Controller for High Performance Single-loop Applications UCD9501 Digital Power Controller for High Performance Multi-Loop Applications (2) (1) (2) UCD7200 UCD7600 (1) (2) (3) (4) CURRENT SENSE LIMIT PER CHANNEL (2) (1) (2) (3) 3V3, CS, HVS110 (1) (2) (3) 3V3, CCS, HVS110 (1) (4) (3) 3V3 = 3.3-V linear regulator. CS = current sense and current limit function. HVS110 = 110-V high voltage startup circuit. CCS = Common current sense and current limit function. 12.2 Documentation Support 12.2.1 Related Documentation 1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, SLUP133. 2. Technical Brief, PowerPad Thermally Enhanced Package, SLMA002 3. Application Brief, PowerPAD Made Easy, SLMA004 12.3 Trademarks TrueDrive, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 19 UCD7201 SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: UCD7201 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCD7201PWP ACTIVE HTSSOP PWP 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7201 UCD7201PWPG4 ACTIVE HTSSOP PWP 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7201 UCD7201PWPR ACTIVE HTSSOP PWP 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCD7201 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of