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UCD7138
SLVSCS1B – MARCH 2015 – REVISED MAY 2015
UCD7138 4-A and 6-A Single-Channel Synchronous-Rectifier Driver With Body-Diode
Conduction Sensing and Reporting
1 Features
3 Description
•
The UCD7138 device is a 4-A and 6-A single-channel
MOSFET driver with body-diode conduction sensing
and reporting and is a high performance driver that
allows the Texas Instruments UCD3138A digital
PWM controller to achieve advanced synchronousrectification (SR) control. The device contains a highspeed gate driver, a body-diode conduction-sensing
circuit, and a turnon delay optimization circuit. The
device is suitable for high-power, high-efficiency
isolated converter applications where SR dead-time
optimization is desired.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Side Gate Driver With Body-Diode
Conduction Sensing
Gate Turnoff Edge Body-Diode Conduction
Reporting
Gate Turnon Edge Delay Optimization
Works Together With the Dead-Time
Compensation (DTC) Module in the UCD3138A
Family of Digital Power Controllers:
– Automatic or Manual Dead-Time Adjustment of
Gate Turnon and Turnoff Edges
– Negative Current Protection
-150-mV Body-Diode Conduction Sensing
Threshold
Able to Sense Body Diode Conduction Times as
Low as 10 ns
4-A Peak-Source and 6-A Peak-Sink Drive
Current
Fast Propagation Delays (14-ns Typical)
Fast Rise and Fall Times (5-ns Typical)
Up to 2-MHz Operating Frequency
4.5-V to 18-V Supply Range
Rail-to-Rail Drive Capability
VCC Undervoltage Lockout (UVLO)
6-Pin 3-mm × 3-mm WSON-6 Package
The UCD7138 device offers asymmetrical rail-to-rail
4-A source and 6-A sink peak-current drive capability.
The short propagation delay and fast rise and fall
time allows efficient operation at high frequencies. An
internal high-speed comparator with a –150-mV
threshold detects the body-diode conduction and
reports the information to the UCD3138A digitalpower controller. The UCD7138 device is capable of
sensing body-diode conduction time as low as 10 ns.
The SR turnon edge is optimized by the UCD7138
device. The SR turnoff edge is optimized by the
UCD3138A digital-power controller which analyzes
the body-diode conduction information reported by
the UCD7138 DTC pin.
The benefits of the chipset include maximizing
system efficiency by minimizing body-diode
conduction time, robust and fast negative-current
protection, and a simple interface.
2 Applications
•
•
•
Device Information(1)
LLC Converters
Hard Switching Full-Bridge Converters
Digital Power-Control Applications
PART NUMBER
PACKAGE
UCD7138
WSON (6)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
VCC
VSOURCE
4.5 to 18 V
Power Savings for a 340-W LLC Application
PGND
UCD3138A
95
3
DTC
Module
1
2
IN
DTC
VCC
94
VD
5
OUT
4
D
UCD7138
G
DGND
6
CTRL
Thermal Pad
(GND)
S
Efficiency (%)
DPWM
93
Without UCD7138 +
UCD3138A SR
Optimization
With UCD7138 +
UCD3138A SR
Optimization
92
91
PGND
90
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
Load Current (A)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD7138
SLVSCS1B – MARCH 2015 – REVISED MAY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
5 Revision History
Changes from Revision A (April 2015) to Revision B
•
2
Page
Changed the device status from Product Preview to Production Data ................................................................................. 1
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SLVSCS1B – MARCH 2015 – REVISED MAY 2015
6 Pin Configuration and Functions
DRS Package
6-Pin WSON With Exposed Thermal Pad
Top View
IN
1
DTC
2
VCC
3
Thermal
Pad
(GND)
6
CTRL
5
VD
4
OUT
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
IN
I
Input: Gate driver input. This pin should be connected directly to the DPWM output of the
digital controller.
2
DTC
O
Body-diode conduction-time report: Standard digital IO. Pulled high internally. Output low
when the body diode is conducting. This pin should be connected to the DTC0 or DTC1 pin
on UCD3138A.
3
VCC
P
IC supply: External bias supply input. The supply range is 4.5-V to 18-V. A ceramic bypass
capacitor of at least 1 µF should be placed as close as possible to the VCC pin and the
thermal pad. Where possible, use thick & wide Cu connections.
4
OUT
O
Gate driver output: Integrated push-pull gate driver for one or more external power
MOSFETs. Typical 4-A source and 6-A sink capability. This is a rail-to-rail output, with the
rails defined by the voltages on VCC and GND. This pin should be connected to the gate
terminal of the synchronous rectification MOSFET.
5
VD
I
Drain voltage: Connect this pin as close as possible to the controlled-MOSFET drain pad.
This pin is internally connected to the diode conduction detection comparator. The
comparator has a –0.15-V threshold to detect body-diode conduction. A 20-Ω resistor should
be connected between the VD pin and MOSFET drain terminal to limit the current. The
maximum voltage of the VD pin should not exceed 45 V. A simple external circuit can enable
the usage of much higher voltages, see Figure 34.
6
CTRL
I
Rising edge optimization control: Connect this pin to ground to disable rising edge
optimization. Leave this pin floating or connect it to logic high to enable rising edge
optimization.
—
Thermal Pad
(GND)
—
Exposed thermal pad: The exposed pad on the bottom of the package enhances the
thermal performance of the device. This pad is the device ground reference.
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SLVSCS1B – MARCH 2015 – REVISED MAY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
VCC
–0.3
20
IN, CRTL
–0.3
3.8
–1
45
VD
Maximum VCC continuous input current
DC current
V
50
Output current, peak (pulse)
Switching frequency, ƒS
Operating junction temperature, TJ
–40
Lead temperature, soldering, 10 s, T(SOL)
Storage temperature, Tstg
(1)
UNIT
–65
mA
6
A
2000
kHz
125
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS–001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
VCC input voltage from a low impedance source
4.5
18
VIN
Input voltage
0
3.6
C(BP)
VCC bypass capacitor
1
TJ
Operating junction temperature
UNIT
V
V
µF
–40
125
°C
7.4 Thermal Information
UCD7138
THERMAL METRIC (1)
DRS (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
73.4
RθJC(top)
Junction-to-case (top) thermal resistance
84.2
RθJB
Junction-to-board thermal resistance
46.3
ψJT
Junction-to-top characterization parameter
2.6
ψJB
Junction-to-board characterization parameter
46.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
12.4
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLVSCS1B – MARCH 2015 – REVISED MAY 2015
7.5 Electrical Characteristics
At VCC = 12 VDC, –40°C < TJ = TA < 125°C, 1µF capacitor from VCC to GND, all voltages are with respect to ground and
currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC BIAS SUPPLY
ICC(UV)
VCC current, undervoltage
VCC = 3.4 V
122
186
µA
ICC(ON)
VCC current, no switching
VCC = 12 V
0.85
1.1
mA
13
17
mA
ICC(OPERATE)
VCC current, normal operation
(1)
VCC = 12 V, C(LOAD) = 10 nF,
ƒ = 100 kHz
GATE INPUT (IN)
VIH
Input signal high threshold
1.93
2.03
2.10
V
VIL
Input signal low threshold
0.98
1.03
1.08
V
VI(hys)
Input hysteresis
0.90
1.00
V
DTC OUTPUT
VOL(DTC)
Low level output voltage
0.25
VOH(DTC)
High level output voltage
IOH(DTC)
Output sinking current
IOL(DTC)
Output sourcing current
VDTC
Maximum DTC pin output voltage
2.5
V
V
4
–4
mA
mA
3.5
3.6
V
3.30
3.80
4.30
V
3.10
3.56
4.02
V
UNDERVOLTAGE LOCKOUT SECTION (UVLO)
VCC(ON)
VCC turnon threshold
VCC(OFF)
VCC turnoff threshold
VCC(hys)
UVLO hysteresis
VCC(hys) = VCC(ON) – VCC(OFF)
0.24
V
COMPARATOR
VTH
Body diode conduction sensing
threshold
CI(VD–ground)
Differential input capacitance
between VD and ground (1)
VD = –150 mV
VCC-VOH
Output high voltage
IOUT = –10 mA
0.038
0.064
V
VOL
Output low voltage
IOUT = 10 mA
0.0025
0.009
V
TA = 25°C, IOUT = –25 mA to
–50 mA
5
6.1
Ω
TA = –40°C to 125°C,
IOUT = –50 mA
5
6.3
Ω
TA = 25°C, IOUT = 25 mA to
50 mA
0.31
0.44
Ω
TA = –40°C to 125°C,
IOUT = 50 mA
0.33
0.45
Ω
–179
–147
–113
20
mV
pF
GATE DRIVER
R(UP)
R(DOWN)
Pullup resistance
Pulldown resistance
IO(source)
Output peak current (source)
IO(sink)
Output peak current (sink)
(1)
(1)
(1)
C(LOAD) = 0.22 µF, ƒS = 1 kHz,
5-V output
–4
A
C(LOAD) = 0.22 µF, ƒS = 1 kHz,
5-V output
6
A
Ensured by Design, not tested in Production.
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7.6 Switching Characteristics
At VCC = 12 VDC, –40°C < TJ = TA < 125°C, 1µF capacitor from VCC to GND, all voltages are with respect to ground and
currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
tr
Rise time
tf
Fall time
Minimum IN duration (width) that changes OUT
state
tw(IN)
td(1)
Gate driver turn on propagation delay
td(2)
Gate driver turn off propagation delay
td(COMP)
td(DTC)
MIN
Body-diode conduction detection-comparator
controlled-turnon propagation delay (1)
DTC output propagation delay
TYP MAX
UNIT
5
8
ns
C(LOAD) =1 nF, VCC = 12 V,
See Figure 1 and Figure 24
4
8
ns
C(LOAD)=1 nF, VCC = 5 V,
See Figure 1 and Figure 24
3.36
5
ns
C(LOAD)=1 nF, VCC = 12 V,
See Figure 1 and Figure 24
3.5
5
ns
10
23
ns
10
23
ns
VCC = 5 V
11
13
ns
VCC = 12 V
11
13
ns
C(LOAD) = 1 nF, VIN = 0 V to 3.3 V, VCC = 5 V,
VVD = –0.5 V, See Figure 1 and Figure 24
14
26.6
ns
C(LOAD) = 1 nF, VIN = 0 V to 3.3 V, VCC = 12
V,
VVD = –0.5 V, See Figure 1 and Figure 24
14
25
ns
C(LOAD) = 1 nF, VIN = 3.3 V to 0 V, VCC = 5 V,
See Figure 1 and Figure 24
14
22.9
ns
C(LOAD) = 1 nF, VIN = 3.3 V to 0 V, VCC = 12
V,
See Figure 1 and Figure 24
14
22
ns
C(LOAD) = 1 nF, VIN = 3.3 V, VCC = 5 V, VVD =
2 V to –0.5 V, See Figure 24
28
36
ns
C(LOAD) = 1 nF, VIN = 3.3 V, VCC = 12 V, VVD
= 2 V to –0.5 V, See Figure 24
26
33
ns
VCC = 5 V
21
27
ns
VCC = 12 V
18
25
ns
Minimum VD pulse duration (width) that changes VCC = 5 V
the DTC output state
VCC = 12 V
tw(VD)
(1)
TEST CONDITIONS
C(LOAD) =1 nF, VCC = 5 V,
See Figure 1 and Figure 24
For details about the operation, see the Gate Turnon and Turnoff section.
High
90%
IN
10%
Low
High
90%
OUT
10%
Low
td(1) tr
td(2) tf
Figure 1. Input Driver Operation
6
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7.7 Typical Characteristics
170
950
900
150
Standby Current (PA)
Start-up Current (PA)
850
130
110
90
800
750
700
650
600
70
VCC = 5 V
VCC = 12 V
550
50
-50
0
50
Temperature (qC)
100
500
-50
150
VCC = 3.4 V
13
12.5
12
11.5
11
10.5
0
VCC = 12 V
50
Temperature (qC)
100
150
150
D002
-140
-145
-150
-155
VCC = 5 V
VCC = 12 V
-160
-50
0
D003
C(LOAD) = 10 nF
3.8
3.56
UVLO Off-Voltage (V)
3.57
3.76
3.74
3.72
100
150
D004
Figure 5. Body-Diode Conduction Sensing Threshold (VTH)
vs Temperature
3.82
3.78
50
Temperature (qC)
VCC = 12 V
ƒ = 100 kHz
Figure 4. Operating Supply current (ICC(OPERATE)) vs
Temperature
UVLO On-Voltage (V)
100
Figure 3. Standby Current (ICC(ON))vs Temperature
Body Diode Conduction Sensing Threshold (PA)
Operating Supply Current (mA)
13.5
3.7
-50
50
Temperature (qC)
No switching
Figure 2. Start-Up Current (ICC(UV)) vs Temperature
10
-50
0
D023
3.55
3.54
3.53
3.52
3.51
0
50
Temperature (qC)
100
150
3.5
-50
D005
Figure 6. UVLO On-Voltage (VCC(ON))vs Temperature
0
50
Temperature (qC)
100
150
D006
Figure 7. UVLO OFF-Voltage (VCC(OFF)) vs Temperature
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Typical Characteristics (continued)
0.5
Gate Drive Pulldown Resistance (:)
Gate Drive Pullup Resistance (:)
9
8
7
6
5
4
3
2
VCC = 5 V
VCC = 12 V
1
0
-50
0
50
Temperature (qC)
100
0.4
0.3
0.2
0.1
VCC = 5 V
VCC = 12 V
0
-50
150
Figure 8. Gate-Driver Pullup Resistance (R(UP)) vs
Temperature
Gate Drive Output Fall Time (ns)
Gate Drive Output Rise Time (ns)
100
150
D008
6
5
4
3
2
1
VCC = 5 V
VCC = 12 V
0
-50
0
50
Temperature (qC)
100
5
4
3
2
1
VCC = 5 V
VCC = 12 V
0
-50
150
11.4
Minimum IN Pulse Duration Which
Changes the Pin Output State (ns)
11.6
16
14
12
10
8
6
4
VCC = 5 V
VCC = 12 V
2
0
50
Temperature (qC)
50
Temperature (qC)
100
150
150
D010
11.2
11
10.8
10.6
10.4
10.2
VCC = 5 V
VCC = 12 V
10
9.8
-50
D011
Figure 12. Minimum VD Pulse Duration Which Changes the
DTC Pin Output State (tw(VD)) vs Temperature
100
Figure 11. Gate-Drive Output Rise Time (tf) vs Temperature
18
0
-50
0
D009
Figure 10. Gate-Drive Output Rise Time (tr) vs Temperature
Minimum VD Pulse Duration Which
Changes the DTC Pin Output State (ns)
50
Temperature (qC)
Figure 9. Gate-Driver Pulldown Resistance (R(DOWN)) vs
Temperature
6
8
0
D007
0
50
Temperature (qC)
100
150
D012
Figure 13. Minimum IN Pulse Duration Which Changes the
Pin Output State (tw(IN)) vs Temperature
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Typical Characteristics (continued)
25
Gate Turnoff Propagation Delay (ns)
Gate Turnon Propagation Delay (ns)
30
25
20
15
10
5
VCC = 5 V
VCC = 12 V
0
-50
0
50
Temperature (qC)
100
20
15
10
5
VCC = 5 V
VCC = 12 V
0
-50
150
Figure 14. Gate Turnon Propagation Delay (td(1)) vs
Temperature
100
150
D014
18
DTC Output Propagation Delay (ns)
Comparator-Controlled Turnon Delay for
Body Diode Conduction Detection (ns)
50
Temperature (qC)
Figure 15. Gate Turnoff Propagation Delay (td(2)) vs
Temperature
35
30
25
20
15
10
5
VCC = 5 V
VCC = 12 V
0
-50
0
50
Temperature (qC)
100
17
16
15
14
13
12
11
VCC = 5 V
VCC = 12 V
10
-50
150
0
D015
Figure 16. Comparator-Controlled Turnon Delay for BodyDiode Conduction Detection (td(COMP)) vs Temperature
50
Temperature (qC)
100
150
D016
Figure 17. DTC Output Propagation Delay (td(DTC)) vs
Temperature
30
25
Gate Turnoff Propagation Delay (ns)
Gate Turnon Propagation Delay (ns)
0
D013
25
20
15
10
40°C
25°C
125°C
5
0
20
15
10
5
40°C
25°C
125°C
0
0
5
10
Supply Voltage (V)
15
20
0
D017
Figure 18. Gate Turnon Propagation Delay (td(1)) vs Supply
Voltage (VCC)
5
10
Supply Voltage (V)
15
20
D018
Figure 19. Gate Turnoff Propagation Delay (td(2)) vs Supply
Voltage (VCC)
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Typical Characteristics (continued)
18
DTC Output Propagation Delay (ns)
Comparator-Controlled Turnon Delay for
Body Diode Conducation Detection (ns)
35
30
25
20
15
10
40°C
25°C
125°C
5
0
5
10
Supply Voltage (V)
15
15
14
13
12
11
10
40°C
25°C
125°C
9
20
0
5
D019
Figure 20. Comparator-Controlled Turnon Delay for BodyDiode Conduction Detection (td(COMP)) vs Supply Voltage
(VCC)
10
Supply Voltage (V)
15
20
D020
Figure 21. DTC Output Propagation Delay (td(DTC)) vs Supply
Voltage (VCC)
6
6
Gate Drive Output Fall Time (ns)
Gate Drive Output Rise Time (ns)
16
8
0
5
4
3
2
40°C
25°C
125°C
1
0
5
4
3
2
40°C
25°C
125°C
1
0
0
5
10
Supply Voltage (V)
15
20
0
D021
Figure 22. Gate-Drive Output Rise Time (tr) vs Supply
Voltage (VCC)
10
17
5
10
Supply Voltage (V)
15
20
D022
Figure 23. Gate-Drive Output Fall time (tf) vs Supply Voltage
(VCC)
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8 Detailed Description
8.1 Overview
The UCD7138 low-side gate driver is a high-performance driver for secondary-side synchronous rectification with
body-diode conduction sensing. The device is suitable for high-power high-efficiency isolated converter
applications where dead-time optimization is desired. The body-diode conduction is sensed at the falling edge of
the gate-drive signal and sent to the UCD3138A digital-power controller through one digital IO pin. The digital
controller can adjust the dead-time setting based on this information. The body-diode conduction time is detected
in a certain time window in the UCD3138A digital controller. This detection prevents reporting erroneous signals
because of noise or reverse current. At the gate turnon edge, the UCD7138 gate driver optimizes the dead time
by turning the gate on as soon as diode conduction is detected. The benefits of this driver to the system include,
but are not limited to, improved efficiency, improved reliability, and ease of design.
The internal gate driver is a single-channel, high-speed gate driver suitable for both 12-V and 5-V drive. The gate
driver offers 4-A source and 6-A sink (asymmetrical drive) peak drive current capability. The package and pin
configuration provide minimum parasitic inductances to reduce rise and fall times and to limit ringing.
Additionally, the short propagation delay with minimized tolerances and variations allows efficient operation at
high frequencies. The 5-Ω and 0.35-Ω pull-up and pull-down resistances boost immunity to hard switching with
high slew-rate dV and dt.
The internal body-diode conduction detector is a high-speed comparator with 20-ns propagation delay. The DTC
output is internally pulled high by default. When body-diode conduction is sensed, DTC pin drives low.
8.2 Functional Block Diagram
VDD_3p3V_IO
DTC
+
2
4
VD
5
OUT
±150 mV
10
Comparator
DTC Buffer
VDD_3p3V
CTRL
3
VCC
S
IN
1
VCC
6
R
LDO
Q
Q
VDD_3p3V
VDD_3p3V_IO
Gate Driver
Thermal Pad
(GND)
Bandgap and
UVLO
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8.3 Feature Description
8.3.1 Body-Diode Conduction Detection
In Figure 24, VDS is the drain-to-source voltage which is connected to the VD pin. The IN pin is the gate-driver
input-command signal from the UCD3138A digital controller. The DTC pin is the sensed body-diode conduction.
The OUT pin is the gate-driver output. The body-diode conduction detection comparator has a –150-mV
threshold. When the body diode conducts, the DTC pin is low. If the body diode does not conduct, the DTC pin is
high.
(V)
VDS
VDTC(th)
IN
DTC
OUT
(t)
td(2)
Gate turnon edge controlled
by the IN pin, if DTC low is
detected at the IN rising edge
td(COMP)
td(1)
td(2)
Gate turnon edge controlled
by the DTC pin, if DTC high is
detected at the IN rising edge
Figure 24. Input-Output Timing Diagram (Turn-On Optimization is Enabled)
To improve noise immunity, the comparator output DTC is blanked when the gate driver output, OUT, is high.
The DTC signal always outputs high when OUT is high.
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Feature Description (continued)
8.3.2 Gate Turnon and Turnoff
Gate turnon is controlled by both the gate driver input, IN, and body-diode conduction. System robustness is
enhanced through internal logic that guarantees that OUT is only allowed high if IN is also high. At the IN rising
edge, the UCD7138 gate-driver analyzes the DTC signal and determines the required course of action. The OUT
pin is sent high immediately if the DTC comparator output is low at the rising edge of the IN signal. If the DTC pin
is high at the rising edge of the IN signal, OUT is held low until DTC goes low. To allow the gate turnon edge to
optimize freely, setting the dead time between the primary side falling edge and the IN rising edge smaller than
expected in the UCD3138A digital controller is recommended.
The gate turnoff edge is determined by the IN signal only. The gate is turned off immediately at the IN falling
edge.
Table 1. Truth Table for CTRL Pin Function
CTRL PIN CONFIGURATION
FUNCTION
0 V or ground
Turn-on optimization disabled
3.3 V or floating
Turn-on optimization enabled
8.3.3 VCC and Undervoltage Lockout
The UCD7138 device has an internal undervoltage-lockout (UVLO) protection feature based on the VCC-pin
voltage. Whenever the driver is in the UVLO condition (such as when the VCC voltage is less than VCC(ON) during
power up or when the VCC voltage is less than VCC(OFF) during power down), the device holds all outputs low,
regardless of the status of the inputs. The UVLO voltage is typically 3.8 V with a 240-mV hysteresis. This
hysteresis helps prevent chatter when low VCC supply voltages have noise from the power supply and also when
droops occur in the VCC bias voltage.
For example, at power up, the UCD7138 driver output remains low until the VCC voltage reaches the UVLO
threshold. The magnitude of the OUT signal rises with VCC until steady-state VCC is reached. The output remains
low until the UVLO threshold is reached. The DTC signal begins to rise when VCC begins to rise. The internal
diode conduction detection comparator remains inactive until VCC passes VCC(ON) threshold.
VCC
VCC(ON)
VCC(OFF)
IN
OUT
VD
DTC
Figure 25. Device Power Up and Power Down
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8.3.4 Operating Supply Current
The UCD7138 device features very-low quiescent supply current. The total supply current is the sum of the
quiescent supply current, the average IOUT current from switching, and any current related to pull-up resistors on
the unused input pin. Knowing the operating frequency (ƒS) and the MOSFET gate (QG) charge, the average IOUT
current can be calculated as product of QG and ƒS.
8.3.5 Driver Stage
The input pins of the UCD7138 device are based on a CMOS-compatible input-threshold logic that is
independent of the VCC supply voltage. The logic-level thresholds can be conveniently driven with PWM control
signals derived from 3.3-V.
The output stage of the UCD7138 device features a unique architecture on the pull-up structure. This
architecture delivers the highest peak-source current when needed during the Miller-plateau region of the power
switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage
pull-up structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function
of the N-Channel MOSFET is to provide a brief boost in the peak sourcing current to enable fast turnon. This
boost occurs by briefly turning on the N-Channel MOSFET when the output is changing state from LOW to
HIGH.
VCC
ROH
R(NMOS),
pullup
Input Signal
Anti
ShootThrough
Circuitry
Gate
Voltage
Boost
OUT
Narrow pulse
at each turn on
ROL
Figure 26. Gate-Driver Output Structure
8.4 Device Functional Modes
8.4.1 UVLO Mode
When the VCC voltage to the device has not reached the VCC(ON) threshold or has fallen below the UVLO
threshold, VCC(OFF) , the device operates in the low-power UVLO mode. In this mode, most internal functions are
disabled and the ICC current is very low. In UVLO mode, the OUT pin is held low. The device passes out of
UVLO mode when the VCC voltage increases above the VCC(ON) threshold.
8.4.2 Normal Operation Mode
In this mode, the ICC current is higher because all internal control and timing functions are operating and the
gate-driver output, OUT, is driving the controlled MOSFET for synchronous rectification. In this mode, the VCC
current is the sum of ICC(ON) plus the average current required to drive the load on the OUT pin.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCD7138 device can be used in a wide range of applications. The device can be used on many centertapped secondary-side rectification topologies. Specifically, the device can be used in half-bridge LLC converters.
In these applications, the UCD3138A and UCD7138 chipset enables the synchronous rectifiers to closely
approximate the behavior of an ideal diode which is difficult to do in an LLC converter because of the variations
in the SR current-conduction time.
The UCD7138 and UCD3138A chipset together can provide an easy-to-use, high-performance and advanced
SR-control solution. Without this solution, fine tuning is required for each operation region (including below
resonant frequency, at resonant frequency, and above resonant frequency). For LLC converters in production,
each power stage may have a different resonant frequency because of tolerances of circuit capacitors and
inductors. Calibration is required for each converter to achieve high efficiency. With UCD7138 and UCD3138A
advanced SR control, optimal SR operation is easily achieved for every converter without fine tuning and
calibration of the resonant tank can be eliminated in production. For more information see Using UCD7138 and
UCD3138A for Advanced Synchronous Rectification Control, SLUA737.
9.2 Typical Application
9.2.1 Half-Bridge LLC
Figure 27 shows a typical half-bridge LLC application using the UCD7138 device as a secondary-side SR driver
and the UCD3138A device as a controller.
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Typical Application (continued)
UCD3138A
DPWM0A
DPWM0B
DPWM1A
DPWM1B
DTC0
DTC1
AD03
AD04
AD13
EAP0
EAN0
EAP1
Connect
to ground
or 3.3 V
V(BUS)
UCD7138
CTRL
6
OUT
4
VD
5
Thermal Pad
(GND)
1
IN
2
DTC
3
DPWM1B
DTC0
VCC
Q1
QSR2
Transformer
L(RES)
Q2
LK
Oring
Circuitry
NS
RL(RES)
LM
VOUT
NP
C(OUT1)
NS
RF(1)
C(OUT1)
AD03
EAP0
V(BUS)
Rectifier and
filter
RESR(2)
C(RES)
AD04
RESR(1)
RF(2)
CF
QSR1
EAN0
RS
CS
RS(1)
RS(2)
C(RES)
ADC13
EAP1
Driver
DPWM0B
Driver
DPWM0A
UCD7138
CTRL
Connect
to ground
or 3.3 V
6
OUT
4
VD
5
Thermal Pad
(GND)
1
IN
DPWM1A
2
DTC
DTC1
3
VCC
Figure 27. Half-Bridge LLC Typical Application Diagram
In LLC converters, if the SRs are not well optimized, the SR conduction time can either be too long or too short.
The duration of the body diode conduction time can be determined by examining the drain-to-source voltage of
the MOSFET when it is off. The SR turnon edge is optimized by the UCD7138 device by turning the gate on as
soon as body-diode conduction is sensed. The SR turnoff edge is determined when the UCD3138A digital
controller analyzes the sensed body-diode conduction time. Figure 28 shows the typical drain-to-source
waveforms on a half-bridge LLC converter and the desired waveforms.
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Typical Application (continued)
SR turn off too late
Set SR on time
Typical drain-tosource waveforms
without dead-time
optimization
Negative
current
reset
causes
body-diode
conduction
SR turns off
earlier
SR turn off too early
Set SR on time
Positive
current
reset
causes
body-diode
conduction
SR turns off
later
SR turn on too early
Set SR on time
Dead time is
too short; high
voltage spikes
can occur on
the other SR
SR turns off
later
SR turn on too late
Set SR on time
Dead time is
too long; low
efficiency
SR turns off
earlier
Desired
waveforms
Figure 28. Drain to Source Voltage Waveforms in a Typical Half Bridge LLC Application and Desired
Waveforms
As shown in Figure 29, when the SR pulse is on for too long, the drain-to-source voltage shoots up. The upper
waveform in Figure 29 shows the SR current. The lower waveform shows the SR drain-to-source voltage. The
black segment of the curves show when the SR MOSFET is on. The red and green segments of the curves show
when the SR MOSFET is off. The SR current is positive at first, but continues to drop until it is negative. The
drain-to-source voltage is close to 0 V when the SR MOSFET is on. As soon as the SR MOSFET is turned off,
the negative current must reset. The capacitance across the drain and source terminal is charged, and the drainto-source voltage increases. The green segments of the curves show when the negative current reset process is
complete at which point the body diode of the MOSFET conducts briefly again.
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Typical Application (continued)
Synchronous
Rectifier
Current
Negative
Current
Reset
D
Drain-to-Source
Voltage
Charged by
Negative
Current
Negative
Current
S
Negative Current
Charges Drain-toSource Voltage
Synchronous
Rectifier Current
Drain-to-Source
Voltage
SR MOSFET
Turnoff
Body-Diode
Conduction
Figure 29. SR Drain-to-Source Voltage Shoot Up When No Negative Current Flow Occurs
For the UCD3138A device, a DTC detection window is generated at the falling edge of the gate drive command
IN signal. Only during this detection window is the DTC low time counted by a 4-ns resolution timer capture
inside the UCD3138A device. Figure 30 shows the simplified system block diagram. In the two body-diode
conduction cases shown in Figure 31, the SR on time should be adjusted in different directions. The detection
window identify that these two cases are different. If, during the detection window, a large amount of DTC low
time is detected, and the SR turns off too early. If, during the detection window, no or very-short DTC low time is
detected and the SR turns off too late.
UCD3138A
DPWM
Module
IN
Detection
Window
Generation
OUT
UCD7138
4-ns
Timer
Capture
DTC
SR MOSFET
VD
Figure 30. Simplified System Block Diagram
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Typical Application (continued)
SR turnoff too early
SR turnoff too late
VD
Comparator
threshold
DTC
IN
Detection window
Figure 31. Body-Diode Connection Detection
The UCD3138A digital controller counts the body-diode conduction time of the current cycle and adjusts the SR
on time of the next cycle. In Figure 32, the DTC0 and DTC1 signals are the body-diode conduction inputs
received from the UCD7138 device. SR0_DPWM and SR1_DPWM are the DPWM waveforms for the SRs. The
red and green dashed lines are moving edges controlled by both the UCD3138A digital-compensator output and
the DTC interface. In each cycle, directly after the falling edge of the SR DPWM waveform, a detection window is
generated for the body-diode conduction time. The detection window is defined by both DETECT_BLANK and
DETECT_LEN registers. During this detection window, a 4-ns timer capture counts the conduction time of the
body diode. The SR DPWM turnoff edge of the next cycle is then adjusted accordingly.
SR0_DPWM
Adjust
SR1_DPWM
Detect
Detect
Adjust
DTC0
Detect
Detect
DTC1
DETECT_BLANK
DETECT_LEN
Figure 32. Timing Diagram of the DTC Interface in UCD3138A
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Typical Application (continued)
A_CNT or B_CNT value
127
¨= Manual Control register value
If in Manual Control Mode
¨= 1
TARGET_OFFSET
¨= 0
TARGET_LOW
¨= ±1
¨= Manual Control register value
Else if A_CNT or B_CNT < FLT_THRESH
¨= FLT_STEP
Else if A_CNT or B_CNT < TARGET_LOW
¨= ±1
Else if A_CNT or B_CNT > TARGET_LOW + TARGET_OFFSET
¨= 1
Else
¨= 0
FLT_THRESH
¨= FLT_STEP
0
Figure 33. DTC Interface Principle
Figure 33 shows how the SR turnoff edge is adjusted based on the DTC measurement of the previous cycle. The
A_CNT or B_CNT is the counted values of diode conduction time of two SRs which ranges from 0 to 127. The
two types of SR control modes are automatic-control mode and manual-control mode. If manual-control mode is
used, the SR on-time adjustment value is determined by the manual write register. If automatic-control mode is
used, the UCD3138A digital controller automatically calculates the SR on-time adjustment amount for the next
cycle. The body-diode conduction time at the falling edge of the SR gate is regulated to a target value by stepby-step edge adjustment in the UCD3138A device. The SR on time is reduced by a preprogrammed large
amount, when the sensed body-diode conduction time is less than a programmable threshold. This reduction
prevents the power supply from damaged caused by negative current in the SRs.
For more information on the DTC interface on UCD3138A see UCD7138 and UCD3138A for Advanced
Synchronous Rectification Control, SLAU737 and UCD3138A Highly Integrated Digital Controller for Isolated
Power, SLUSC66.
9.2.1.1 Design Requirements
9.2.1.1.1 Gate Input
The input stage of the driver should be driven by a signal with fast rise and fall times. Caution must be exercised
whenever the driver is used with slowly varying input signals, in situations where the device is located in a
mechanical socket or PCB layout is not optimal (bad grounding, for example). Ground bounce is often caused by
high di/dt current from the driver output, coupled with board-layout parasitic. The differential voltage between the
input pin IN and ground pad GND may be modified by ground bounce and trigger an unintended change of
output state. Because of short propagation delay, the unintended change of state can ultimately result in highfrequency oscillations, which increases power dissipation and can potentially damage the device. In the worst
case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1 nF) between
the input pin and ground very close to the driver device may be necessary.
9.2.1.1.2 Gate Output
The output of the gate driver (OUT) must be connected as close to the MOSFET gate as possible. A small
resistor may be connected in between to reduce the high-frequency oscillations on the gate. Doing so can also
slow down the gate transitions. The DTC detection windows inside UCD3138A may need some adjustment to
compensate for the delay caused by the added resistor.
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Typical Application (continued)
9.2.1.1.3 Drain-to-Source Voltage Sensing
When the drain-to-source voltage is below 0 V, current flows out of the VD pin to the drain terminal of the
MOSFET. This current flow must be limited to ensure proper operation of the device. The recommended currentlimiting resistance value is 20Ω.
The highest voltage that can be applied to VD pin is 45 V which is good for applications where 40-V MOSFETs
are used for the secondary-side SRs. If a higher voltage is required for VD pin, an external high-voltage blocking
circuit can be used together with the UCD7138 device as shown in Figure 34. Depending on the required voltage
rating, a different external high-voltage blocking MOSFET can be selected. Usually a small SOT-23 MOSFET
can be used. In this circuit, the gate terminal of the external high-voltage blocking MOSFET is connected to VCC
of the UCD7138 gate driver. The source terminal is connected with a current-limiting resistor to the VD pin of the
UCD7138 device. The drain terminal is connected to the SR MOSFET drain terminal. When a low voltage is
presented at the drain terminal, the blocking MOSFET is turned on because of the positive gate-to-source
voltage. When the drain voltage becomes higher and higher, the source terminal voltage rises along with the
drain terminal until the gate-to-source voltage falls below the threshold. When the source voltage is high enough
so that the blocking MOSFET is turned off, the high voltage on the SR drain is blocked.
UCD7138
Connect to
SR MOSFET
drain terminal
D
CTRL
6
OUT
4
Thermal Pad
(GND)
VD 5
S
1
IN
2
DTC
3
VCC
G
Figure 34. External High-Voltage Blocking Circuit
9.2.1.1.4 DTC Output
The DTC pin is the internal comparator output. This pin should be connected to the DTC0 or DTC1 pin on the
UCD3138A device. To keep edges sharp, no filtering is recommended. If noise spikes are observed on the DTC
signal, the blanking times in the UCD3138A device can be used to prevent the digital controller from sensing
noise. This pin is not designed to drive large current. If filtering must be used, ensure that the sink and source
current on this pin is within ±4 mA as specified in the
Electrical Characteristics table.
9.2.1.1.5 Turn-on Edge Optimization
The turnon edge optimization is useful when a positive current flow is at the rising edge of SRs. To maximize the
efficiency gain, the dead time between the falling edge of the primary and the rising edge of the secondary
should be programmed to a smaller value than expected, so that the rising edge of the SRs can move freely by
UCD7138.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Design Without SR-Control Optimization
The design procedure of an LLC converter with synchronous rectification can be greatly simplified by using the
UCD7138 and UCD3138A chipset. The converter hardware and firmware can initially be designed without
advanced SR optimization and then add SR optimization function in.
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Typical Application (continued)
For more information on the UCD3138A-based digital LLC converter, UCD3138A Highly Integrated Digital
Controller for Isolated Power, SLUSC66.
9.2.1.2.2 Setting the DTC Detection Window
The body-diode conduction should be detected in a specific region for the system to operate correctly. The
detection window is defined by a blanking time register DETECT_BLANK and a detection length register
DETECT_LEN in the UCD3138A device. To set the detection window, let the LLC converter operate below
resonant frequency. measure the VD, IN, and DTC waveforms on an oscilloscope. Use cursors to measure the
time, t, difference between the IN falling edge and the starting point of body-diode conduction (first falling edge of
DTC excluding noise spike). The blanking time should be set to be less than t. Usually the required blanking time
is very short or non existent, so the blanking time can be set to around 10% of t. The detection window length
can be set to a few times of the desired body-diode conduction time. For example, if the desired body-diode
conduction time is 40 ns, the detection window length can be set to 120 ns. Make sure that the body-diode
conduction is well covered inside the detection window when it is at an optimal value. The end point of the
detection window should never exceed the first valley on the VD waveform to avoid errors in measurement (see
Figure 35).
Measure the time difference between the SR turn-off
command and body diode conduction starting point
First valley
Noise
spike
VD
Body-diode
conduction
IN
OUT
DTC
Detect
Blank
Figure 35. Setting the DTC Detection Window in UCD3138A
After the detection window is set, enable the DTC module in manual control mode. Set the offset in the manual
control registers to 0. Change the input voltage and load current to different operation points to verify that the
UCD3138A DTC module measures the correct values in the A_CNT and B_CNT registers. See the
UCD3138A64 Programmer’s Manual, SLUUB54 for detailed register information.
9.2.1.2.3 Setting the Clamps
The SR adjustment accumulator clamps defines the maximum SR turnoff edge offset from the calculated value
from the UCD3138A compensator. The maximum clamp can be set to prevent the SR on time from going too
long and causing shoot through. The minimum clamp can be set based on the light load condition where the
desired SR turnoff edge offset is the maximum.
In addition to the SR adjustment accumulator clamps, the SR pulse falling edge is naturally clamped at 50% or
100% or the switching period in UCD3138A. This natural clamp is a default feature of UCD3138A and does not
require any special setting.
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Typical Application (continued)
9.2.1.2.4 Setting the DTC Optimization Target and Hysteresis
The body diode must maintain a minimum conduction time for the UCD3138A DTC interface to function properly.
The minimum body-diode conduction time is set by the DTC target and target register. A target hysteresis
register can also be set to reduce the steady-state output-voltage ripple.
9.2.1.2.5 Setting the DTC Negative Current Fault Protection
If the detected body-diode conduction time is less than the programmed threshold, negative current can occur.
This threshold can be set by the fault threshold register in the UCD3138A DTC module. If a DTC fault is
detected, the SR on time is reduced by a programed step size in the next switching cycle. This step size is
defined by FLT_STEP register in the DTC module. To avoid noise and jitter in the negative current fault
detection, a consecutive DTC fault counter can be used. A fault step is executed only after a consecutive number
of faults are detected.
After all these registers are set, enable the UCD3138A DTC module in automatic control mode, enable the
turnon-edge optimization on the UCD7138 device, and review the different operation conditions to see the overall
system performance. The DTC module can be turned on or off by toggling DTC_EN bit in Loop Mux register in
UCD3138A. The performance before and after SR optimization control can be compared very easily as shown in
the Application Curves section.
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Typical Application (continued)
9.2.1.3 Application Curves
Blank
Detect
Blank
DTC (2 V/div)
DTC (2 V/div)
VD (2 V/div)
VD (2 V/div)
No optimization, SR on time too long.
High VDS stress on the other SR.
Horizontal: 200 ns/div
With optimization
Horizontal: 200 ns/div
Figure 36. SR Turnoff Edge Before Optimization
Blank
Figure 37. SR Turnoff Edge After Optimization
Blank
Detect
DTC (2 V/div)
DTC (2 V/div)
VD (2 V/div)
VD (2 V/div)
Figure 38. SR Turnoff Edge Before Optimization
Detect
With optimization
Horizontal: 200 ns/div
No optimization, SR on time too short. Low efficiency.
Horizontal: 200 ns/div
24
Detect
Figure 39. SR Turnoff Edge After Optimization
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Typical Application (continued)
VD (5 V/div)
VD (5 V/div)
DTC (5 V/div)
DTC (5 V/div)
No optimization, SR on turnon too late. Low efficiency.
Horizontal: 200 ns/div
Figure 40. SR Turnon Edge Before Optimization
With optimization
Horizontal: 200 ns/div
Figure 41. SR Turnon Edge After Optimization
VD (5 V/div)
VD (5 V/div)
DTC (5 V/div)
DTC (5 V/div)
No optimization, SR turnon too early.
Horizontal: 200 ns/div
With optimization
Horizontal: 200 ns/div
Figure 42. SR Turnon Edge Before Optimization
Figure 43. SR Turnon Edge After Optimization
95
Efficiency (%)
94
93
Without UCD7138 +
UCD3138A SR
Optimization
With UCD7138 +
UCD3138A SR
Optimization
92
91
90
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
Load Current (A)
D001
Efficiency increase at peak efficiency: 0.54% Peak efficiency increase (occurs at no-load): 2.62%
Average efficiency increase over constant voltage load range: 0.63%
Peak efficiency with and without SR optimization: 94.85% at 19.92 A
Figure 44. Efficiency Comparison with and without UCD7138 + UCD3138A Advanced SR Control
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SLVSCS1B – MARCH 2015 – REVISED MAY 2015
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10 Power Supply Recommendations
Because the driver draws current from the VCC pin to bias all internal circuits, for the best high-speed circuit
performance, two VCC bypass capacitors are recommended to prevent noise problems. The use of surface-mount
(SM) components is highly recommended. A 1μF ceramic capacitor should be placed as close as possible to the
VCC to ground pad of the gate driver.
11 Layout
11.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device
operation and design robustness. The following circuit layout guidelines are strongly recommended.
• Place the driver device as close as possible to power and ground to minimize the length of high-current
traces between the output pins and the gate of the power device.
• Place the VCC bypass capacitors between the VCC pin and ground as close as possible to the driver with
minimal trace length to improve the noise filtering. These capacitors support the high-peak current that is
drawn from the VCC supply during turnon of the power MOSFET. The use of low inductance SM components
such as chip resistors and chip capacitors is highly recommended.
• The turnon and turnoff current-loop paths (driver device, power MOSFET, and VCC bypass capacitors) should
be minimized as much as possible to keep the stray inductance to a minimum.
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The ground
of the driver should be connected to the other circuit nodes such as the source of power switch, ground of
PWM controller, and others at one single point. The connected paths should be as short as possible and as
wide as possible to reduce resistance and inductance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at the OUT pin can corrupt the input
signals during transition. The ground plane must not be a conduction path for any current loop. Instead, the
ground plane must be connected to the star-point with one single trace to establish the ground potential.
• A 1-Ω resistor may be connected between OUT pin and the gate terminal of the MOSFET to reduce gate to
source voltage ringing.
• A 20-Ω resistor should be connected between VD pin and the drain terminal of the MOSFET to limit the
current flowing out of VD pin when the drain terminal voltage is negative.
26
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UCD7138
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SLVSCS1B – MARCH 2015 – REVISED MAY 2015
11.2 Layout Example
D
D
D
D
Top Layer
Bottom Layer
Multi-Layer
D
Via
CTRL
6
VD
5
OUT
4
Thermal Pad
(GND)
20
S
S
S
G
1
IN
2
DTC
3
VCC
Via 1
Via
1 µF
Figure 45. Layout Example With Surface-Mount MOSFET
Top Layer
Bottom Layer
Multi-Layer
S
Via
IN
1
6
CTRL
D
DTC
2
VCC
3
Thermal Pad
(GND)
5
VD
4
OUT
20 Q
G
1 Q
1 µF
Figure 46. Layout Example With Through-Hole MOSFET
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• UCD3138A Highly Integrated Digital Controller for Isolated Power, SLUSC66
• Using UCD7138 and UCD3138A for Advanced Synchronous Rectification Control, SLUA737
• UCD3138 Digital Power Peripherals Programmer’s Manual , SLUU995
• UCD3138A Migration Guide, SLUA741
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCD7138DRSR
ACTIVE
SON
DRS
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UD7138
UCD7138DRST
ACTIVE
SON
DRS
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UD7138
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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