USBN9602-28MX

USBN9602 USBN9602 (Universal Serial Bus) Full Speed Function Controller with DMA Support Literature Number: SNOS029A USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support 1.0 General Description Block Diagram CS RD WR trol endpoint EP0 and six FIFOs for an additional six unidirectional Endpoint Pipes to support USB interrupt, bulk and isochronous data transfers. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements. et e The USBN9602 is an integrated USB Node controller compatible with the USB Specification Versions 1.0 and 1.1. Integrated onto a single IC are the required USB transceiver with a 3.3V Regulator, Media Access Controller, USB endpoint (EP) FIFOs, a versatile 8-bit parallel interface, MICROWIRE/PLUS™ Interface and a clock generator. A total of seven FIFO buffers support the different USB messages: one bidirectional FIFO for the mandatory con- A0/ALE D[7:0]/AD[7:0] INTR MODE[1:0] ol Microcontroller Interface Endpoint/Control FIFOs Status EP2 EP4 EP6 RX EP1 EP3 EP5 TX O Endpoint0 bs Control 48 MHz Oscillator Clock RESET Vcc GND XIN XOUT CLKOUT Generator SIE Media Access Controller (MAC) Clock Recovery Physical Layer Interface (PHY) USB Event Detect V3.3 Transceiver D+ D- VReg AGND Upstream Port ® TRI-STATE is a registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS™ and MICROWIRE ™ are trademarks of National Semiconductor Corporation. © 1998 National Semiconductor Corporation www.national.com USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support November 1998 2.0 Features et e ■ ■ ■ ol ■ bs ■ ■ Full-Speed USB Node Device USB transceiver 3.3V signal voltage regulator 48 MHz oscillator circuit Programmable clock generator Serial Interface Engine consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification 1.0 compliant Control/Status Register File USB Function Controller with seven FIFO-based Endpoints: – One bidirectional Control Endpoint 0 (8 bytes) – Three Transmit Endpoints (2*32 and 1*64 bytes) – Three Receive Endpoints (2*32 and 1*64 bytes) 8-bit parallel interface with two selectable modes: – non-multiplexed – multiplexed (Intel compatible) DMA support for parallel interface MICROWIRE/PLUS™ Interface 28-pin SO package O ■ ■ ■ ■ ■ ■ 2 www.national.com Table of Contents 11.0 et e 10.0 Transmit Mask Register (TXMSK) . . . . . . . . . . . 26 Receive Event Register (RXEV) . . . . . . . . . . . . . 27 Receive Mask Register (RXMSK) . . . . . . . . . . . 27 NAK Event Register (NAKEV) . . . . . . . . . . . . . . 27 NAK Mask Register (NAKMSK) . . . . . . . . . . . . . 27 FIFO Warning Event Register (FWEV) . . . . . . . . 27 FIFO Warning Mask Register (FWMSK) . . . . . . 28 Frame Number High Byte Register (FNH) . . . . . 28 Frame Number Low Byte Register (FNL) . . . . . . 28 Function Address Register (FAR) . . . . . . . . . . . . 28 Endpoint Control Register 0 (EPC0) . . . . . . . . . . 29 Transmit Status Register 0 (TXS0) . . . . . . . . . . . 29 Transmit Command Register 0 (TXC0) . . . . . . . 29 Transmit Data Register 0 (TXD0) . . . . . . . . . . . . 30 Receive Status Register 0 (RXS0) . . . . . . . . . . . 30 Receive Command Register 0 (RXC0) . . . . . . . . 30 Receive Data Register 0 (RXD0) . . . . . . . . . . . . 31 Endpoint Control Register x (EPC1 through EPC6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.29 Transmit Status Register x (TXS1, TXS2, TXS3) 31 11.30 Transmit Command Register x (TXC1, TXC2, TXC3) 32 11.31 Transmit Data Register x (TXD1, TXD2, TXD3) . 32 11.32 Receive Status Register x (RXS1, RXS2, RXS3) 33 11.33 Receive Command Register x (RXC1, RXC2, RXC3) 33 11.34 Receive Data Register x (RXD1, RXD2, RXD3) . 34 Design considerations . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 Targeted Applications . . . . . . . . . . . . . . . . . . . . . 35 12.2 3.3V Regulator Issues . . . . . . . . . . . . . . . . . . . . 35 12.3 Simplified Application Diagrams . . . . . . . . . . . . . 35 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Electrical Characteristics - PRELIMINARY . . . . . . . . 37 14.1 Parallel Interface Timing (MODE[1:0] = 00b) . . . 39 14.2 Parallel Interface Timing (MODE[1:0] = 01b) . . . 41 14.3 DMA Support Timing . . . . . . . . . . . . . . . . . . . . . 43 14.4 MICROWIRE Interface Timing (MODE[1:0] = 10b) . . . . . . . . . . . . . . . . . . . . . . . 44 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.0 13.0 14.0 ol 7.0 8.0 9.0 bs 4.0 5.0 6.0 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 11.23 11.24 11.25 11.26 11.27 11.28 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Voltage Regulator (VReg) . . . . . . . . . . . . . . . . . . . 4 3.3 Serial Interface Engine (SIE) . . . . . . . . . . . . . . . . . 4 3.4 Endpoint/Control FIFOs . . . . . . . . . . . . . . . . . . . . . 4 3.5 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . 5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Non-Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MICROWIRE/PLUS Interface . . . . . . . . . . . . . . . . . . . . 13 Device Functional States . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 Suspend Operation . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 Remote Resume . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.3 USB Resume Operation . . . . . . . . . . . . . . . . . . . 16 9.4 Functional State Transitions . . . . . . . . . . . . . . . . 16 Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 Transmit and Receive Endpoint FIFOs . . . . . . . . 18 10.2 Bidirectional Control Endpoint FIFO0 Operation . 19 10.3 Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2, TXFIFO3) . . . . . . . . . . . . . . . . . . . . . . 19 10.4 Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) . . . . . . . . . . . . . . . . . . . . . . 20 10.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . 21 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.1 Main Control Register (MCNTRL) . . . . . . . . . . . . 23 11.2 Clock Configuration Register (CCONF) . . . . . . . . 23 11.3 DMA Control Register (DMACNTRL) . . . . . . . . . 24 11.4 RevisionIdentifierRegister(RID)RevisionIdentifier(RID) 24 11.5 Node Functional State Register (NFSR) . . . . . . . 24 11.6 Main Event Register (MAEV) . . . . . . . . . . . . . . . . 25 11.7 Main Mask Register (MAMSK) . . . . . . . . . . . . . . 25 11.8 Alternate Event Register (ALTEV) . . . . . . . . . . . . 25 11.9 Alternate Mask Register (ALTMSK) . . . . . . . . . . . 26 11.10 Transmit Event Register (TXEV) . . . . . . . . . . . . . 26 15.0 O 1.0 2.0 3.0 3 www.national.com 3.0 Device Overview The USB standard specifies bit stuffing and unstuffing as a method to ensure adequate transitions on the line to enable clock recovery at the receiving end. Whenever a string of consecutive 1s is encountered, the bit-stuffing logic inserts a 0 after every sixth 1 in the data stream. The bit-unstuffing logic reverses this process. The USBN9602 is an integrated USB Node controller. The block diagram on page 1 of the data sheet shows the major on-chip components of the device. 3.1 Transceiver The USBN9602 contains a high-speed transceiver, which consists of three main functional blocks: The clock recovery block uses the incoming NRZI data to extract a data clock (12 MHz) from an input clock derived from a crystal or crystal oscillator (48 MHz frequency). This clock is used in the data recovery circuit. The output of this block is binary data (decoded from the NRZI stream) that can be appropriately sampled using the extracted 12 MHz clock. The jitter performance and timing characteristics meet the requirements set forth in Chapter To minimize signal skew, the differential output swings of 7 of the USB Specification. the transmitter are well balanced. Slew-rate control is used on the driver to minimize radiated noise and cross 3.4 Endpoint/Control FIFOs talk. The drivers support TRI-STATE® operation to allow The Endpoint Pipe Controller (EPC) provides the interface bidirectional half-duplex operation of the transceiver. for USB Function endpoints. An endpoint is the ultimate The differential receiver operates over the complete com- source or sink of data. An endpoint pipe provides for the mon mode range, that is guaranteed to be larger than that movement of data between USB and memory, and comof the single-ended receivers, to avoid potential glitches in pletes the path between the USB Host and the function the Serial Interface Engine (SIE) after Single-Ended Ze- endpoint. According to the USB specification, up to 31 such endpoint pipes are supported at any given time, ros. each with the same Function Address. The USBN9602, Single-ended receivers are present on each of the two however, supports a maximum of seven endpoint pipes. data lines. These are required, in addition to the differential receiver, to detect an absolute voltage with a switching A USB Function is a USB device that is able to transmit threshold between 0.8V and 2.0V (TTL inputs). An exter- and receive information on the bus. A Function may have nal 1.5 ± 5% kΩ resistor, tied to a voltage source between one or more configurations, each of which defines the in3.0V and 3.6V referenced to the local ground, is required terfaces that make up the device. Each interface, in turn, is composed of one or more endpoints. on D+ to indicate that this is a high-speed node. Each endpoint is an addressable entity on USB and is required to respond to IN and OUT tokens from the USB Host (typically a PC). An IN token indicates that the host has requested to receive information from an endpoint, and an OUT token indicates that the host is about to send information to an endpoint. bs 3.2 Voltage Regulator (VReg) ol et e – differential receiver – single-ended receiver with on-chip voltage reference – transmitter with on-chip current source The performance requirements met by this transceiver are described in Chapter 7 of the Universal Serial Bus Specification Version 1.0. O The Voltage Regulator provides a 3.3V voltage from the 5.0V device power for the integrated transceiver. This 3.3V output can be used to supply power to the 1.5 kΩ pull-up resistor. It can be disabled under software control to allow using the device in a 3.3V system. This output must be decoupled with a 10 µF tantalum capacitor to Upon detection of an IN token addressed to an endpoint, the endpoint is responsible for responding with a data ground. packet. If the endpoint is currently stalled, a STALL hand3.3 Serial Interface Engine (SIE) shake packet is sent under software control. If the endThe USB Serial Interface Engine (SIE) consists of a Phys- point is enabled, but no data is present, a NAK (Negative ical Layer Interface (PHY) level and a Media Access Con- Acknowledgment) handshake packet is sent automatically. troller (MAC) level. The PHY level includes the digital- If the Endpoint is Isochronous and enabled, but no data clock recovery circuit, a digital glitch filter, End_Of_Packet present, a bit stuff error followed by an end of packet is detection circuitry, and bit stuffing and unstuffing logic. sent on the bus. The MAC level includes packet formatting, CRC genera- Similarly, upon detection of an OUT token addressed to tion and checking, endpoint address detection, and pro- an endpoint, the endpoint is responsible for receiving a vides the necessary control to give the NAK, ACK, and data packet sent by the host and storing it in a buffer. If STALL responses as determined by the Endpoint Control- the endpoint pipe is currently stalled, a STALL handshake ler for the specified endpoint pipe. The SIE is also respon- packet is sent at the end of the data transmission. If the sible for detecting and reporting events on detection of endpoint pipe is currently disabled, no handshake packet USB-specific events such as Reset, Suspend, and Re- is sent at the end of the data transmission. If the endpoint sume. The transmitter outputs of the module to the trans- pipe is enabled, but no buffer is present in which to store ceiver are well matched (under 1 ns) to minimize skew on the data, a NAK (Negative Acknowledgment) handshake the USB signals. packet is sent. If the Endpoint is Isochronous and enabled but can’t handle the data, the data will be lost. 4 www.national.com 4.0 Connection Diagram A Disabled endpoint does not respond to IN, OUT, or SETUP tokens. The Endpoint Pipe Controller maintains separate status and control information for each endpoint pipe. For IN tokens, the Endpoint Pipe Controller is responsible for transferring data from the defined buffer to the host. For OUT tokens, the Endpoint Pipe Controller is responsible for transferring data from the host to the defined buffer. 3.5 Microcontroller Interface A CPU or microcontroller can be connected via an 8-bit parallel interface or a MICROWIRE interface. For the parallel interface, there are two addressing modes (multiplexed or non-multiplexed). These modes are selected by hardwiring the proper binary code on the MODE1 and MODE0 pins. 1 28 CLKOUT 2 27 XOUT 3 26 INTR 4 25 XIN MODE0 DRQ 5 24 MODE1 DACK 6 23 GND 22 21 Vcc GND A0/ALE/SI D0/SO 7 28 pin 8 SO D1 9 20 D– D2 10 19 D3 11 18 D+ V3.3 D4 D5 12 17 13 16 AGND RESET D6 14 15 D7 et e In addition, an interrupt output is provided. The type of the interrupt can be programmed to be either push-pull activehigh or active-low output, or an open-drain active-low output. CS RD WR/SK Order Number USBN9602-28M See NS Package Number M28B O bs ol Figure 1. USBN9602 Connection Diagram 5 www.national.com 5.0 Pin Descriptions ble), and a brief description of the pin function. The following tables briefly describe the USBN9602 pins. Each table lists a related set of device pins and shows the device pin number, the signal direction (“I” for input, “O” for output, “I/O” for bidirectional, or N.A. for not applica- Note that unused input or bidirectional pins must be pulled up or down as appropriate. This is essential to reduce overall power consumption and to limit EMI. 5.0.1 Power Supply Pin # 22 Dir Label N.A. Vcc 21,23 N.A. GND Pin Functional Description Digital Power Supply (Vcc) Digital Power Supply (GND) N.A. AGND Analog Power Supply (AGND) 18 N.A. V3.3 Transceiver 3.3V Voltage Supply. This pin can be used as the internal 3.3V voltage regulator output. The regulator is intended to power only the internal transceiver and one external pull-up. An external 1 µF de-coupling capacitor is required on this pin. The voltage regulator output is disabled upon hardware reset. If the internal voltage regulator is left disabled, this pin can be used as an 3.3V supply input for the transceiver. et e 17 5.0.2 Oscillator, Clock and Reset Pin # Dir Label Pin Functional Description N.A. XIN Input for internal 48 MHz crystal oscillator circuit. A 48 MHz third harmonic crystal may be used. 27 N.A. XOUT Output for the internal crystal oscillator circuit. ol 26 O CLKOUT Clock Output. This pin provides a programmable clock source. Upon hardware reset, this pin sources a 4 MHz clock (there may be an initial phase discontinuity). It may be programmed for different speeds or disabled via the Clock Configuration Register (these subsequent transitions are synchronous and will occur smoothly). 16 I RESET bs 28 Active-Low Reset input. Signal conditioning is provided on this pin to allow the use of a simple RC power-on reset circuit. Oscillator Circuits O The XIN and XOUT pins may be connected to make a 48 MHz closed loop crystal controlled oscillator. Alternately an external 48 MHz clock source may be input to clock the device. The internal crystal oscillator uses a 48 MHz 3rd harmonic crystal. The circuit for the crystal option is shown in Figure 2. If an external clock source is used, it is connected to XIN. XOUT is unconnected. XIN XTAL1 C1 C3 Stray capacitance and inductance should be kept as low as possible in the oscillator circuit. Trace lengths should be minimized by locating the crystal and external components as close as possible to the XIN and XOUT pins. 48 MHz OSC C2 L1 Note: The circuit shown has been tested with crystals from ECS Inc. only (e.g. part number ECS-480-S-1-3OT). For other crystals , please consult the manufacturer for recommended circuit and component values. Figure 2. 3rd Harmonic Crystal Oscillator Connections 6 www.national.com 5.0 Pin Descriptions (Continued) Component Values Tolerance 48 MHz Parallel AT-Cut 40 Ω 7 pF 1 mW 2500 ppm C1 22 pF 10% C2 56 pF 10% C3 100 nF 10% L1 470 nH 10% Crystal 1 Parameters Resonance Frequency Third Overtone Type Maximum Effective Series Resistance Maximum Shunt Capacitance Maximum Drive Level 5.0.3 USB Port Dir Label Pin Functional Description 19 I/O D+ USB D+ upstream port. This pin requires an external 1.5k pull-up to 3.3V to signal full speed operation. 20 I/O D– USB D– upstream port. O bs ol et e Pin # 7 www.national.com 5.0 Pin Descriptions (Continued) 5.0.4 Microprocessor Interface Pin # Dir 24:25 I Label Pin Functional Description MODE[1:0] Interface Mode select input pins. Each of these pins should be hard-wired to Vcc or GND to select the interface mode: MODE[1:0] = 00: Mode 0: non-multiplexed parallel interface mode MODE[1:0] = 01: Mode 1: multiplexed parallel interface mode MODE[1:0] = 10: Mode 2: MICROWIRE interface mode MODE[1:0] = 11: Mode 3: reserved† †Note: Mode 3 also selects the MICROWIRE interface mode in the USBN9602, but this mode should be reserved to preserve compatibility with future devices. I DACK Active-low DMA Acknowledge. This pin is only used if DMA is enabled. If DMA is not used, this pin must be tied to Vcc. 5 O DRQ DMA Request. This pin is only used if DMA is enabled. 4 O INTR Interrupt Output. The interrupt signal modes (active high, active low or open drain) can be programmed via the Main Control Register. During Reset, this pin is placed in the TRISTATE mode. 1 I CS Active-low chip select signal. 2 I RD Active-low read signal for parallel interface. 3 I WR Mode 0,1: Active-low write signal for parallel interface. SK Mode 2: MICROWIRE shift clock A0 Mode 0 address bus line A0 for parallel interface. I ALE 8 I/O SI Mode 2 MICROWIRE Serial Input D0 Mode 0 Data bus line D0 I/O SO Mode 2 MICROWIRE Serial Output D1 Mode 0 Data bus line D1 AD1 I/O D2 Mode 1 Address/Data bus line AD1 Mode 0 Data bus line D2 O 10 Mode 1 Address/Data bus line AD0 bs AD0 9 Mode 1 Address Latch Enable for parallel interface. ol 7 et e 6 AD2 11 I/O D3 AD3 12 I/O D4 AD4 13 I/O D5 AD5 14 I/O D6 AD6 15 I/O D7 AD7 Mode 1 Address/Data bus line AD2 Mode 0 Data bus line D3 Mode 1 Address/Data bus line AD3 Mode 0 Data bus line D4 Mode 1 Address/Data bus line AD4 Mode 0 Data bus line D5 Mode 1 Address/Data bus line AD5 Mode 0 Data bus line D6 Mode 1 Address/Data bus line AD6 Mode 0 Data bus line D7 Mode 1 Address/Data bus line AD7 8 www.national.com 6.0 Parallel Interface The parallel interface allows the USBN9602 to function as 6.1 Non-Multiplexed Mode a CPU or microcontroller peripheral. One of two interface The non-multiplexed mode uses the control pins CS, RD, modes can be selected via the MODE0 pin while the WR, the address pin A0, and the bidirectional data bus MODE1 pin is pulled low: D[7:0], as shown in Figure 3. This mode is selected by tying both the MODE1 and MODE0 pin to GND. – Non-multiplexed mode – Multiplexed mode The CPU has direct access to the registers DATA_IN, DATA_OUT and ADDR. Reading and writing data to the USBN9602 can be done either in standard or burst mode. See Figure 4 for timing information on the signal timing in non-multiplexed mode. CS DATA_IN 0x00 A0 DATA IN WR et e RD DATA OUT D[7:0] ol DATA_OUT ADDRESS bs ADDR 0x3F REGISTER FILE O Figure 3. Non-Multiplexed Mode Interface Block Diagram 9 www.national.com 6.0 Parallel Interface (Continued) CS A0 RD WR D[7:0] out out et e input Write Address Read Data Burst Read Data Figure 4. Non-Multiplexed Mode Basic Timing Diagram 6.1.4 ADDRESS 6.1.1 Standard Access Mode The address register (ADDR) acts as a pointer to the internal memory. This register is write-only and is cleared upon reset. ol The standard USBN9602 access sequence for the nonmultiplexed interface mode is to write the address to the ADDRESS register and then read or write the data from/to the DATA_OUT/DATA_IN register. Updating of the DATA_OUT register occurs following the write of the ADDR register. Selection between the ADDRESS register and the DATA_OUT/DATA_IN register is done with the A0 input. 6.1.5 DATA_OUT bs The Data Output register (DATA_OUT) is updated with the memory register to which the ADDR register is pointing. Update occurs under the following conditions: 1. After the ADDR register is written 2. After a read from the DATA_OUT register In burst mode, the ADDR register is written once with the memory address of the desired on-chip register. Then 3. After a write to the DATA_IN register consecutive reads/writes are performed to the This register is read-only and holds undefined data after DATA_OUT/DATA_IN register without writing a new ad- reset. dress. The DATA_OUT register contents for read opera- 6.1.6 DATA_IN tions are updated once after every read. The Data Input register (DATA_IN) holds the data which is 6.1.3 User Registers written to the USBN9602 address ADDR is pointing to. The following table gives an overview of the parallel inter- This register is write-only and is cleared upon reset. face registers in non-multiplexed mode. In the table, the reserved bits return undefined data on read and should be 6.2 Multiplexed Mode The multiplexed mode uses the control pins CS, RD, WR, written with zero. the address latch enable signal ALE, and the bidirectional A0 Access Register Bit Number address data bus AD[7:0], as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to 7 6 5 4 3 2 1 0 Vcc. 0 read DATA_OUT The address is latched into the ADDR register while ALE O 6.1.2 Burst Mode 0 write DATA_IN 1 read reserved 1 write reserved is high and data is output/input with the next active RD or WR signal. All registers are directly accessible in this interface mode. Figure 7 shows the basic timing. ADDRESS[5:0] 10 www.national.com 6.0 Parallel Interface (Continued) CS DATA IN 0x00 WR RD DATA OUT AD[7:0] EN ALE ADDR et e ADDRESS 0x3F REGISTER FILE ol Figure 6. Multiplexed Mode Interface Block Diagram bs ALE O CS RD or WR AD[7:0] ADDR DATA Figure 7. Multiplexed Mode Basic Read/Write Timing 11 www.national.com 7.0 DMA Support The USBN9602 supports DMA transfers with an external DMA controller to and from Endpoints 1 through 6. In this mode, the device pins DRQ and DACK are used in addition to the parallel interface pins RD or WR and the data D[7:0] pins. The DMA mode can only be used with the parallel interface modes (MODE1 tied to GND). The read or write address is generated internally and the state of the A0/ALE pin is ignored during a DMA cycle. Figure 8 shows the basic DMA read timing and Figure 9 shows the basic DMA write timing. The DMA support logic has a lower priority than the parallel interface. CS needs to stay inactive during a DMA cycle. If CS becomes active, DACK is ignored and a regular read/write operation is performed. Only one Endpoint can be enabled at a given time to issue a DMA request when data is received or transmitted. DRQ DACK WR D[7:0] To enable DMA transfers, the following steps must be performed: Figure 8. DMA Write to USBN9602 et e 1. The local CPU programs the DMA controller for fly-by demand mode transfers. In this mode, transfers occur only when the USBN9602 requests them via the DRQ pin. The data is read/written from/to the USBN9602 receive/transmit FIFO and written/read into/from local memory during the same bus transaction. 2. The DMA address counter is programmed to point to the destination memory block in the local shared memory, and the byte count register is programmed with the number of bytes in the block to be transferred. 3. The DMA request enable bit and DMA source bits are set in the USBN9602. In addition, the software must set the respective Endpoint enable bit. 4. The USB host can now perform USB bulk or isochronous data transfers over the USB bus to the receive FIFO or from the transmit FIFO in the USBN9602. 5. If the FIFO’s warning limit is reached or the transmission/reception is completed, a DMA request/acknowledge sequence is started for the predetermined number of bytes. The time at which a DMA request is issued depends on the selected DMA Mode (controlled by the DMACNTRL.DMOD bit), the current status of the endpoint FIFO, and the FIFO warning enable bits. A DMA request can be issued immediately. 6. After the DMA controller is granted control of the bus, it drives a valid memory address and asserts DACK and RD or WR, thus transferring a byte from the USBN9602 receive FIFO to memory or from memory to the transmit FIFO. This process continues until the DMA byte count, within the DMA controller, reaches zero. 7. After the programmed amount of data is transferred, the firmware needs to do one of the following (depending on the transfer direction and mode): queue the new data for transmission by setting the TXCx.TX_EN bit, set the end-of-packet marker by setting the TXCx.TX_LAST bit, re-enable reception by setting the RXCx.RX_EN bit, or check whether the last byte of the packet was received (RXSx.RX_LAST). The DMA transfer can be halted at any time by resetting the USBN9602 DMA request enable bit. If the USBN9602 DMA request enable bit is cleared during the middle of a DMA cycle, the current cycle is completed before the DMA request is terminated. input DRQ DACK D[7:0] output Figure 9. DMA Read from USBN9602 O bs ol RD 12 www.national.com 8.0 MICROWIRE/PLUS Interface The MICROWIRE/PLUS interface allows the USBN9602 IRE/PLUS mode uses pins called chip select (CS), serial to function as a peripheral of a CPU or microcontroller via clock (SK), serial data in (SI), and serial data out (SO), as a serial interface. This mode is selected by pulling the shown in Figure 10. MODE1 pin high and the MODE0 pin low. The MICROW- 0x00 DATA OUT SK SYNC DATA_OUT CS SO SHIFT REG et e SI DATA IN DATA_IN ADDR ADDRESS ol CMD[1:0] 0x3F REGISTER FILE bs Figure 10. MICROWIRE Interface Block Diagram O The MICROWIRE interface is enabled by a falling edge of CS and reset with a rising edge of CS. Data on SI is shifted in after the rising edge of SK and data is shifted out on SO after the falling edge of SK. Data transfer from and to the shift register is done after the falling edge of the eighth SK clock. Data is transferred with the most significant bit first. Table 1 summarizes the available commands for the MICROWIRE interface. Note: A write operation to any register always reads out the contents of the register after the write occurs and shifts out that data in the next cycle. This read does not clear the bit in the respective register, even for a clear-on-read (“Cor”) type bit. An exception is writing to the TXDx (transmit data) registers, which causes undefined data to be read out during the next cycle. 13 www.national.com 8.0 MICROWIRE/PLUS Interface (Continued) Table 1. MICROWIRE Command/Address Byte Format Byte Transferred CMD Sequence initiated. One cycle equals eight SK clocks. Data is transferred after the eighth SK. clock of one cycle. ADDR 0 5 4 3 2 1 0 0 RADDR (read) 0 1 x 1 0 WADDR (normal write) 1 1 WADDR (burst write) 0 Cycle 1: Shift in CMD/RADDR; shift out previous read data Cycle 2: Shift in next CMD/ADDR; shift out RADDR data Cycle 1: No action; shift out previous read data (does not clear CoR bits) Cycle 1: Shift in CMD/WADDR; shift out previous read data Cycle 2: Shift in WADDR write data; shift out WADDR read data (does not clear CoR bits) Cycle 1: Shift in CMD/WADDR; shift out previous read data Cycle 2-n: Shift in WADDR write data; shift out WADDR read data (does not clear CoR bits); terminate this mode by pulling CS high et e 1 Writing data can be done in standard mode or burst mode. The standard mode requires two bytes: the command and address being shifted in and the data being shifted in. In burst mode, the command and address are transferred first, and then consecutive data is written to that address. The burst mode is terminated by CS going inactive (high). ol Reading the data is done by shifting in the 2-bit command (CMD) and the 5-bit address (RADDR or WADDR) while simultaneously shifting out read data from the previous address. CS O SK bs For the MICROWIRE interface, Figure 11 shows the basic read timing, Figure 12 shows the standard write timing, and Figure 13 shows the write timing in burst mode. SI SO 8 Cycles CMD = 0x ADDR 8 Cycles CMD = 0x ADDR undefined data Read Data 8 Cycles new command Read Data Figure 11. MICROWIRE Interface Basic Read Timing 14 www.national.com 8.0 MICROWIRE/PLUS Interface (Continued) CS SK SI SO 8 Cycles 8 Cycles CMD = 10 ADDR Write Data - undefined data - Read Data 8 Cycles new command Read Data et e Figure 12. MICROWIRE Interface Standard Write Timing SI CMD=11 ADDR - undefined data - 8 Cycles 8 Cycles Write Data Write Data Read Data Read Data O SO 8 Cycles bs SK ol CS Figure 13. MICROWIRE Interface Burst Write Timing 15 www.national.com 9.0 Device Functional States At any given time, the USBN9602 operates in one of the following states: – “NodeReset” the device is reset – “NodeOperational” when the device is operating normally – “NodeSuspend” when the device is suspended due to USB inactivity – “NodeResume” when the device wakes up from the suspended state The Suspend, Resume, or Reset line condition causes a transition from one operating state to another. These conditions are detected by specialized hardware and reported via the Alternate Event (ALTEV) register. If interrupts are enabled, an interrupt is generated upon the occurrence any of the specified condition. USB specifications requires that a device must be ready to respond to USB tokens within 10 ms after wake-up or reset. 9.4 Functional State Transitions Figure 14 is a state diagram showing the device states and transitions. The conditions that trigger each transition are shown in the figure. Conditions that require firmware operation are shown in italics. Note that all USBN9602 state transitions are initiated by the firmware. 9.1 Suspend Operation et e A USB device is expected to enter the Suspend state in response to the Suspend event, which occurs when 3 ms has elapsed without any detectable bus activity. The USBN9602 looks for this event and signals it by setting the ALTEV.SD3 bit, which causes an interrupt to be generated. The firmware should respond by putting the USBN9602 in Suspend state. ol In the Suspend state, the transceiver enters a special lowpower mode. All registered states and FIFO Buffers remain static so that upon resumption of activity, no additional operations are necessary. bs The USBN9602 can resume operation from the Suspend state under firmware control as a response to a local event at the host controller, which can in turn wake up the USB bus via a remote resume operation, or upon detection of a resume command on the USB bus that signals an interrupt to the host controller. 9.2 Remote Resume If the host has enabled remote wake-ups to occur from this node, the USBN9602 can initiate a remote wake-up. O Once the firmware detects the event that is supposed to wake-up the bus, it releases the USBN9602 from the suspend state by initiating a Remote Resume on the USB using the NFSR register. The node firmware must ensure that at least 5 ms of Idle has been present on the USB. While in the Resume state, a constant “K” is signaled on the USB. This should last for at least 1 ms, after which the USB host continues sending the resume signal for at least an additional 20 ms, and then completes the resume operation by issuing the End_Of_Packet (EOP) sequence. To successfully detect the EOP, the firmware has to enter the “NodeOperational” state by setting the NFSR register. Should an End_Of_Packet from the host not be received within 100 ms, the Remote Resume should be initiated again by the software. 9.3 USB Resume Operation Upon detection of resume or reset signal while in the Suspend state, the USBN9602 can signal this to the main controller by generating an interrupt. 16 www.national.com 9.0 Device Functional States (Continued) set_oper NodeOperational 10b suspend_det & set_suspend hw/sw reset reset_det & set_reset NodeReset 00b resume_compl & set_oper resume_det & set_oper NodeResume 01b NodeSuspend 11b local_event & sd5_detect & clear_suspend et e reset_det & set_reset transition initiated by firmware Figure 14. Node Functional State Diagram The following notes apply to the state diagram: When the node is not in the NodeOperational state, all port registers and internal Endpoint states are reset. In the NodeResume state, resume signaling is propagated upstream. In the NodeSuspend state, the node may enter a low-power state and is able to detect resume signaling. 2 describes the individual conditions that trigger state transitions. ol – – – Table Table 2. State Transition Conditions set_reset set_suspend Node Functional State register NFS[1:0] bits are written with 00b. The firmware should only initiate set_reset if ALTEV.RESET is set. Node Functional State register NFS[1:0] bits are written with 11b. The firmware should only initiate set_suspend if ALTEV.SD3 is set. Node Functional State register NFS[1:0] bits are written with 10b. O set_oper Condition Asserted bs State Transition clear_suspend Node Functional State register NFS[1:0] bits are written with 01b. The firmware should only initiate clear_suspend if ALTEV.SD5 is set. reset_det Alternate Event register RESET bit set (ALTEV.RESET = 1). local_event A local event that should wake up the USB. sd5_det Alternate Event register SD5 bit set (ALTEV.SD5 = 1). suspend_det Alternate Event register SD3 bit set (ALTEV.SD3 = 1). resume_det Alternate Event register RESUME bit set (ALTEV.RESUME = 1). resume_compl The node should stay in the NodeResume state for at least 10ms and then must enter the NodeOperational state to detect the EOP from the host, which terminates this remote resume operation. EOP is indicated by ALTEV.EOP = 1. 17 www.national.com 10.0 Endpoint Operation Packets are broadcast from the root hub to all the nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to permit optimal use of microcontroller bandwidth. One function address with seven different endpoint combinations is decoded in parallel. If a match is found, then that particular packet is received into the FIFO; otherwise it is ignored. The incoming USB Packet Address Field and Endpoint Field are extracted from the incoming bit stream. Then the address field is compared to the Function Address Register (FADR) and if a match is detected, the Endpoint Field is compared to all of the Endpoint Control Registers (EPCx) in parallel. A match will then cause the payload data to be received or transmitted using the respective Endpoint FIFO. match FADR Register match receive/transmit FIFO0 EPC0 Reg. transmit FIFO1 et e EPC1 Reg. receive FIFO1 EPC2 Reg. transmit FIFO2 EPC3 Reg. ol receive FIFO2 EPC4 Reg. transmit FIFO3 bs EPC5 Reg. receive FIFO3 O EPC6 Reg. Figure 15. USB Function Address/Endpoint Decoding 10.1 Transmit and Receive Endpoint FIFOs The USBN9602 uses a total of seven Transmit and Receive FIFOs. There is one bidirectional Transmit and Receive FIFO for the mandatory control endpoint zero, plus an additional three transmit and three receive FIFOs, for up to six additional endpoints. As shown in Table 3, the bidirectional FIFO for endpoint zero is 8 bytes deep and the additional unidirectional FIFOs are 32 or 64 bytes deep for both transmit and receive. Each FIFO can be programmed for one exclusive USB endpoint used together with one globally decoded USB function address. The firmware must not have both transmit and receive enabled for endpoint zero at any given time. 18 Table 3. USBN9602 Endpoint FIFO Sizes Endpoint # TX FIFO size (name) 0 RX FIFO size (name) 8 (FIFO0) 1 32 (TXFIFO1) - 2 - 32 (RXFIFO1) 3 32 (TXFIFO2) - 4 - 32 (RXFIFO2) 5 64 (TXFIFO3) - 6 - 64 (RXFIFO3) www.national.com 10.0 Endpoint Operation (Continued) TXC0.FLUSH RXC0.FLUSH Idle RXC0.RX_EN write to TXD0 RxWait TxFill SETUP token TXC0.TX_EN & 0-length pkt. TXC0.TX_EN OUT or SETUP token et e transmission done TxWait FIFO0 empty (all data read) IN token Rx ol Tx Figure 16. Endpoint 0 Operation Note that the actual current operating state is not directly visible to the firmware. O bs If two endpoints in the same direction are programmed with the same endpoint number and both are enabled, then data will be received or transmitted using the endpoint with the lower number until that endpoint gets disabled for BULK or INTERRUPT transfers, or becomes full or empty for ISO transfers. For example, if receive EP2 and receive EP4 both use the endpoint number five and are both isochronous, then the first OUT packet is received into EP2 and the second OUT packet is received into EP4, if there is no firmware interaction in between. For ISO endpoints, this allows implementing a ping-pong buffer scheme together with the frame number match logic. Endpoints in different directions programmed with the same endpoint number still operate independently. A packet written to the FIFO will be transmitted if an IN token for the respective Endpoint is received. If an error condition is detected, the packet data remains in the FIFO and transmission is retried with the next IN token. The FIFO contents can be flushed to allow response to an OUT token or to write new data into the FIFO for the next IN token. If an OUT token is received for the FIFO, the firmware will be informed about data being received to the FIFO only if there was no error condition (CRC or STUFF error). Erroneous receptions are automatically discarded. 10.3 Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2, TXFIFO3) 10.2 Bidirectional Control Endpoint FIFO0 OperaThe Transmit FIFOs for Endpoints 1, 3, and 5 support tion FIFO0 is intended to be used for the bidirectional control endpoint zero. It can be configured to receive data sent to the default address by setting the DEF bit of the EPC0 register. Isochronous transfers are not supported for the control endpoint. Bulk, Interrupt, and Isochronous USB transfers of packets that are greater than the FIFO size. Therefore, the firmware must update the FIFO contents while the USB packet is being transmitted on the bus. Figure 17 illustrates the operation of the transmit FIFOs. The Endpoint 0 FIFO can hold a single receive or transmit packet with up to eight bytes of data. Figure 16 is a state diagram showing the basic operation of the Endpoint 0 FIFO in both the receive and transmit directions. 19 www.national.com 10.0 Endpoint Operation (Continued) FLUSH (resets TXRP and TXWP) TXRP TFxS - 1 0x0 + TFL = TXWP - TXRP + Tx FIFO X TXWP et e + TCOUNT = TXRP - TXWP (= TFxS - TxFL) ol Figure 17. Tx FIFO Operation 10.3.1 TFxS 10.3.4 TxFL Transmit FIFO Level. This value indicates how many bytes not yet transmitted remain in the FIFO before an underrun condition occurs on the next read of the FIFO. bs The diagram labels used in Figure 17 are explained below. Transmit FIFO x Size. This is the total number of bytes available within the FIFO. O A FIFO warning can be issued if TxFL decreases to a specific value. The respective FWEV.TXWARNx bit is set 10.3.2 TXRP if TxFL is equal to or less than the number specified with Transmit Read Pointer. This pointer is incremented every TXCx.TFWL. time the Endpoint controller reads data from the Transmit FIFO. This pointer wraps around to zero if TFxS is 10.3.5 TCOUNT reached. TXRP is never incremented beyond the value of Transmit FIFO Count. This value indicates how many empty bytes are available to be filled within the Transmit the write pointer TXWP. An underrun condition occurs if TXRP equals TXWP and FIFO. This value is accessible by the firmware via the an attempt is made to transmit more bytes with the TX- TXSx Register. Cx.LAST bit not set. 10.3.3 TXWP 10.4 Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) Transmit Write Pointer. This pointer is incremented every The Receive FIFOs for Endpoints 2, 4, and 6 support time the firmware writes to the Transmit FIFO. This pointer Bulk, Interrupt, and Isochronous USB transfers of packets that are greater than the FIFO size. If the packet length wraps around to zero if TFxS is reached. exceeds the FIFO size, the firmware must read the FIFO If the attempt is made to write more bytes to the FIFO contents while the USB packet is being received on the than actual space is available (FIFO overrun), the write to bus. Figure 18 shows the detailed behavior of the Receive the FIFO is ignored. You should therefore check TCOUNT FIFOs. to obtain an indication of the number of empty bytes reThe diagram labels used in Figure 18 are explained bemaining. low. 20 www.national.com 10.0 Endpoint Operation (Continued) FLUSH (resets RXRP and RXWP) RXRP RFxS - 1 0x0 RCOUNT = RXWP - RXRP + + Rx FIFO X RXWP et e + RFL = RXRP - RXWP (= RFxS - RCOUNT) Receive FIFO x Size. This is the total number of bytes available within the FIFO. 10.4.2 RXRP A FIFO warning can be issued if RxFL decreases to a specific value. The respective FWEV.RXWARNx bit is set if RxFL is equal to or less than the number specified with RXCx.RFWL. bs 10.4.1 RFxS ol Figure 18. Rx FIFO Operation O 10.4.5 RCOUNT Receive Read Pointer. This pointer is incremented every time the firmware reads from the Receive FIFO. This Receive FIFO Count. This value indicates how many pointer wraps around to zero if RFxS is reached. RXRP is bytes are available to be read out of the Receive FIFO. This value is accessible by the firmware via the RFSx never incremented beyond the value of RXWP. Register. If the attempt is made to read more bytes than are actually available (FIFO underrun), the last byte is read repeti- 10.5 Programming Model tively. You should therefore check RCOUNT to obtain an Figure 19 illustrates the register hierarchy. It shows the reindication of the number of received bytes remaining. lationship between the endpoint registers and event registers. 10.4.3 RXWP Receive Write Pointer. This pointer is incremented every time the Endpoint controller writes to the Receive FIFO. This pointer wraps around to zero if RFxS is reached. A overrun condition occurs if RXRP equals RXWP and an attempt is made to receive more bytes. 10.4.4 RxFL Receive FIFO Level. This value indicates how many more bytes can be received until an overrun condition occurs with the next write to the FIFO. 21 www.national.com 10.0 Endpoint Operation (Continued) MAEV RXEV FWEV TXEV AEV NAK TXSTA0 et e TXC0 TXFD0 EPC0 RXSTA0 RXC0 FIFO0 8 byte ol RXFD0 O bs TXSTAx TXCx EPCx TFIFOx 16/32 byte TXFDx RXSTAx RXCx xxx EPCy RFIFOy 16/32 byte RXFDx Other user-accessible registers Figure 19. Register Hierarchy 22 www.national.com 11.0 Register Set 11.1.3 NAT The USBN9602 has a set of memory-mapped registers that can be read or written to control the USB interface. Some register bits are reserved. Reading reserved registers bits returns undefined data. Reserved register bits should be always written with zero. The following conventions are used to describe the register format: bit number read/write characteristics: The NAT bit should be set by the firmware only if an external 3.3V supply has been provided to the V3.3 pin, or at least 1 msec after the VGE bit is set (in the latter case the delay allows the internal regulator sufficient time to become stable). r = register bit is read-only 11.1.4 INTOC w = register bit is write-only r/w = register bit is read and written by firmware Interrupt Output Control bits 1 and 0. These bits control the Interrupt Output pin characteristics according to the following table. CoR = register bit is cleared if read Table 4. INTOC Bit Definition bit or field name (res = reserved) HW = register bit can be modified by device and firmware 11.1 Main Control Register (MCNTRL) 0 0 r/w 11.1.1 SRST bit 3 bit 2 bit 1 res NAT VGE res – 0 – r/w 1 0 0 0 Disabled (active-high, open drain) bit 0 0 1 active-low open drain SRST 1 0 active-high push-pull 0 – 0 r/w – r/w 1 O 1 active-low push-pull 11.2 Clock Configuration Register (CCONF) Software Reset. Setting this bit causes a software reset of the device. This reset is equivalent to a hardware reset except that the clock configuration register is unaffected. Note that the software reset bit clears itself at the end of the initiated reset operation. 11.1.2 VGE Interrupt Output ol INTOC[1:0] bit 5 bit 4 INTOC bs bit 6 et e reset value bit 7 Node Attached. This bit, when set, indicates that this node is ready to be detected as attached to the USB. When reset, the transceiver forces SE0 on the USB port to prevent the Hub (to which this node is connected) from detecting an attach event. After reset, this bit is left cleared to allow the device time before having to respond to commands. After this bit is set, the device no longer drives the USB and should be ready to receive Reset signaling form the hub. bit 7 bit 6 bit 5 CODIS res 0 – r/w – bit 4 bit 3 bit 2 bit 1 bit 0 CLKDIV[3:0] 1 0 1 1 r/w 11.2.1 CLKDIV Voltage Regulator Enable. Setting this bit enables the internal 3.3V voltage regulator. This bit is hardware reset to 0, disabling the internal 3.3V regulator by default. When the internal 3.3V regulator is disabled, the device is effectively disconnected from the USB. Upon power-up, the firmware may perform any needed initialization (such as power-on self test) and then set the VGE bit. Until the VGE bit is set, the upstream hub port will not detect the presence of the device. External clock divisor. The value in this field sets the clock frequency at the CLKOUT output pin as follows: frequency = 48 MHz / (CLKDIV+1) A hardware reset configures the divisor to 11 decimal which yields a 4 MHz output clock. If the CLKDIV value is changed by the firmware, the clock output period is expanded or shortened in its current phase for glitch-free switching. If the VGE bit is reset, an external 3.3V power supply may 11.2.2 CODIS be used on the V3.3 pin. Clock Output Disable. Setting this bit disables the clock output. When this bit is set, the CLKOUT output pin is frozen in its current state. 23 www.national.com 11.0 Register Set (Continued) DMA requests from a receive endpoint remains activated until the request condition goes away. If DMOD is cleared to 0, DMA requests will be issued until the firmware reads the respective receive status register (RXSx) and thus resets the RX_LAST bit, or if the endpoint FIFO becomes empty due to sufficient reads. If DMOD is set to 1, DMA requests will be issued until the FIFO warning condition goes away, or the FIFO is flushed. 11.3 DMA Control Register (DMACNTRL) bit 7 bit 6 bit 5 bit 4 bit 3 DEN res DMOD 0 – 0 r/w – r/w bit 2 bit 1 bit 0 DSRC[2:0] 0 0 0 r/w 11.3.1 DSRC DMA Source. The DMA source bit field holds the binary encoded value that specifies which one of Endpoints 1 to 6 is enabled for DMA support. The DSRC bits are cleared upon reset. Table 5 summarizes the DSRC bit settings. Table 5. DSRC Bit Description 11.3.3 DEN Endpoint # 1 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 x DMA Enable. This bit enables the DMA support mode when set. If this bit is reset and the current DMA cycle is completed or not yet issued, the DMA transfer is terminated. When the USBN9602 operates is in the MICROWIRE interface mode, DMA operation cannot be enabled and setting this bit does not have any effect. 11.4 Revision Identifier Register (RID) bit 7 bit 6 bit 5 bit 4 – reserved – 11.3.2 DMOD bit 3 reserved ol 2 et e DSRC If DMOD is cleared to 0 (and the endpoint and DMA are enabled), DMA requests will be issued until the firmware reads the respective transmit/receive status register (TXCx or RXCx) and thus resets the TX_DONE/RX_LAST bit. If DMOD is set to 1 (and the endpoint and DMA are enabled), DMA requests will be issued until the FIFO warning condition goes away. bit 1 bit 0 REVID[3:0] 0 0 0 r 11.4.1 REVID bs DMA Mode. This bit specifies the time at which a DMA request is issued. 0 bit 2 O This register holds the binary encoded chip revision. For If the DMOD bit is 0, a DMA request is issued upon trans- this revision it holds 0001b. fer completion. For transmit endpoints EP1, EP3, and 11.5 Node Functional State Register (NFSR) EP5, this is the time at which the data is completely transferred as indicated by the TX_DONE bit. For receive Endbit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 points EP2, EP4, and EP6, this is the time at which the res NFS[1:0] data is completely transferred as indicated by the RX_LAST bit. If the DMOD bit is 1, a DMA request is is– 0 0 sued when the respective FIFO warning bit is set. – r/w A DMA request from a transmit endpoint remains activated until the request condition goes away. If DMOD is cleared to 0, DMA requests will be issued until the firm- 11.5.1 NFS ware reads the respective transmit status register (TXSx) Node Functional State bits. The firmware should initiate all and thus resets the TX_DONE bit, or if the TX- required state transitions according to the respective staCx.TX_LAST bit in the transmit command register gets set tus bits in the Alternate Event register. The valid transiby the firmware. If DMOD is set to 1, DMA requests will tions are shown in the “Node Functional State Diagram” be issued until the FIFO warning condition goes away as on page 17. The NFS bits set the node state as follows: a result of sufficient bytes being transferred to the end- NFS[1:0] = 00 : NodeReset point, or if the TX_DONE bit get set as a result of a transNFS[1:0] = 01 : NodeResume mission. NFS[1:0] = 10 : NodeOperational NFS[1:0] = 11 : NodeSuspend 24 www.national.com 11.0 Register Set (Continued) “NodeReset” is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all Endpoint Pipes are disabled. EPC0.DEF and FAR.AD_EN should be cleared by the software upon entry into this state. Upon exit from this state, EPC0.DEF should be set so that the device responds to the default address. “NodeResume” is the state in which Resume “K” signalling is generated. The firmware should cause a transition to this state to initiate a remote wake-up sequence by the device. The node must remain in this state for at least 1 ms and no more than 15 ms. “NodeOperational” is the normal operational state. In this state the node is configured for operation on the USB. 11.6 Main Event Register (MAEV) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 NAK Handshake. This bit is set if one of the unmasked NAK Event register bits has been set. This bit is cleared when the NAK Event register is read. 11.6.6 ULD Unlock Locked Detected. If set, this bit indicates that the Frame Timer has entered the unlocked state from a locked condition, or has re-entered the locked condition from an unlocked condition, as determined by the Unlocked Status bit (FN.UL) being currently set. This bit is cleared when the register is read. 11.6.7 RX_EV Receive Event. This bit is set if any of the unmasked bits in the Receive Event register are set. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared when all of the RX_LAST bits in each of the receive status registers and all of the RXOVRRN bits in the receive event register are cleared. et e “NodeSuspend” is the device inactive state. The firmware should cause a transition to this state upon detection of a Suspend event while in the NodeOperational state. While in the NodeSuspend state, the transceivers operate in their low-power suspend mode. All Endpoint Controllers and internal states remain frozen. Upon detection of bus activity, the ALTEV.RESUME bit is set. In response, software can cause an entry to the NodeOperational state. 11.6.5 NAK 11.6.8 INTR Master Interrupt Enable. This bit is hard-wired to zero in the Main Event register. However, the corresponding bit in the Main Mask register is the master interrupt enable. 11.7 Main Mask Register (MAMSK) bit 0 bit 7 INTR RX_EV ULD NAK FRAME TX_EV ALT WARN 0 0 0 see text r CoR r CoR 11.6.1 WARN 0 0 r r bit 3 bit 2 bit 1 bit 0 INTR RX_EV ULD NAK FRAME TX_EV ALT WARN 0 ol 0 bit 5 bit 4 0 r 0 0 0 0 0 0 0 r/w bs 0 bit 6 A bit is set to 1 in the Main Mask register enables generFIFO Warning. One of the unmasked bits in the FIFO ation of an interrupt on the occurrence of the respective Warning Event register has been set. The WARN bit is event in the Main Event register. Interrupt generation is cleared by reading the FIFO Warning Event Register. disabled otherwise. For information on the individual interrupt events, see the description of the Main Event register. 11.6.2 ALT O Alternate Event. One of the unmasked bits in the Alter- 11.8 Alternate Event Register (ALTEV) nate Event register has been set. The ALT bit is cleared bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 when the Alternate Event register is read. RESUME RESET SD5 SD3 EOP 11.6.3 TX_EV Transmit Event. This bit is set if any of the unmasked bits in the Transmit Event register (TXFIFOx or TXUNDRNx) are set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status register are cleared. 0 0 CoR CoR 0 0 0 CoR CoR CoR res – – 11.8.1 SD3 Suspend Detect 3 ms. This bit is set after 3 milliseconds of idle time is detected on the upstream port, indicating that the device should be suspended. The suspend ocFrame event. This bit is set if the frame counter is updated curs under firmware control by writing the SUSPEND valwith a new value. This can be due to a valid SOF packet ue to the NFS register. The SD3 bit is cleared when the being received on the USB or due to an artificial update if register is read. the frame counter was unlocked or a frame was missed. This bit is cleared when the register is read. 11.6.4 FRAME 25 www.national.com 11.0 Register Set (Continued) 11.8.2 SD5 11.10 Transmit Event Register (TXEV) Suspend Detect 5 ms. This bit is set after 5 milliseconds of idle time is detected on the upstream port, indicating that this device is now permitted to perform a remote wake-up operation. The resume operation may be initiated under firmware control by writing the RESUME value to the NFS register. The SD5 bit is cleared when the register is read. bit 7 bit 6 bit 5 TXFI FO3 TXFI FO2 TXFI FIFO TXFIF TXFIF TXFIF FO1 0 O3 O2 O1 11.8.4 RESUME 0 0 0 r bit 2 bit 1 bit 0 FIF O0 TXFIFO[3:0] 0 0 0 see text 0 0 r 11.10.1 TXFIFO Transmit FIFO. These bits are copies of the TX_DONE bits from the corresponding Transmit Status registers. The bits are set when the IN transaction for the corresponding transmit endpoint is completed. The bits are cleared when the corresponding Transmit Status register is read. 11.10.2 TXUDRRN et e Resume. This bit is set when resume signaling is detected on the USB while this device is in the Suspend state (NFSR.NFS = 11), indicating that this device should begin its wake-up sequence and enter the operational state. The RESUME bit is cleared when the register is read. bit 3 TXUDRRN[3:0] 11.8.3 RESET Reset. This bit is set when 2.5 µsec of SEO is detected on the upstream port. In response, the functional state bits (NFSR.NFS) should be written with 00 to reset the device, and the device should remain in the reset state for at least 100 µsec. After being reset, the functional state may be returned to the operational state. The RESET bit is cleared when the register is read. bit 4 ol Transmit Underrun. These bits are copies of the respective TX_URUN bits from the corresponding Transmit Status registers. Whenever any of the Transmit FIFOs underflow, the respective TXUDRRN bit is set. These bits 11.8.5 EOP are cleared when the corresponding FIFOx Transmit StaEnd of Packet. This bit is set when a valid End of Packet tus register is read. sequence is detected on the USB. This bit is used when As Endpoint 0 implements a store and forward principle, this device has initiated a Remote wake-up sequence to an underrun condition for FIFO0 cannot occur. Thus, the indicate that the resume sequence has been acknowl- TXUDRRN0 bit is always zero. edged and completed by the host. The EOP bit is cleared 11.11 Transmit Mask Register (TXMSK) when the register is read. 11.9 Alternate Mask Register (ALTMSK) bs bit 7 bit 6 0 0 0 0 res res bit 6 bit 5 bit 4 bit 3 TXUDRRN[3:0] bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RESUME RESET SD5 SD3 EOP 0 bit 7 0 0 0 bit 2 bit 1 bit 0 TXFIFO[3:0] 0 0 0 0 0 r/w r/w O A bit is set to 1 in the Transmit Mask register enables automatic setting of the MAEV.TX_EV bit in the Main Event A bit is set to 1 in the Alternate Mask register enables au- register on the occurrence of the respective event in the tomatic setting of the MAEV.ALT bit in the Main Event reg- Transmit Event register. Setting of the MAVE.TX_EV bit is ister on the occurrence of the respective event in the disabled otherwise. For information on the individual transAlternate Event register. Setting of the MAVE.ALT bit is mit events, see the description of the Transmit Event regdisabled otherwise. For information on the individual alter- ister. nate events, see the description of the Alternate Event register. 26 www.national.com 11.0 Register Set (Continued) 11.12 Receive Event Register (RXEV) bit 7 bit 6 bit 5 bit 4 bit 3 11.14 NAK Event Register (NAKEV) bit 2 bit 1 bit 0 bit 7 RXFIFO3 RXFIFO2 RXFIFO1 FIFO0 RXFIFO3 RXFIFO2 RXFIFO1 FIFO0 RXOVRRN[3:0] 0 0 0 0 0 CoR 0 0 bit 5 bit 4 bit 3 OUT[3:0] RXFIFO[3:0] 0 bit 6 0 0 bit 2 bit 1 bit 0 IN[3:0] 0 0 0 0 CoR 0 0 CoR r 11.14.1 IN 11.12.1 RXFIFO Receive FIFO. This bit is set whenever either RX_ERR or RX_LAST in the respective Receive Status register is set. Reading the corresponding Receive Status register automatically clears this bit. 11.14.2 OUT Out Token NAK. This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (FAR.AD_EN = 1 and EPCx.EP_EN = 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. This bit is cleared when the register is read. et e The USBN9602 implementation discards all packets for Endpoint 0 received with errors. This is necessary, in the case of retransmission due to media errors, to ensure that a good copy of a SETUP packet is captured. Otherwise, the FIFO could be tied up holding corrupted data and unable to receive a retransmission of the same packet. Therefore, the RXFIFO0 bit only reflects the value of RX_LAST (and not RX_ERR) for endpoint 0. In Token NAK. This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (FAR.AD_EN = 1 and EPCx.EP_EN = 1) in response to an IN token. This bit is cleared when the register is read. 11.15 NAK Mask Register (NAKMSK) bit 7 If data streaming is used for the receive endpoints (EP2, EP4, and EP6), the firmware needs to check with the respective RX_ERR bits to ensure that the packets received are not corrupted by errors. Receive Overrun. This bit is set in the event of a FIFO overrun condition. This bit is cleared when the register is read. bit 5 bit 4 bit 3 RXOVRRN[3:0] 0 0 0 bit 4 bit 2 bit 1 bit 0 RXFIFO[3:0] 0 0 0 0 bit 3 OUT[3:0] 0 0 0 0 0 bit 2 bit 1 bit 0 IN[3:0] 0 0 0 r/w A bit is set to 1 in the NAK Mask register enables automatic setting of the MAEV.NAK bit in the Main Event register on the occurrence of the respective event in the NAK Event register. Setting of the MAEV.NAK bit is disabled otherwise. For information on the individual NAK events, see the description of the NAK Event register. bs 11.13 Receive Mask Register (RXMSK) bit 6 bit 5 ol 11.12.2 RXOVRRN bit 7 bit 6 11.16 FIFO Warning Event Register (FWEV) 0 O r/w bit 7 bit 6 bit 5 RXFIFO3 RXFIFO2 RXFIFO1 bit 4 res bit 3 bit 2 bit 1 TXFIFO3 TXFIFO2 TXFIFO1 bit 0 res A bit is set to 1 in the Receive Mask register enables auRXWARN[3:1] res TXWARN[3:1] res tomatic setting of the MAEV.RX_EV bit in the Main Event 0 0 0 – 0 0 0 – register on the occurrence of the respective event in the Receive Event register. Setting of the MAVE.RX_EV bit is r – r – disabled otherwise. For information on the individual receive events, see the description of the Receive Event 11.16.1 TXWARN register. Transmit FIFO Warning. This bit is set to 1 when the respective Transmit Endpoint FIFO reaches the warning limit as specified by the TFWL bits of the respective Transmit Command register and transmission from the respective endpoint is enabled. This bit is cleared when the warning condition is cleared by writing new data to the FIFO, by flushing the FIFO, or when the transmission is done as indicated by the TX_DONE bit within the Transmit Status register. 27 www.national.com 11.0 Register Set (Continued) 11.16.2 RXWARN 11.18.3 MF Receive FIFO Warning. This bit is set to 1 when the respective Receive Endpoint FIFO reaches the warning limit as specified by the RFWL bits of the respective Receive Command register. This bit is cleared when the warning condition is cleared by reading data from the FIFO or by flushing the FIFO. Missed SOF Flag. This bit is set to indicate a discontinuity in the Frame Number. It is set when the frame number in a valid received SOF does not match the expected next value. The flag is also set when an SOF is not received within 12060 bit times. Upon reset, this flag is set to 1. 11.17 FIFO Warning Mask Register (FWMSK) bit 0 Reset Frame Count. Setting this bit resets the Frame Number to 0x000 and then clears itself (the RFC bit) to zero. This bit always reads back as zero. 11.19 Frame Number Low Byte Register (FNL) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 RXFIFO3 RXFIFO2 RXFIFO1 res TXFIFO3 TXFIFO2 TXFIFO1 res RXWARN[3:1] res TXWARN[3:1] res 0 0 0 0 0 0 0 11.18.4 RFC bit 7 0 11.18 Frame Number High Byte Register (FNH) bit 5 bit 3 MF UL RFC reserved 1 1 0 – r r w/r0 – bit 2 bit 1 0 0 bit 2 bit 1 bit 0 0 0 0 0 0 bit 0 The Frame Number Low Byte register (FNL) holds the low-order byte of the Frame Number (see the description of the Frame Number High Byte register (FNH). The correct sequence to read the frame number is FNL first, then FNH. Reading from the FNL register locks the three highorder bits in the FNH register, ensuring a match between the low-order and high-order bits. 11.20 Function Address Register (FAR) FN[10:8] bit 7 0 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 AD_EN AD[6:0] r bs 11.18.1 FN bit 3 r ol bit 6 bit 4 et e A bit is set to 1 in the FIFO Warning Mask register enables automatic setting of the MAEV.WARN bit in the Main Event register on the occurrence of the respective event in the FIFO Warning Event register. Setting of the MAVE.WARN bit is disabled otherwise. For information on the individual FIFO warning events, see the description of the FIFO Warning Event register. bit 7 bit 5 FN[7:0] r/w bit 4 bit 6 0 O Frame Number. This field contains the highest-order bits of the current frame number, as received in the last SOF packet. If a valid frame number is not received within 12060 bit times (FLMAX with tolerance) of the previous change, the frame number is incremented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next frame number from a valid SOF packet. The low-order byte of the frame number is contained in the Frame Number Low Byte register (FNL). The correct sequence to read the frame number is FNL first, then FNH. Reading from the FNL register locks the three highorder bits in the FNH register, ensuring a match between the low-order and high-order bits. 11.18.2 UL Unlocked Flag. This bit is set to indicate that at least two frames were received without an expected frame number or that no valid SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN. Upon reset, this flag is set to 1. 0 0 r/w 0 0 0 r/w The Function Address register (FAR) sets the function address for the device. The different Endpoint numbers are set for each endpoint individually via the Endpoint Control registers. 11.20.1 AD Address. This field holds the 7-bit function address. The function address is used for transmission and reception of all tokens addressed to the device. 11.20.2 AD_EN Address Enable. When set to 1, the bits AD[6:0] are used in address comparison. See “Endpoint Operation” on page 18 for details. When cleared, the device does not respond to any token on the USB bus. Note: If the DEF bit in the Endpoint Control Register 0 is set, Endpoint zero responds to the default address. 28 www.national.com 11.0 Register Set (Continued) 11.22 Transmit Status Register 0 (TXS0) 11.21 Endpoint Control Register 0 (EPC0) bit 7 bit 6 bit 5 bit 4 STALL DEF res 0 0 – r/w r/w – bit 3 bit 2 bit 1 bit 7 bit 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res ACK_STAT TX_DONE EP[3:0] 0 bit 6 0 0 r; hardwired to 0 – 0 0 – CoR CoR TCOUNT[4:0] 0 0 0 0 0 r This register controls the mandatory control endpoint zero. 11.22.1 TCOUNT 11.21.1 EP Transmit FIFO Count. This field indicates the count of empty bytes available in the FIFO. The value in this field is never larger than eight for Endpoint zero. Endpoint Address. This field holds the 4-bit endpoint address. For Endpoint 0, these bits are hard-wired to 0000b. 11.21.2 DEF Transmit Done. This bit, when set, indicates that a transmission of a packet has been completed. This bit is cleared when the register is read. 11.22.3 ACK_STAT Acknowledge Status. This bit indicates the acknowledge status (from the host) regarding the ACK for the previously sent packet. This bit is to be interpreted when TX_DONE is set to 1. This bit itself is set when an ACK is received; otherwise it remains cleared. This bit is also cleared when the register is read. et e Default Address. When this bit is set, the device responds to the default address, regardless of the contents of the FAR[6:0] and EP0[3:0] fields. When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared. 11.22.2 TX_DONE 11.23 Transmit Command Register 0 (TXC0) bit 7 bit 6 bit 5 ol This bit is used in the transition from the default address to an assigned address. The transition from the default address 00000000000b to an address assigned during bus enumeration cannot occur in the middle of the SET_ADDRESS control sequence, in order to allow completion of the control sequence. However, the address needs to be changed immediately upon completion of the SET_ADDRESS control sequence to avoid errors in the case that another control sequence immediately follows the SET_ADDRESS command. bit 3 bit 2 IGN_IN FLUSH TOGGLE bit 1 bit 0 res TX_EN – 0 0 0 – 0 – r/w r/w HW r/w – r/w HW bs Upon USB-Reset, the firmware has 10 mS to set things up and should write 0x80 to the Function Address Register (FAR) and 0x00 to Endpoint Control Register 0 (EPC0). At SET_ADDRESS, the firmware must write 0x40 to EPC0. Then write the assigned function address, logically ORed with 0x80, to FAR. Then queue a zero-length IN packet to complete the status phase of the SET_ADDRESS control sequence. res bit 4 11.23.1 TX_EN O Transmit Enable. This bit must be set by the firmware to start a packet transmission. It is cleared by the chip after transmitting a single packet or a STALL handshake in reNote that if a SET_ADDRESS control sequence occurs sponse to an IN token. Note that the RX_EN bit in the Rewhen the current function address is not the default, then ceive Command Register 0 takes precedence over this bit. the mechanism described above does not work. The firm- In other words, as long as the RX_EN bit is set, the ware must not set the DEF bit in this case, and must not TX_EN bit is ignored. update the FAR register until the SET_ADDRESS control A zero-length packet is indicated by setting this bit without writing any data into the FIFO. sequence completes (including all handshakes). 11.23.2 TOGGLE 11.21.3 STALL Stall Handshake. Setting this bit causes the chip to gener- Data Toggle. This bit specifies the type of PID used for ate a STALL handshake under either of the following con- transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID ditions: to be generated. This bit is not altered by the hardware. – The transmit FIFO is enabled and an IN token is received. – The receive FIFO is enabled and an OUT token is received. Note that setting this bit does not cause a STALL handshake to be generated in response to a SETUP token. 11.23.3 FLUSH Flush FIFO. Writing a 1 to this bit flushes all data from the control endpoint FIFO, resets the Endpoint to IDLE, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on Upon transmitting the STALL handshake, the RX_LAST or the USB, flushing is delayed until after the transfer is TX_DONE bit is set in the respective Receive Status or done. This bit is cleared on reset. This bit and the RXC0.FLUSH bit are equivalent. Transmit Status register. 29 www.national.com 11.0 Register Set (Continued) 11.25.4 SETUP 11.23.4 IGN_IN Ignore IN Tokens. When this bit is set, the endpoint ig- Setup Packet. When set, this bit indicates that a setup packet has been received. This bit is left unchanged on nores any IN tokens directed to its configured address. zero-length packets. It is cleared when the register is 11.24 Transmit Data Register 0 (TXD0) read. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 11.26 Receive Command Register 0 (RXC0) bit 0 TXFD bit 7 bit 6 bit 5 bit 4 bit 3 don’t care res w – 0 – r/w HW 11.24.1 TXFD Transmit FIFO Data Byte. See “Bidirectional Control Endpoint FIFO0 Operation” on page 19 for a description of this type of data handling. bit 2 bit 1 bit 0 IGN_OUT RX_EN 0 0 0 r/w r/w r/w FLUSH IGN_SETUP 11.26.1 RX_EN Receive Enable. Out packet reception is disabled after the reception of every data packet or when a STALL handshake is returned in response to an OUT token. A 1 must be written to this bit to re-enable data reception. Recep11.25 Receive Status Register 0 (RXS0) tion of SETUP packets is always enabled. In the case of bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other inres SETUP TOGGLE RX_LAST RCOUNT[3:0] tervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and return an ACK – 0 0 0 0 0 0 0 handshake. If any other reasons prevent the Endpoint – CoR CoR CoR r Controller from accepting the SETUP packet, it must not generate a handshake. This allows recovery from a condiThis is the receive status register for the bidirectional con- tion where the ACK of the first SETUP token is lost by the trol endpoint zero. To allow the reception of a SETUP host. packet after the reception of a zero-length OUT/SETUP 11.26.2 IGN_OUT packet, two copies of this register exist in hardware: one to hold the receive status of a zero-length packet and an- Ignore OUT Tokens. When this bit is set, the endpoint igother to hold the status of the following SETUP packet nores any OUT tokens directed to its configured address. with data. If a zero-length packet is followed by a SETUP 11.26.3 IGN_SETUP packet, the first read of this register indicates the status of Ignore SETUP Tokens. When this bit is se.t the endpoint the zero-length packet (with RX_LAST set and RCOUNT ignores any SETUP tokens directed to its configured adcleared to zero) and the second read indicates the status dress. of the SETUP packet. 11.26.4 FLUSH 11.25.1 RCOUNT Flush FIFO. Writing a 1 to this bit flushes all data from the Receive FIFO Count. This field indicates the count of control endpoint FIFO, resets the Endpoint to IDLE, clears bytes presently in the RX FIFO. The value in this field is the FIFO read and write pointers, and then clears itself. If never larger than eight for endpoint zero. the endpoint is currently using the FIFO0 to transfer data 11.25.2 RX_LAST on the USB, flushing is delayed until after the transfer is Receive Last. This bit, when set, indicates that the done. This bit is cleared on reset. This bit and the RCOUNT field reflects the number of bytes remaining of TXC0.FLUSH bit are equivalent. the packet. This bit is left unchanged on zero-length packets. This bit is cleared when the register is read. O bs ol et e The firmware is expected to write only the packet payload data. The PID and CRC16 are created automatically. 11.25.3 TOGGLE Data Toggle. When set, this bit indicates that the last successfully received packet was received with a DATA1 PID. This bit is cleared if the last successfully received packet had a DATA0 PID. This bit is left unchanged on zerolength packets. This bit is also cleared by reading the Receive Status Register 0. 30 www.national.com 11.0 Register Set (Continued) – The receive FIFO is enabled and an OUT token is received. Note that setting this bit does not cause a STALL handshake to be generated in response to a SETUP token. 11.27 Receive Data Register 0 (RXD0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RXFD 11.29 Transmit Status Register x (TXS1, TXS2, TXS3) don’t care r bit 7 11.27.1 RXFD bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TX_URUN ACK_STAT TX_DONE Receive FIFO Data Byte. See “Bidirectional Control Endpoint FIFO0 Operation” on page 19 for a description of this type of data handling. 0 0 0 CoR CoR CoR TCOUNT[4:0] 0 0 0 0 0 r The firmware should expect to read only the packet payload data. The PID and CRC16 are removed from the in- The Transmit Status Registers TXS1, TXS2, and TXS3 report on the status of Transmit Endpoint FIFOs 2, 4, and 6, coming data stream automatically. respectively. The three registers follow the format shown 11.28 Endpoint Control Register x (EPC1 through above. EPC6) bit 6 bit 5 bit 4 STALL res ISO EP_EN 0 – 0 0 r/w – r/w r/w bit 3 bit 2 bit 1 EP[3:0] 0 et e 11.29.1 TCOUNT bit 7 0 0 r/w bit 0 Transmit FIFO Count. This field indicates the count of empty bytes available in the FIFO. If this count is greater than 31, a value of 31 is reported. 0 11.29.2 TX_DONE 11.28.1 EP bs Endpoint Address. This field holds the 4-bit endpoint address. 11.28.2 EP_EN – A data packet has completed transmission in response to an IN token with non-ISO operation. – The endpoint sent a STALL handshake in response to an IN token – A scheduled ISO frame was transmitted or discarded. This bit is cleared when the register is read. If this bit is set, the TXCx.TX_EN bit is prevented from being set. ol The six Endpoint Control Registers EPC1 through EPC6 control the configuration of unidirectional endpoints 1 through 6, respectively. Each register follows the format shown above. Transmit Done. This bit, when set, indicates that the endpoint responded to a USB packet. There are three conditions which can cause this bit to be set: O Endpoint Enable. When this bit is set, the bits EP[3:0] are used in address comparison together with the bits FAR.AD[6:0]. See “Endpoint Operation” on page 18 for details. When the EP_EN bit is cleared, the endpoint does not respond to any token on the USB bus. Note: The FAR.AD_EN bit is the global address compare enable for the USBN9602. If this bit is cleared, the device does not respond to any address, regardless of EP_EN bit. 11.29.3 ACK_STAT Acknowledge Status. This bit is to be interpreted when TX_DONE is set. This bit has two functions: one for ISO mode (EPCx.ISO is set) and one for non-ISO mode (EPCx.ISO is reset). For non-ISO operation, this bit indicates the acknowledge status (from the host) regarding the ACK for the previously sent packet. This bit itself is set when an ACK is received; otherwise it is cleared. For ISO operation, this bit is set if a frame number LSB match occurs and data was sent in response to an IN toIsochronous Endpoint. When this bit is set to 1, the Endken. (For details, see the description of the IGN_ISOMSK point is isochronous. This implies that no NAK is sent if the Endpoint is enabled but not ready. In other words, if bit in the Transmit Command Register.) Otherwise, this bit an IN token is received and no data is available within the is reset, the FIFO is flushed, and TX_DONE is set. FIFO to transmit or if an OUT token is received and the The ACK_STAT bit is also cleared when the register is FIFO is full, as there is no USB handshake for isochro- read. nous transfers. 11.29.4 TX_URUN 11.28.3 ISO 11.28.4 STALL Transmit FIFO Underrun. This bit is set during a transmisStall Handshake. Setting this bit causes the chip to gener- sion if the transmit FIFO becomes empty and no new data ate a STALL handshake under either of the following con- is written to the FIFO. The Media Access Controller (MAC) forces a bit stuff error followed by an EOP in this case. ditions: The TX_URUN bit is reset when the register is read. – The transmit FIFO is enabled and an IN token is received. 31 www.national.com 11.0 Register Set (Continued) 11.30.5 TFWL 11.30 Transmit Command Register x (TXC1, TXC2, TXC3) bit 7 IGN_ISOMSK bit 6 bit 5 bit 4 bit 3 TFWL[1:0] 0 0 r/w 0 r/w res bit 2 bit 1 bit 0 FLUSH TOGGLE LAST TX_EN – 0 0 0 0 – r/w HW r/w r/w HW r/w HW The Transmit Command Registers TXC1, TXC2, and TXC3 allow control of Transmit Endpoint FIFOs 2, 4, and 6, respectively. The three registers follow the format shown above. Transmit FIFO Warning Limit. These bits specify how many more bytes can be transmitted from the corresponding FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal or less than the selected warning limit, the WARN bit within the FIFO Warning Event Register (FWEV.TXFW[x]) is set. To avoid interrupts caused by setting the TXFW[x] bit while the FIFO is filled before a transmission is started, the TXFWL[x] bit is only set when transmission from the endpoint is enabled (TXC[x].TX_EN is set). See Table 6. Table 6. Transmit FIFO Warning Limits TFWL[1:0] Transmit WARN Condition 0 0 Disable WARN warning bit for transmit FIFOs Transmit Enable. This bit must be set by the firmware to start a packet transmission. It is cleared by the chip after transmitting a single packet or a STALL handshake in response to an IN token. If the TXSx.TX_DONE bit is set, this bit is prevented from being set. 0 1 ≤ 4 bytes left in FIFO to transmit 1 0 ≤ 8 bytes left in FIFO to transmit 1 1 ≤ 16 bytes left in FIFO to transmit et e 11.30.1 TX_EN 11.30.2 LAST 11.30.6 IGN_ISOMSK Ignore ISO mask. This bit only has an effect if the endpoint is set to be isochronous. If set, this bit disables locking to specific frame numbers with the alternate function of the TOGGLE bit. Thus, data is transmitted upon reception of the next IN token. If IGN_ISOMSK is cleared, data is only transmitted when FNL[0] matches TOGGLE. ol Last Byte. Setting this bit indicates to the chip that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO during the actual transmission. If the LAST bit is not set and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. A zero-length packet is indicated by setting this bit without writing any data into the FIFO. 11.30.3 TOGGLE bs The transmit state machine transmits the payload data, CRC16, and EOP signal, and then clears the LAST bit. 11.31 Transmit Data Register x (TXD1, TXD2, TXD3) Data Toggle. This bit has two functions: one for the ISO mode (EPCx.ISO bit set) and one for the non-ISO mode (EPCx.ISO bit cleared). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TXFD don’t care O w For non-ISO operation, the bit specifies the type of PID used for transmitting the packet. A value of 0 causes a The Transmit Data Registers TXD1, TXD2, and TXD3 DATA0 PID to be generated, while a value of 1 causes a hold data for Transmit Endpoint FIFOs 2, 4, and 6, respecDATA1 PID to be generated. tively. The three registers follow the format shown above. For ISO mode of operation, this bit and the least signifi- 11.31.1 TXFD cant bit of the frame counter (FNL[0]) act as a mask for Transmit FIFO Data Byte. See “Transmit Endpoint FIFO the TX_EN bit to allow pre-queueing of packets to specific Operation (TXFIFO1, TXFIFO2, TXFIFO3)” on page 19 for frame numbers. In other words, transmission in ISO mode a description of Endpoint FIFO data handling. is only enabled if FNL[0] = TOGGLE. If an IN token is not received while this condition is true, the contents of the The firmware is expected to write only the packet payload FIFO are flushed with the next SOF. If the endpoint is set data. The PID and CRC16 are inserted automatically in the transmitted data stream. to ISO, data is always transferred with a DATA0 PID. This bit is not altered by the hardware. 11.30.4 FLUSH Flush FIFO. Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the Endpoint to IDLE, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data flushing is delayed until after the transmission is done. 32 www.national.com 11.0 Register Set (Continued) 11.32 Receive Status Register x (RXS1, RXS2, RXS3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RX_ERR SETUP TOGGLE RX_LAST 0 0 0 0 CoR CoR CoR HW CoR 11.33 Receive Command Register x (RXC1, RXC2, RXC3) bit 7 bit 6 bit 5 bit 4 RCOUNT[3:0] 0 0 0 bit 3 bit 2 bit 1 bit 0 res RFWL[1:0] res FLUSH IGN_SETUP res RX_EN 0 – r 0 0 – r/w – 0 0 – 0 – r/w r/w – r/w 11.32.2 RX_LAST ol et e The Receive Command Registers RXC1, RXC2, and The Receive Status Registers RXS1, RXS2, and RXS3 RXC3 allow control over Receive Endpoint FIFOs 2, 4, report the status of Receive Endpoint FIFOs 2, 4, and 6, and 6, respectively. The three registers follow the format respectively. The three registers follow the format shown shown above. above. 11.33.1 RX_EN To allow the reception of a SETUP packet after the recepReceive Enable. Out packet reception is disabled after the tion of a zero-length OUT/SETUP package, two copies of reception of every data packet or when a STALL handthis register exist in hardware: one to hold the receive stashake is returned in response to an OUT token. The tus of a zero-length package and another to hold the staRX_EN bit must be set to re-enable data reception. Retus of the following SETUP packet with data. If a zeroception of SETUP packets is always enabled. In the case length package is followed by a SETUP package, the first of back-to-back SETUP packets (for a given endpoint) read of this register indicates the status of the zero-length where a valid SETUP packet has been received with no package and the second read indicates the status of the other intervening non-SETUP tokens, the receive state SETUP package. machine discards the new SETUP packet and returns an 11.32.1 RCOUNT ACK handshake. If any other cause prevents the receive Receive FIFO Count. This field indicates the count of state machine from accepting the SETUP packet, it must bytes presently in the Endpoint receive FIFO. If this count not generate a handshake. is greater than 15, a value of 15 is reported. 11.33.2 IGN_SETUP 11.32.3 TOGGLE Ignore SETUP Tokens. When this bit is set, the endpoint ignores any SETUP tokens directed to its configured address. 11.33.3 FLUSH bs Receive Last. This bit, when set, indicates that the COUNT field reflects the number of bytes remaining of the packet. This bit is cleared when the register is read. Toggle Data. This bit has two functions: one for ISO mode (EPCx.ISO set) and one for non-ISO mode (EPCx.ISO cleared). 11.33.4 RFWL[1:0] O For non-ISO operation, this bit is set if the last successfully received packet was received with a DATA1 PID. This bit is cleared if the last successfully received packet has a DATA0 PID. This bit is left unchanged on zero-length packets. Flush FIFO. Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the Endpoint to IDLE, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after the reception is done. Receive FIFO Warning Limit. These bits specify how many more bytes can be received in the respective FIFO before an overrun condition occurs. If the number of bytes For ISO operation, this bit reflects the least significant bit subsequently received in the FIFO is greater than or equal of the frame number (FNL[0]) after a packet is successful- to the selected warning limit, then the WARN bit in the FIFO Warning Event Register (FWEV.RXFW[x]) is set. ly received for this endpoint. Table 7. Receive FIFO Warning Limits This bit is reset to zero by reading the Receive Status Register. RFWL [1:0] 11.32.4 SETUP Receive WARN Condition Setup Packet. This bit, when set, indicates that a setup packet has been received. This bit is cleared when the register is read. 0 0 0 1 4 more bytes can be received in FIFO 11.32.5 RX_ERR 1 0 8 more bytes can be received in FIFO 1 1 16 more bytes can be received in FIFO Receive Error. This bit is set in the event of a media error such as a bit stuffing or CRC Error. The firmware needs to flush the respective FIFO when this bit is set. 33 Disable WARN bit warning for receive FIFO www.national.com 11.0 Register Set (Continued) 11.34 Receive Data Register x (RXD1, RXD2, RXD3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RXFD – r The Receive Data Registers RXD1, RXD2, and RXD3 hold data from Receive Endpoint FIFOs 2, 4, and 6, respectively. The three registers follow the format shown above. 11.34.1 RXFD Receive FIFO Data Byte. See “Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)” on page 20 for a description of Endpoint FIFO data handling. O bs ol et e The firmware should expect to read only the packet payload data. The PID and CRC16 are removed automatically by the receive state machine. 34 www.national.com 12.0 Design considerations 12.1 Targeted Applications 12.2 3.3V Regulator Issues The USBN9602 is designed to be used in Full Speed USB operations. The target applications are self-powered devices like modems, printers, storage devices, imaging devices, etc. To comply with the Agreed USB Device Working Group Review Requests - 110 dated July 7, 1997, a 7.5 kΩ ± 1% resistor can be tied from D+ to Vcc, or use a 1.13 kΩ ± 1% resistor tied to 3.3V. The USBN9602 is not intended for use in low speed applications. While not normally intended for bus-powered operation, this is possible in some cases with the addition of external circuitry. Contact National Semiconductor for the application notes that describe bus-powered use. Vcc = 5V Vcc = 3.3V OR 7.5 kΩ ± 1% 1.13 kΩ ±1% D+ D+ 12.3 Simplified Application Diagrams 3.3V VCC IN 4148 Note: pull all unused input and I/O pins up or down, as appropriate. 1.5K VCC 10K USB CONNECTOR 24Ω MODE1 MODE0 COP888EG 10 uF G0/INT 48 MHz 22 pF CKI SL SO SK D+ D- 24Ω RST INTR USBN9602 XIN et e RST D+ D- AGND CLKOUT 3rd harmonic XOUT SK SI SO 100 nF 56 pF ol 470nH bs Figure 20. MICROWIRE Serial Interface ALE WR RD O XTAL1 VCC 8051 AD7 AD0 A8 - A15 RESET 1.5K ALE WR RD CLKOUT DECODER USB CONNECTOR 24Ω D+ D24Ω MODE1 MODE0 USBN9602 AD7 XIN AD0 8 8 3.3V AGND 48 MHz 3rd harmonic CS D+ D- 22 pF INTR RST XOUT INTO VCC 100 nF VCC 470nH 56 pF 10 uF IN 4148 10K 10 uF Figure 21. Multiplex Parallel Interface 35 www.national.com 13.0 Memory Map Table 8 is a memory map showing the addresses of the USBN9602 registers. Table 8. USBN9602 Memory Map Address Register Name Register Function MCNTRL Main Control Register 0x01 CCONF Clock Configuration Register 0x02 reserved reserved 0x03 RID Revision Identifier 0x04 FAR Function Address Register 0x05 NFSR Node Functional State Register 0x06 MAEV Main Event Register 0x07 MAMSK Main Mask Register 0x08 ALTEV Alternate Event Register 0x09 ALTMSK Alternate Mask Register 0x0A TXEV Transmit Event Register 0x0B TXMSK Transmit Mask Register 0x0C RXEV Receive Event Register 0x0D RXMSK Receive Mask Register 0x0E NAKEV NAK Event Register 0x0F NAKMSK NAK Mask Register 0x10 FWEV FIFO Warning Event Register 0x11 FWMSK FIFO Warning Mask Register 0x12 FNH Frame Number Register High Byte 0x13 FNL 0x14 DMA CNTRL DMA Control Register 0x150x1F reserved reserved 0x20 EPC0 Endpoint Control Register 0 0x21 TXD0 Transmit Data Register 0 0x22 TXS0 Transmit Status Register 0 0x23 TXC0 Transmit Command Register 0 0x24 reserved reserved 0x25 RXD0 Receive Data Register 0 0x26 RXS0 Receive Status Register 0 0x27 RXC0 Receive Command Register 0 0x28 EPC1 Endpoint Control Register 1 0x29 TXD1 Transmit Data Register 1 0x2A TXS1 Transmit Status Register 1 Register Name Register Function 0x2B TXC1 Transmit Command Register 1 0x2C EPC2 Endpoint Control Register 2 0x2D RXD1 Receive Data Register 1 0x2E RXS1 Receive Status Register 1 0x2F RXC1 Receive Command Register 1 0x30 EPC3 Endpoint Control Register 3 0x31 TXD2 Transmit Data Register 2 0x32 TXS2 Transmit Status Register 2 0x33 TXC2 Transmit Command Register 2 0x34 EPC4 Endpoint Control Register 4 0x35 RXD2 Receive Data Register 2 et e 0x00 Address RXS2 Receive Status Register 2 0x37 RXC2 Receive Command Register 2 0x38 EPC5 Endpoint Control Register 5 0x39 TXD3 Transmit Data Register 3 0x3A TXS3 Transmit Status Register 3 0x3B TXC3 Transmit Command Register 3 0x3C EPC6 Endpoint Control Register 6 0x3D RXD3 Receive Data Register 3 0x3E RXS3 Receive Status Register 3 0x3F RXC3 Receive Command Register 3 bs ol 0x36 O Frame Number Register Low Byte 36 www.national.com 14.0 Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. -0.5V to +7.0V Supply Voltage DC Input Voltage -0.5V to Vcc +0.5V DC Output Voltage -0.5V to Vcc +0.5V -65°C to +150°C Storage Temperature 260°C Lead Temperature (Soldering 10 seconds) ESD Rating 1 2 kV 1. Human body model; 100pF discharged through a 1.5 kΩ resistor. DC Electrical Characteristics (4.5V< VCC < 5.5V1, 0°C < TA< +70°C, unless otherwise specified) Parameter Icc1 Operating Supply Current Icc2 Standby Supply Current Condition Min Max Units 30 40 mA 5 10 mA -0.2 0.2 V suspend mode: clock off, no accesses. USB SIGNALS Typ. et e Symbol OPERATING RATINGS Differential Input Sensitivity VCM Differential Common Mode Range 0.8 2.5 V VSE Single Ended Receiver Threshold 0.8 2.0 V VOL Output Low Voltage RL = 1.5k to 3.6V 0.3 V VOH Output High Voltage RL = 15k to GND 2.8 3.6 V IOZ TRI-STATE Data Line Leakage 0V < VIN < 3.3V -10 10 µA 20 pF bs O CTRN (D+) – (D–) ol VDI Transceiver Capacitance DIGITAL INPUTS/OUTPUTS (RESET, MODE, CLKOUT, AD0-AD7, WR, RD, A0) VOH Output High Voltage IOH = -6mA VOL Output Low Voltage IOL = 6mA VIH Input High Voltage VIL Input Low Voltage IIL Input Low Current IIH IOZ 2.4 V 0.4 2.0 V V 0.8 V VIN = GND -10 µA Input High Current VIN = Vcc 10 µA TRI-STATE Leakage2 VOUT = Vcc or GND 10 µA 37 -10 www.national.com 14.0 Electrical Characteristics (Continued) DC Electrical Characteristics (4.5V< VCC < 5.5V1, 0°C < TA< +70°C, unless otherwise specified) Symbol Parameter Condition Min Typ. Max Units OSCILLATOR INPUT/OUTPUT (XIN, XOUT) VIH Input High Switching Level3 VIL Input Low Switching Level3 4.5 V 1.35 V 1. VCC should be between 4.75V and 5.25V if the internal 3.3V regulator is used. If external 3.3V regulator is used, voltage on the V3.3 pin should be between 3.15 and 3.6V and VCC remains between 4.5V and 5.5V. 2. Not testable due to 15k pulldown resistor per USB Specification. 3. When XIN is used as an input for an external oscillator, the duy cycle must be between 45% and 55%. AC Electrical Characteristics (4.5V< VCC < 5.5V1, 0°C < TA< +70°C, unless otherwise specified) Symbol Parameter Condition2,3 Min Typ Max Units FULL SPEED SIGNALING (D+, D–) Rise Time TF Fall Time TRFM Rise / Fall Time Matching (T R /TF) VCRS Output Signal Crossover Voltage4 ZDRV Driver Output Impedance (Single Ended) CL = 50pF 4 20 nS CL = 50pF 4 20 nS CL = 50pF 90 110 % CL = 50pF 1.3 2.0 V CL = 50pF5 28 43 Ω CL =50pF 6 15 nS CL =50pF 6 15 nS 55 % ol et e TR CLOCK OUT CHARACTERISTICS (CLKOUT) Output Rise Time TF Output Fall Time TCYCLE Output Duty Cycle bs TR 45 O 1. VCC should be between 4.75V and 5.25V if the internal 3.3V regulator is used. If external 3.3V regulator is used, voltage on the V3.3 pin should be between 3.15 and 3.6V and VCC remains between 4.5V and 5.5V. 2. Testing will be centered around 50 Ω, not 45 Ω ± 15% as specified in USB Specification Revision 1.0. 3. Waveforms are measured from 10% to 90%. 4. Not testable. 5. Includes external resistor of 18 Ω. 6. Fout