CS51023EDR16

CS51021/22/23/24 CS51021/CS51023 CS51022/CS51024 Enhanced Current Mode PWM Controller Description The CS51021/22/23/24 Fixed Frequency PWM Current Mode Controller family provides all necessary features required for AC-DC or DC-DC primary side control. Several features are included eliminating the additional components needed to implement them externally. In addition to low start-up current (75µA) and high frequency operation capability, the CS51021/ 22/23/24 family includes overvoltage and undervoltage monitoring, externally programmable dual Device Features s 75µA Max. Startup Current s Fixed Frequency Current Mode Control s 1MHz Switching Frequency s Undervoltage Protection Monitor s Overvoltage Protection Monitor with Programmable Hysteresis s Programmable Dual Threshold Overcurrent Protection with Delayed Restart s Programmable Soft Start s Accurate Maximum Duty Cycle Limit s Programmable Slope Compensation s Leading Edge Current Sense Blanking s 1A Sink/Source Gate Drive s Bidirectional Synchronization (CS51021/23) s 50ns PWM Propagation Delay s 100µA Max Sleep Current (CS51022/24) threshold overcurrent protection, current sense leading edge blanking, current slope compensation, accurate duty cycle control and an externally available 5V reference. The CS51021 and CS51023 feature bidirectional synchronization capability, while the CS51022 and CS51024 offer a sleep mode with 100µA maximum IC current consumption. The CS51021/22/23/24 family is available in a 16 lead narrow body SO package. Sleep/Synch VCC Start/Stop CS51021 CS51022 CS51023 CS51024 Synch Sleep Synch Sleep Typical Application Diagram 8.25V/7.7V 8.25V/7.7V 13V/7.7V 13V/7.7V VIN (36V to 72V) PGND SYNC/SLEEP 100 51k 11V FZT688 10 BAS21 22µF 18V 0.1µF 1µ F 100:1 200K,1% 24.3K 1% 10K 4:1 MBRB2060CT 2:5 VOUT (5V/5A) 100µF 100µF SGND 0.01µF 10K 4700pF 51K CS51021/51022 22K VC VREF COMP VFB RTCT SYNC/ SLEEP CSS LGnd VCC UV OV ISET SLOPE GATE ISENSE PGnd 10 2.49K,1% 680pF BA521 10 IRF6345 100pF Package Options 16 Lead SO Narrow GATE ISENSE 1 330pF 0.01µF U1 6.98k, 6.98k, 100 1% 1% 100p 470pF 62 10 VC PGnd VCC VREF LGnd SS COMP VFB 0.1µF 5.1K TL431 1000pF 180 10K MOC81025 SLEEP or SYNC SLOPE 2K, 1% UV OV RTCT ISET 1K 2K,1% 1K 36-72V to 5V, 5A DC-DC Convertor Consult factory for other package options. Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 2/22/99 1 A ® Company CS51021/22/23/24 Absolute Maximum Ratings Power Supply Voltage, VCC ............................................................................................................................................-0.3V, 20V Driver Supply Voltage, VC ..............................................................................................................................................-0.3V, 20V SYNC, SLEEP, RTCT, SOFT START, VFB, SLOPE, ISENSE, UV, OV, ISET (Logic Pins).......................................-0.25V to VREF Peak GATE Output Current.........................................................................................................................................................1A Steady State Output Current..................................................................................................................................................± 0.2A Operating Junction Temperature, TJ ..................................................................................................................................... 150°C Storage Temperature Range, TS ...................................................................................................................................-65 to 150°C ESD (Human Body Model).........................................................................................................................................................2kV Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s Under Voltage Lockout START Threshold (CS51021/22) START Threshold (CS51023/24) STOP Threshold Hysteresis (CS51021/22) Hysteresis (CS51023/24) ICC @ Startup (CS51021/22) ICC @ Startup (CS51023/24) ICC Operating (CS51021/23) ICC Operating (CS51022/24) IC Operating s Voltage Reference Initial Accuracy Total Accuracy Line Regulation Load Regulation NOISE Voltage OP Life Shift FAULT Voltage OK Voltage OK Hysteresis Current Limit s Error Amplifier Initial Accuracy Reference Voltage VFB Leakage Current Open Loop Gain Unity Gain Bandwidth COMP Sink Current COMP Source Current TA=25°C, IREF = 2mA, VCC = 14V, VFB = COMP (Note 1) VFB = COMP VFB = 0V 1.4V < COMP < 4V (Note 1) (Note 1) COMP = 1.5V, VFB = 2.7V COMP = 1.5V, VFB = 2.3V 2 60 1.5 2 -0.2 2.465 2.440 2.515 2.515 -0.2 90 2.5 6 -0.5 2.565 2.590 -2 V V µA dB MHz mA mA TA = 25C, IREF = 2mA, VCC = 14V (Note1) 4.95 1mA 1V, VC = 20V 11 1.5 1.2 13.5 0.6 1 -1 60 15 2.2 1.5 16 0.8 -50 100 40 V V V V A µA ns ns Active High VSLEEP = 4V VCC ≤ 15V 1.0 11 1.5 25 50 2.7 46 100 V µA µA 1.0 160 3.5 35 80 1.25 1.5 260 4.3 70 120 2 2.7 360 4.8 140 150 3.5 V ns V kΩ ns mA RT = 12k, CT = 390pF Delta Frequency 8.2V < VCC < 20V TMIN < TA < TMAX (Note1) (Note1) RT = 12k, CT = 390pF (Note 1) (Note 1) 10k Resistor to ground on RTCT TA=25°C (Note 1) 0.333 70 230 255 2 8 77 3 1.5 1.4 1 1 83 280 3 kHz % % µs % V V V mA mA VFB = 2.3V VFB = 2.7V FREQ = 120Hz (Note 1) VSS=2.5V, VFB = 0V, ISET = 2V (Note 1) 4.35 0.4 60 2.4 0.95 4.8 0.8 85 2.5 1 5 1.2 2.6 1.15 V V dB V V 1.2 0.8 0.925 1.6 1.2 1.075 ISYNC = 100µA (Note 1) SYNC to GATE RESET 1k Load 3 CS51021/22/23/24 Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s SLOPE Compensation Charge Current COMP Gain Discharge Voltage s Current Sense OFFSET Voltage Blanking Time Blanking Disable Voltage Second Current Threshold Gain ISENSE Input Resistance Minimum On Time Gain s OV & UV Voltage Monitors OV Monitor Threshold OV Hysteresis Current UV Monitor Threshold UV Monitor Hysteresis s SOFT START (SS) Charge Current Discharge Current Charge Voltage, VSS Discharge Voltage, VSS Note 1: Guaranteed by Design, not 100% tested in production. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION SLOPE = 2V Fraction of slope voltage added to ISENSE (Note 1) SYNC = 0V -63 0.095 -53 0.100 0.1 -43 0.105 0.2 µA V/V V (Note 1) Adjust VFB 0.09 1.8 1.21 0.10 55 2 1.33 5 70 0.80 0.11 160 2.2 1.45 110 0.82 V ns V V/V kΩ ns V/V GATE High to Low (Note 1) 30 0.78 2.4 -10 1.38 25 2.5 -12.5 1.45 75 2.6 -15 1.52 100 V µA V mV SS = 2V SS = 2V -70 250 4.4 0.25 -55 1000 4.7 0.27 -40 5 0.30 µA µA V V 16L PDIP & SO Narrow 1 2 3 3 GATE ISENSE SYNC (CS51021/23) SLEEP (CS51022/24) SLOPE UV OV External power switch driver with 1.0A peak capability. Current sense amplifier input. Bi-directional synchronization. Locks to the highest frequency. Active high chip disable. In sleep mode, VREF and GATE are turned off. Additional slope to the current sense signal. Internal current source charges the external capacitor. Undervoltage protection monitor. Overvoltage protection monitor. 4 5 6 4 CS51021/22/23/24 Package Pin Description: continued PACKAGE PIN # PIN SYMBOL FUNCTION 16L PDIP & SO Narrow 7 8 RTCT ISET Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. Voltage at this pin sets pulse-by-pulse overcurrent threshold, and second threshold (1.33 times higher) with Soft Start retrigger (hiccup mode). Feedback voltage input. Connected to the error amplifier inverting input. Error amplifier output. Frequency compensation network is usually connected between COMP and VFB pins. Charging external capacitor restricts error amplifier output voltage during the start or fault conditions (hiccup). Logic ground. 5.0V reference voltage output. Logic supply voltage. Output power stage ground connection. Output power stage supply voltage. Block Diagram VCC + START STOP Vcc_OK 9 10 11 12 13 14 15 16 VFB COMP SS LGnd VREF VCC PGnd VC VREF VREF = 5V VREF_OK + LGnd SLEEP SYNC RTCT VC 200ns 4.3V OSC 4.75V G2 D4 ZD1 13.5V S F1 SS Clamp D2 G1 ISET Clamp D3 + 2.5V E/A D1 VREF 53µA + – 2V VFB Monitor G4 DISABLE 0.1V + SS Monitor + Q GATE R COMP PGnd 20k 10k PWM Comp VREF 55µA VFB SS SLOPE ISENSE Q2 × × 0.1 0.8 ∑ – 55ns Blank VISense 4.7V – 1.33 2nd Threshold ISET OV VREF 12.5µA × G3 FAULT Discharge Latch OV Monitor + 2.5V – UV Monitor + UV 1.45V – Figure 1: CS51021/22/23/24 Block Diagram 5 CS51021/22/23/24 Circuit Description 200ns 4.3V SYNC RTCT TCH 0V VSLOPE SLOPE 0V IS 0V IS + 0.1 SLOPE IS TDIS Blanking is disabled when VFB is less than 2V so that the minimum on-time of the controller does not have an additional 55ns of delay time during fault conditions. For the remaining portion of the switching period, the current sense signal, combined with a fraction of the slope compensation voltage, is applied to the positive input of the PWM comparator where it is compared with the divided by three error amplifier output voltage. The pulse-bypulse overcurrent protection threshold is set by the voltage at the ISET pin. This voltage is passed through the ISET Clamp and appears at the non-inverting input of the PWM comparator, limiting its dynamic range according to the following formula: Overcurrent Threshold= 0.8 × VI(SENSE) +0.1V + 0.1 VSLOPE where VI(SENSE) is voltage at the ISENSE pin and VSLOPE is voltage at the SLOPE pin. VCOMP 55ns Blanking PWM COMP 0V 0V GATE VIN 0V VDS During extreme overcurrent or short circuit conditions, the slope of the current sense signal will become much steeper than during normal operation. Due to loop propagation delay, the sensed signal will overshoot the pulseby-pulse threshold eventually reaching the second overcurrent protection threshold which is 1.33 times higher than the first threshold and is described by the following equation: 2nd Threshold = 1.33 × VI(SET) Exceeding the second threshold will reset the Soft Start capacitor CSS and reinitiate the Soft Start sequence, repeating for as long as the fault condition persists. Soft Start During power up, when the output filter capacitor is discharged and the output voltage is low, the voltage across the Soft Start capacitor (VSS) controls the duty cycle. An internal current source of 55µA charges CSS. The maximum error amplifier output voltage is clamped by the SS Clamp. When the Soft Start capacitor voltage exceeds the error amplifier output voltage, the feedback loop takes over the duty cycle control. The Soft Start time can be estimated with the following formula: tSS = 9 × 104 × CSS The Soft Start voltage, VSS, charges and discharges between 0.25V and 4.7V. Slope Compensation DC-DC converters with current mode control require a current sense signal with slope compensation to avoid instability at duty cycles greater than 50%. Slope capacitor CS is charged by an internal 53µA current source and is discharged during the oscillator discharge time. The slope compensation voltage is divided by 10 and is added to the current sense voltage, VI(SENSE). The signal applied to the Figure 2: Typical Waveforms Theory of Operation Powering the IC The IC has two supply and two ground pins. VC and PGnd pins provide high speed power drive for the external power switch. VCC and LGnd pins power the control portion of the IC. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, the output is held low. The CS51021/22/23/24 requires only 75µA of startup current. Voltage Feedback The output voltage is monitored via the VFB pin and is compared with the internal 2.5V reference. The error amplifier output minus one diode drop is divided by 3 and connected to the negative input of the PWM comparator. The positive input of the PWM comparator is connected to the modified current sense signal. The oscillator turns the external power switch on at the beginning of each cycle. When current sense ramp voltage exceeds the reference side of PWM comparator, the output stage latches off. It is turned on again at the beginning of the next oscillator cycle. Current Sense and Protection The current is monitored at the ISENSE pin. The CS51021/22/23/24 has leading edge blanking circuitry that ignores the first 55ns of each switching period. 6 CS51021/22/23/24 Circuit Description: continued input of the PWM comparator is a combination of these dVSLOPE two voltages. The slope compensation, , is calcudt lated using the following formula: dVSLOPE 53µA = 0.1 × C dt S It should be noted that internal capacitance of the IC will cause an error when determining slope compensation capacitance CS. This error is typically small for large values of CS, but increases as CS becomes small and comparable to the internal capacitance. The effect is apparent as a reduction in charging current due to the need to charge the internal capacitance in parallel with CS. Figure 3 shows a typical curve indicating this decrease in available charging current. 60 VIN R1 R2 R3 VUV Figure 4: UV/OV Monitor Divider VOV To calculate the OV/UV resistor divider: 1. Solve for R3, based on OV hysteresis requirements. VOV(HYST) × 2.5V ’ R3 = V MAX × 12.5µA where VOV(HYST) is the desired amount of overvoltage hysteresis, and VMAX is the input voltage at which the supply will shut down. 2. Find the total impedance of the divider. VMAX × R3 RTOT = R1 + R2 + R3 = 2.5 3. Determine the value of R2 from the UV threshold conditions. 1.45 × RTOT R2 = − R3, VMIN where VMIN is the UV voltage at which the supply will shut down. 4. Calculate R1. R1 = RTOT − R2 − R3 5. The undervoltage hysteresis is given by: VUV(HYST) = VMIN × 0.075 1.45 Charging Current (µA) 55 50 45 40 35 30 25 20 10 100 1000 Compensation Cap (pF) Figure 3: The slope compensation pin charge current reduces when a small capacitor is used. Undervoltage (UV) and Overvoltage (OV) Monitor Two independent comparators monitor OV and UV conditions. A string of three resistors is connected in series between the monitored voltage (usually the input voltage) and ground (see Figure 4). When voltage at the OV pin exceeds 2.5V, an overvoltage condition is detected and GATE shuts down. An internal 12.5µA current source turns on and feeds current into the external resistor, R3, creating a hysteresis determined by the value of this resistor (the higher the value, the greater the hysteresis). The hysteresis voltage of the OV monitor is determined by the following formula: VOV(HYST) = 12.5µA × R3 where R3 is a resistor connected from the OV pin to ground. When the monitored voltage is low and the UV pin is less than 1.45V, GATE shuts down. The UV pin has fixed 75mV hysteresis. Both OV and UV conditions are latched until the Soft Start capacitor is discharged. This way, every time a fault condition is detected the controller goes through the power up sequence. Synchronization A bi-directional synchronization is provided to synchronize several controllers. When SYNC pins are connected together, the converters will lock to the highest switching frequency. The fastest controller becomes the master, producing a 4.3V, 200ns pulse train. Only one, the highest frequency SYNC signal, will appear on the SYNC line. Sleep The sleep input is an active high input. The CS51022/51024 is placed in sleep mode when SLEEP is driven high. In sleep mode, the controller and MOSFET are turned off. Connect to Gnd for normal operation. The sleep mode operates at VCC ≤ 15V. Oscillator and Duty Cycle Limit The switching frequency is set by RT and CT connected to the RTCT pin. CT charges and discharges between 3V and 1.5V. The maximum duty cycle is set by the ratio of the on time, tON, and the whole period, T = tON + tOFF. Because the 7 CS51021/22/23/24 Circuit Description: continued timing capacitor’s discharge current is trimmed, the maximum duty cycle is well defined. It is determined by the ratio between the timing resistor RT and the timing capacitor CT. Refer to figures 5 and 6 to select appropriate values for RT and CT. 1 fSW = T ; TSW = tCH + tDIS SW 2500 100 7 6 90 5 8 80 4 3 2 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF Duty Cycle (%) 70 1 60 1 2000 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF 50 Frequency (kHz) 1500 40 5 10 15 20 25 30 35 40 45 50 55 RT (kΩ) 2 1000 3 4 500 5 6 8 0 5 10 7 15 20 25 30 Figure 6: Duty Cycle vs. RT for Discrete Capacitor Values. 35 40 45 50 RT (kΩ) Figure 5: Frequency vs. RT for Discrete Capacitor Values. 8 CS51021/22/23/24 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count 16L SO Narrow Metric Max Min 10.00 9.80 English Max Min .394 .386 Thermal Data RΘJC RΘJA typ typ 16L SO Narrow 28 115 ˚C/W ˚C/W Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D REF: JEDEC MS-012 0.25 (0.10) 0.10 (.004) Ordering Information Part Number CS51021ED16 CS51021EDR16 CS51022ED16 CS51022EDR16 CS51023ED16 CS51023EDR16 CS51024ED16 CS51024EDR16 Rev. 2/22/99 Description 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) 9 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. © 1999 Cherry Semiconductor Corporation