CS43L41
Low Power 24-Bit, 96 kHz DAC with Volume Control
Features
Description
l Complete Stereo DAC System: Interpolation,
The CS43L41 is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.
D/A, Output Analog Filtering
l ATAPI Mixing
l 101 dB Dynamic Range
l 89 dBFS THD+N
l Low Clock Jitter Sensitivity
l +2.4 V to +5 V Power Supply
l Filtered Line Level Outputs
l On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l Digital Volume Control with Soft Ramp
The CS43L41 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power and operates over a wide power supply range. These features are
ideal for portable DVD, portable MP3, Mini-Disc, and
mobile phones.
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
l 24
ORDERING INFORMATION
CS43L41-KZ
16-pin TSSOP, -10 to 70 °C
mW with 2.4 V supply
I
SCL/CCLK
SDA/CDIN
Control Port
RST
SCLK
LRCK
SDATA
Serial Port
Interpolation Filter
AD0/CS
MUTEC
External
Mute Control
Volume Control
∆Σ DAC
Analog Filter
AOUTA
∆Σ DAC
Analog Filter
AOUTB
Mixer
Interpolation Filter
Volume Control
÷2
MCLK
Advanced Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
SEP ‘99
DS473PP1
1
CS43L41
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL CHARACTERISTICS ................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 10
2. TYPICAL CONNECTION DIAGRAM .................................................................................... 11
3. REGISTER QUICK REFERENCE .......................................................................................... 14
3.1 MCLK Control (address 00h) ............................................................................................ 14
3.2 Mode Control (address 01h) ............................................................................................. 14
3.3 Volume and Mixing Control (address 02h)........................................................................ 15
3.4 Channel A Volume Control (address 03h) ........................................................................ 15
3.5 Channel B Volume Control (address 04h) ........................................................................ 15
4. REGISTER BIT DESCRIPTION .............................................................................................. 16
4.1 Master Clock Divide Enable.............................................................................................. 16
4.2 Auto-Mute ......................................................................................................................... 16
4.3 Digital Interface Format..................................................................................................... 17
4.4 De-emphasis Control ........................................................................................................ 17
4.5 Power On/Off Quiescent Voltage Ramp ........................................................................... 18
4.6 Power Down...................................................................................................................... 18
4.7 Channel A Volume = Channel B Volume.......................................................................... 19
4.8 Soft Ramp or Zero Cross Enable...................................................................................... 19
4.9 ATAPI Channel Mixing and Muting ................................................................................... 20
4.10 Mute ................................................................................................................................ 21
4.11 Volume Control ............................................................................................................... 22
5. PIN DESCRIPTION ................................................................................................................. 23
Analog Power - VA.................................................................................................................. 23
Analog Ground - AGND .......................................................................................................... 23
Analog Output - AOUTA and AOUTB ..................................................................................... 23
Reference Ground - REF_GND .............................................................................................. 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Philips Semiconductors.
SPI is a registered trademark of International Business Machines Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS473PP1
Confidential Draft
9/23/99
CS43L41
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST ............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
7.2 I2C Compatible Mode ...................................................................................................... 26
7.3 Memory Address Pointer (MAP) ....................................................................................... 27
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
DS473PP1
3
CS43L41
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
External Serial Mode Input Timing ................................................................................. 9
Internal Serial Mode Input Timing .................................................................................. 9
Internal Serial Clock Generation .................................................................................... 9
I2C Control Port Timing ................................................................................................ 10
SPI Control Port Timing ............................................................................................... 12
Typical Connection Diagram ........................................................................................ 13
SPI Mode Control Port Formatting ............................................................................... 28
I2C Mode Control Port Formatting ................................................................................ 28
Base-Rate Stopband Rejection .................................................................................... 29
Base-Rate Transition Band .......................................................................................... 29
Base-Rate Transition Band (Detail) ............................................................................. 29
Base-Rate Passband Ripple ........................................................................................ 29
High-Rate Stopband Rejection ..................................................................................... 29
High-Rate Transition Band ........................................................................................... 29
High-Rate Transition Band (Detail) .............................................................................. 30
High-Rate Passband Ripple ......................................................................................... 30
Output Test Load ......................................................................................................... 30
Maximum Loading ........................................................................................................ 30
Power vs. Sample Rate (VA = 5V) ............................................................................... 30
CS43L41 Format 0 (I2S) .............................................................................................. 31
CS43L41 Format 1 (I2S) .............................................................................................. 31
CS43L41 Format 2 ....................................................................................................... 31
CS43L41 Format 3 ....................................................................................................... 32
CS43L41 Format 4 ....................................................................................................... 32
CS43L41 Format 5 ....................................................................................................... 32
CS43L41 Format 6 ....................................................................................................... 33
De-Emphasis Curve ..................................................................................................... 33
ATAPI Block Diagram .................................................................................................. 33
LIST OF TABLES
Table 1. Master Clock Divide Enable ............................................................................................... 16
Table 2. Auto-Mute Enable............................................................................................................... 16
Table 3. Digital Interface Formats .................................................................................................... 17
Table 4. De-emphasis Filter Configurations ..................................................................................... 17
Table 5. Power On/Off Ramp Enable ............................................................................................... 18
Table 6. Power Down Enable ........................................................................................................... 18
Table 7. A=B Volume Control Enable............................................................................................... 19
Table 8. Soft Ramp and Zero Cross Enable..................................................................................... 20
Table 9. ATAPI Decode.................................................................................................................... 20
Table 10. Mute Enable ..................................................................................................................... 21
Table 11. Digital Volume Settings .................................................................................................... 22
Table 12. Common Clock Frequencies ............................................................................................ 24
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DS473PP1
CS43L41
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 °C; Logic "1" = VA; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R L = 10 kΩ,
CL = 10 pF (see Figure 17)),
Base-rate Mode
Parameter
Symbol
Dynamic Performance for VA = 5 V
Specified Temperature Range
TA
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise
(Note 1) THD+N
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Interchannel Isolation
(1 kHz)
Dynamic Performance for VA = 2.4 V
Specified Temperature Range
TA
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise
(Note 1) THD+N
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Interchannel Isolation
(1 kHz)
High-Rate Mode
Min
Typ
Max
Min
Typ
Max
Unit
-10
-
70
-10
-
70
°C
92
96
-
97
101
95
99
-
91
95
-
96
100
94
98
-
dB
dB
dB
dB
-
-89
-77
-37
-88
-75
-35
-84
-72
-32
-
-
-89
-74
-36
-89
-73
-34
-84
-69
-31
-
dB
dB
dB
dB
dB
dB
-
100
-
-
100
-
dB
-10
-
70
-10
-
70
°C
TBD
TBD
-
92
95
91
94
-
TBD
TBD
-
91
95
90
94
-
dB
dB
dB
dB
-
-91
-72
-32
-90
-71
-31
TBD
TBD
TBD
-
-
-89
-71
-31
-88
-70
-30
TBD
TBD
TBD
-
dB
dB
dB
dB
dB
dB
-
100
-
-
100
-
dB
Notes: 1. One-half LSB of triangular PDF dither is added to data.
DS473PP1
5
CS43L41
ANALOG CHARACTERISTICS (Continued)
Parameters
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance
Load Capacitance
Symbol
VQ
(Note 2)
(Note 2)
RL
CL
Min
Typ
Max
Units
0.63•VA
3
-
0.7•VA
0.5•VA
0.1
100
-
0.77•VA
100
Vpp
VDC
dB
ppm/°C
kΩ
pF
Base-rate Mode
Parameter
Symbol
Min
Typ
Max
High-Rate Mode
Min
Typ
Max
Combined Digital and On-chip Analog Filter Response (Note 3)
Passband
(Note 4)
to -0.05 dB corner
0
.4535
to -0.1 dB corner
0
.4621
to -3 dB corner
0
.4998
0
.4982
Frequency Response 10 Hz to 20 kHz
-.02
+.08
-0.06
0
StopBand
.5465
.577
StopBand Attenuation
(Note 5)
50
55
Group Delay
tgd
9/Fs
4/Fs
Passband Group Delay Deviation 0 - 40 kHz
±1.39/Fs
0 - 20 kHz
±0.36/Fs
±0.23/Fs
De-emphasis Error
Fs = 32 kHz
+.2/-.1
(Relative to 1 kHz)
Fs = 44.1 kHz
+.05/-.14
(Note 6)
Fs = 48 kHz
+0/-.22
Unit
Fs
Fs
Fs
dB
Fs
dB
s
s
s
dB
dB
dB
Notes: 2. Refer to Figure 18.
3. Filter response is guaranteed by design.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
6. De-emphasis is not available in High-Rate Mode.
6
DS473PP1
CS43L41
POWER AND THERMAL CHARACTERISTICS
Parameters
Power Supplies
Power Supply Current
VA = 5 V
Power Dissipation
VA = 5 V
normal operation
power-down state
(Note 7)
normal operation
power-down
normal operation
power-down state
(Note 7)
normal operation
power-down
Power Supply Current
VA = 2.4 V
Power Dissipation
VA = 2.4 V
Package Thermal Resistance
Power Supply Rejection Ratio (1 kHz)
(Note 8)
(60 Hz)
Symbol
Min
Typ
Max
Units
IA
IA
-
15
60
17
-
mA
µA
IA
IA
-
75
0.3
10
30
85
TBD
-
mW
mW
mA
µA
-
24
0.07
110
60
40
TBD
-
mW
mW
°C/Watt
dB
dB
θJA
PSRR
Notes: 7. Refer to Figure 19.
8. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1.
DIGITAL CHARACTERISTICS (TA = 25°C; VA =
Parameters
High-Level Input Voltage
VA = 5 V
VA = 2.4 V
Low-Level Input Voltage
VA = 5 V
VA = 2.4 V
Input Leakage Current
Input Capacitance
Maximum MUTEC Drive Current
2.28V - 5.5V)
Symbol
VIH
Min
2.0
2.0
Typ
-
Max
-
Units
V
V
VIL
-
-
0.8
0.8
V
V
Iin
-
8
3
±10
-
µA
pF
mA
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-55
-65
Max
6.0
±10
VA+0.4
125
150
Units
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
DS473PP1
Symbol
VA
Min
2.28
Typ
5.0
Max
5.5
Units
V
7
CS43L41
SWITCHING CHARACTERISTICS (TA = -10 to 70°C; VA = 2.4V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, CL = 20pF)
Parameters
Symbol
Input Sample Rate
Typ
Max
Units
2
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width Low
Fs
Min
MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
31
-
1000
ns
MCLK Pulse Width Low
31
-
1000
ns
MCLK / LRCK = 256 or 128
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
MCLK / LRCK = 512, 256 or 384
SCLK Period
40
50
60
%
tsclkl
20
-
-
ns
tsclkh
20
-
-
ns
tsclkw
1
---------------------( 128 )Fs
-
-
ns
tsclkw
1
-----------------( 64 )Fs
-
-
ns
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDATA valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDATA hold time
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
tsdh
20
-
-
ns
-
50
-
%
-
-
ns
tsclkw
-----------------2
-
µs
1
---------------------- + 10
( 512 )Fs
1
---------------------- + 15
( 512 )Fs
-
-
ns
-
-
ns
1
---------------------- + 15
( 384 )Fs
-
-
ns
MCLK / LRCK = 128 or 192
(Note 9)
(Note 10)
tsclkw
SCLK rising to LRCK edge
tsclkr
SDATA valid to SCLK rising setup time
tsdlrs
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh
1
---------------SCLK
-
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See Figures 20-26)
8
DS473PP1
CS43L41
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
Figure 1. External Serial Mode Input Timing
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS43L41.
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L41.
N equals MCLK divided by SCLK
DS473PP1
9
CS43L41
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
Compatible Mode
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of Both SDA and SCL Lines
tr
-
1
µs
Fall Time of Both SDA and SCL Lines
tf
-
300
ns
tsusp
4.7
-
µs
I2C®
SDA Hold Time from SCL Falling
(Note 11)
SDA Setup time to SCL Rising
Setup Time for Stop Condition
Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 4. I2C Control Port Timing
10
DS473PP1
CS43L41
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
Mode
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
SPI®
CCLK Edge to CS Falling
(Note 12)
CCLK Rising to DATA Hold Time
(Note 13)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 14)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 14)
tf2
-
100
ns
Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Figure 5. SPI Control Port Timing
DS473PP1
11
CS43L41
2.
TYPICAL CONNECTION DIAGRAM
+5 V to + 2.4 V
+
0.1 µF
14
1 µF
VA
2
Audio
Data
Processor
3
4
SDATA
3.3 µF
SCLK
AOUTA
560 Ω
Audio
Output A
15
+
LRCK
10 kΩ
C
RL
CS4341
External Clock
5
MUTEC 16
MCLK
FILT+ 9
VQ
6
7
µ - Controlled
Configuration
8
OPTIONAL
MUTE
CIRCUIT
REF_GND
SCL/CCLK
+
10
.1 µF + 1 µF
11
3.3 µF
SDA/CDIN
AOUTB
AD0/CS
1
12
560 Ω
Audio
Output B
+
10 kΩ
RST
0.1 µF 1 µF
RL
C
AGND
13
C=
R L + 560
4πFs(R L 560)
Figure 6. Typical Connection Diagram
12
DS473PP1
CS43L41
3.
REGISTER QUICK REFERENCE
** “default” ==> bit status after power-up-sequence or reset.
3.1
MCLK Control (address 00h)
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
MCLKDIV
0
0
Reserved
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
POR
1
0
PDN
1
MCLKDIV (MCLK Divide-by-2 Enable)
Default = ‘0’.
0 - Disabled
1 - Enabled
3.2
Mode Control (address 01h)
7
AMUTE
1
6
DIF2
0
5
DIF1
0
AMUTE (Auto-mute)
Default = ‘1’.
0 - Disabled
1 - Enabled
DIF2, DIF1 and DIF0 (Digital Interface Format)
Default = ‘0’.
0 - Format 0, I2S, up to 24-bit data, 64 x Fs Internal SCLK
1 - Format 1, I2S, up to 24-bit data, 32 x Fs Internal SCLK
2 - Format 2, Left Justified, up to 24-bit data
3 - Format 3, Right Justified, 24-bit Data
4 - Format 4, Right Justified, 20-bit Data
5 - Format 5, Right Justified, 16-bit Data
6 - Format 6, Right Justified, 18-bit Data
7 - Identical to Format 1
DEM 1, DEM 0 (De-Emphasis Mode)
Default = ‘0’.
0 - Disabled
1 - 44.1 kHz De-Emphasis
2 - 48 kHz De-Emphasis
3 - 32 kHz De-Emphasis
POR (Power on/off Quiescent Voltage ramp)
Default = ‘1’.
0 - Disabled
1 - Enabled
PDN (Power-Down)
Default =’1’.
0 - Disabled
1 - Enabled
DS473PP1
13
CS43L41
3.3
Volume and Mixing Control (address 02h)
7
A=B
0
6
Soft
1
5
Zero Cross
0
4
ATAPI4
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
A = B (Channel A Volume = Channel B Volume)
Default = ‘0’.
0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by register
04h.
1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ignored.
Soft & Zero Cross (Soft control and zero cross detection control)
Default = ‘10’.
Soft
Zero Cross
Mode
0
0
Changes take effect immediately
0
1
Changes take effect on zero crossings
1
0
Changes take effect with a soft ramp (default)
1
1
Changes take effect in 1/8 dB steps on each zero crossing
ATAPI 0-4 (Channel mixing and muting)
(refer to Table 9)
Default = ‘01001’, (Stereo)
AOUTA = Left Channel
AOUTB = Right Channel
3.4
Channel A Volume Control (address 03h)
3.5
Channel B Volume Control (address 04h)
7
MUTE
0
6
VOL6
0
5
VOL5
0
4
VOL4
0
3
VOL3
0
2
VOL2
0
1
VOL1
0
0
VOL0
0
MUTE
Default = ‘0’
0 - Disabled
1 - Enabled
Volume
Default = ‘0’
(Refer to Table 11)
14
DS473PP1
CS43L41
4.
REGISTER BIT DESCRIPTION
4.1
MASTER CLOCK DIVIDE ENABLE
MCLK Control Register (address 00h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
MCLKDIV
0
Reserved
Access:
R/W in I2C and write only in SPI.
Default:
0 - Disabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
Note: This feature is present on revision C and newer devices. For backward compatibility with previous revision devices, this bit defaults to zero.
MCLKDIV
0
Disabled
1
Enabled
MODE
Table 1. Master Clock Divide Enable
4.2
AUTO-MUTE
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I2C and write only in SPI.
Default:
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period. The muting function is effected, similar to
volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
AMUTE
0
1
MODE
Disabled
Enabled
Table 2. Auto-Mute Enable
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15
CS43L41
4.3
DIGITAL INTERFACE FORMAT
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I2C and write only in SPI.
Default:
0 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 20-26.
DIF2
0
DIF1
0
DIF0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
DESCRIPTION
I2S,
up to 24-bit data, 64 x Fs Internal SCLK
2
I S, up to 24-bit data, 32 x Fs Internal SCLK
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 20-bit Data
Right Justified, 16-bit Data
Right Justified, 18-bit Data
Identical to Format 1
FORMAT
0
FIGURE
20
1
21
2
3
4
5
6
7
22
23
24
25
26
20
Table 3. Digital Interface Formats
4.4
DE-EMPHASIS CONTROL
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I2C and write only in SPI.
Default:
0 - Disabled
Function:
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 27, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is not available in High-Rate Mode.
DEM1
0
0
1
1
DEMO
0
1
0
1
DESCRIPTION
Disabled
44.1kHz
48kHz
32kHz
Table 4. De-emphasis Filter Configurations
16
DS473PP1
CS43L41
4.5
POWER ON/OFF QUIESCENT VOLTAGE RAMP
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I2C and write only in SPI.
Default:
1 - Enabled
Function:
The power On/Off Quiescent Voltage Ramp allows the quiescent voltage to slowly ramp to and from
0 volts to the quiescent voltage during power-on or power-off. Please refer to the applications section
for details of implementing this feature.
POR
0
1
MODE
Disabled
Enabled
Table 5. Power On/Off Ramp Enable
4.6
POWER DOWN
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I2C and write only in SPI.
Default:
1 - Enabled
Function:
The device will enter a low-power state whenever this function is activated. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The contents
of the control registers are retained in this mode.
PDN
0
1
MODE
Disabled
Enabled
Table 6. Power Down Enable
DS473PP1
17
CS43L41
4.7
CHANNEL A VOLUME = CHANNEL B VOLUME
Volume and Mixing Control Register (address 02h)
7
A=B
6
Soft
5
Zero Cross
4
ATAPI4
3
ATAPI3
2
ATAPI2
1
ATAPI1
0
ATAPI0
Access:
R/W in I2C and write only in SPI.
Default:
0 - Disabled
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.
A=B
0
1
MODE
Disabled
Enabled
Table 7. A=B Volume Control Enable
4.8
SOFT RAMP OR ZERO CROSS ENABLE
Volume and Mixing Control Register (address 02h)
7
A=B
6
Soft
5
Zero Cross
4
ATAPI4
3
ATAPI3
2
ATAPI2
1
ATAPI1
0
ATAPI0
Access:
R/W in I2C and write only in SPI.
Default:
10 - Soft Ramp enabled.
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock
periods.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
18
DS473PP1
CS43L41
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
SOFT
0
0
1
1
ZERO
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled
Table 8. Soft Ramp and Zero Cross Enable
4.9
ATAPI CHANNEL MIXING AND MUTING
Volume and Mixing Control Register (address 02h)
7
A=B
6
Soft
5
Zero Cross
4
ATAPI4
3
ATAPI3
2
ATAPI2
1
ATAPI1
0
ATAPI0
Access:
R/W in I2C and write only in SPI.
Default:
01001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS43L41 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer
to Table 9 and Figure 28 for additional information.
ATAPI4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTA
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
AOUTB
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
Table 9. ATAPI Decode
DS473PP1
19
CS43L41
ATAPI4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ATAPI3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTA
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
AOUTB
bL
[(aL+bR)/2]
MUTE
bR
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 9. ATAPI Decode (Continued)
4.10
MUTE
Channel A Volume Control Register (address 03h)
Channel B Volume Control Register (address 04h)
7
MUTE
6
VOL6
5
VOL5
4
VOL4
3
VOL3
2
VOL2
1
VOL1
0
VOL0
Access:
R/W in I2C and write only in SPI.
Default:
0 - Disabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero
Cross bits in the Volume and Mixing Control register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels.
MUTE
0
1
MODE
Disabled
Enabled
Table 10. Mute Enable
20
DS473PP1
CS43L41
4.11
VOLUME CONTROL
Channel A Volume Control Register (address 03h)
Channel B Volume Control Register (address 04h)
7
MUTE
6
VOL6
5
VOL5
4
VOL4
3
VOL3
2
VOL2
1
VOL1
0
VOL0
Access:
R/W in I2C and write only in SPI.
Default:
0 - 0 dB (No attenuation)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB.
Volume settings are decoded as shown in Table 11. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings
less than - 94 dB are equivalent to enabling the Mute bit.
Binary Code
0000000
0010100
0101000
0111100
1011010
Decimal Value
0
20
40
60
90
Volume Setting
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 11. Digital Volume Settings
DS473PP1
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CS43L41
5.
PIN DESCRIPTION
Reset
RST
1
16
MUTEC
Mute Control
Serial Data
SDATA
2
15
AOUTA
Analog Output A
Serial Clock
SCLK
3
14
VA
Analog Power
Left/Right Clock
LRCK
4
13
AGND
Analog Ground
Master Clock
MCLK
5
12
AOUTB
Analog Output B
SCL/CCLK
SCL/CCLK
6
11
REF_GND Reference Ground
SDA/CDIN
SDA/CDIN
7
10
VQ
Quiescent Voltage
AD0/CS
AD0/CS
8
9
FILT+
Positive Voltage Reference
Analog Power - VA
Pin 14, Input
Function:
Analog power supply. Typically 2.4 to 5VDC.
Analog Ground - AGND
Pin 13, Input
Function:
Analog ground reference.
Analog Output - AOUTA and AOUTB
Pins 12 and 15, Output
Function:
The full scale analog output level is specified in the Analog Characteristics specifications table.
Reference Ground - REF_GND
Pin 11, Input
Function:
Ground reference for the internal sampling circuits. Must be connected to analog ground.
Positive Voltage Reference - FILT+
Pin 9, Output
Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source
impedance of 250 kΩ and any current drawn from this pin will alter device performance.
Quiescent Voltage - VQ
Pin 10, Output
Function:
Filter connection for internal quiescent reference voltage, typically 50% of VA. Capacitors must be connected from VQ to analog ground, as shown in Figure 6. VQ is not intended to supply external current. VQ
has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.
22
DS473PP1
CS43L41
Master Clock - MCLK
Pin 5, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base
Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note
that some multiplication factors require setting the MCLKDIV bit in the MCLK Control Register. Table 12
illustrates several standard audio sample rates and the required master clock frequencies.
MCLK (MHz)
Sample Rate
(kHz)
32
44.1
48
64
88.2
96
HRM
128x
4.0960
5.6448
6.1440
8.1920
11.2896
12.2880
192x
6.1440
8.4672
9.2160
12.2880
16.9344
18.4320
256x*
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
384x*
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
256x
8.1920
11.2896
12.2880
-
384x
12.2880
16.9344
18.4320
-
BRM
512x
16.3840
22.5792
24.5760
-
768x*
24.5760
32.7680
36.8640
-
1024x*
32.7680
45.1584
49.1520
-
* Requires MCLKDIV bit = 1 in MCLK Control Register (address 00h)
Table 12. Common Clock Frequencies
Left/Right Clock - LRCK
Pin 4, Input
Function:
The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right
sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs
will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
Serial Audio Data - SDATA
Pin 2, Input
Function:
Two’s complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
DS473PP1
23
CS43L41
Serial Clock - SCLK
Pin 3, Input
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
The CS43L41 supports both internal and external serial clock generation modes. The Internal Serial Clock
Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode
is always preferred.
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master
clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data
format, as shown in Figures 20-26. Operation in this mode is identical to operation with an external serial
clock synchronized with LRCK.
External Serial Clock Mode
The CS43L41 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected
on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode
if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal registers are reset to the default settings, including
the control port, when low. When high, the control port becomes operational and the PDN bit must be
cleared before normal operation will occur. The control port can not be accessed when reset is low.
Serial Control Interface Clock - SCL/CCLK
Pin 6, Input
Function:
Clocks the serial control data into or from SDA/CDIN.
Serial Control Data I/O - SDA/CDIN
Pin 7, Input/Output
Function:
In I2C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode.
Address Bit / Chip Select - AD0/CS
Pin 8, Input
Function:
In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
Mute Control - MUTEC
Pin 16, Output
Function:
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
24
DS473PP1
CS43L41
6. APPLICATIONS
6.1
Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS43L41 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power
arrangement with VA connected to a clean supply.
Decoupling capacitors should be located as close to
the device package as possible.
6.2
Oversampling Modes
The CS43L41 operates in one of two oversampling
modes based on the input sample rate and the state
of the MCLKDIV bit in the MCLK Control Register. Base Rate Mode (BRM) supports input sample
rates up to 50 kHz while High Rate Mode (HRM)
supports input sample rates up to 100 kHz. When
the MCLKDIV bit is cleared, the devices operate in
BRM when MCLK/LRCK is 256, 384 or 512 and
in HRM when MCLK/LRCK is 128 or 192. When
the MCLKDIV bit is set, the devices operate in
BRM when MCLK/LRCK is 512, 768 or 1024 and
in HRM when MCLK/LRCK is 256 or 384.
6.3
Recommended Power-up Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ low and the control port accessible. The desired register settings can be loaded
while keeping the PDN bit set to 1.
3. Set the PDN bit to 0 which will initiate the power-up sequence, which requires approximately 50
µs when the POR bit is set to 0. If the POR bit is
set to 1, see Section 6.4 for total power-up timing.
6.4
Use of the Power ON/OFF Quiescent
Voltage Ramp
The CS43L41 uses a novel technique to minimize
the effects of output transients during power-up
and power-down. This technique, when used with
external DC-blocking capacitors in series with the
audio outputs, minimizes the audio transients commonly produced by single-ended single-supply
converters.
When the device is initially powered-up, the audio
outputs, AOUTA and AOUTB, are clamped to
AGND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiescent voltage, minimizing the power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state. When this occurs, audio output ceases and the internal output
buffers are disconnected from AOUTA and
AOUTB. In their place, a soft-start current sink is
substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off
and the system is ready for the next power-on.
To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning off
the power or exiting the power-down state. If not, a
transient will occur when the audio outputs are initially clamped to AGND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
Use of the Mute Control function is recommended
for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute
DS473PP1
25
CS43L41
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limited by the external mute circuit.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings of the CS43L41. The operation of the control
port may be completely asynchronous to the audio
sample rate. However, to avoid potential interference problems, the control port pins should remain
static if no operation is required. *
The control port has 2 modes: SPI and I2C compatible, with the CS43L41 operating as a slave device
in both modes. If I2C operation is desired, AD0/CS
should be tied to VA or AGND. If the CS43L41
ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. The control port registers are write-only in SPI mode.
7.1
SPI Mode
In SPI mode, CS is the CS43L41 chip select signal,
CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.
Figure 7 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP.
7.2
I2C Compatible Mode
In I2C compatible mode, SDA is a bi-directional
data line. Data is clocked into and out of the part by
the clock, SCL, with the clock to data relationship
as shown in Figure 8. There is no CS pin. Pin AD0
forms the partial chip address and should be tied to
VA or AGND as required. The upper 6 bits of the
7-bit address field must be 001000. To communicate with the CS43L41 the LSB of the chip address
field, which is the first byte sent to the CS43L41,
should match the setting of the AD0 pin. The eighth
bit of the address byte is the R/W bit (high for a
read, low for a write). If the operation is a write, the
next byte is the Memory Address Pointer, MAP,
which selects the register to be read or written. The
MAP is then followed by the data to be written. If
the operation is a read, then the contents of the register pointed to by the MAP will be output after the
chip address.
The CS43L41 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
For more information on I2C, please see “The I2CBus Specification: Version 2.0”, listed in the References section.
* The MCLK is required for both control port interfaces.
The CS43L41 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
26
DS473PP1
Confidential Draft
9/23/99
7.3
CS43L41
MEMORY ADDRESS POINTER (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (Auto MAP Increment Enable)
Default = ‘0’.
0 - Disabled
1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = ‘000’.
CS
CCLK
CHIP
ADDRESS
CDIN
0010000
MAP
DATA
MSB
R/W
byte 1
LSB
byte n
MAP = Memory Address Pointer
Figure 7. SPI Mode Control Port Formatting
Note 1
SDA
001000
ADDR
AD0
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. I2C Mode Control Port Formatting
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27
CS43L41
Figure 9. Base-Rate Stopband Rejection
Figure 10. Base-Rate Transition Band
Figure 11. Base-Rate Transition Band (Detail)
Figure 12. Base-Rate Passband Ripple
Figure 13. High-Rate Stopband Rejection
28
Figure 14. High-Rate Transition Band
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CS43L41
Figure 15. High-Rate Transition Band (Detail)
Figure 16. High-Rate Passband Ripple
3.3 µF
AOUTx
+
V
out
R
C
L
L
AGND
75
100
70
75
Safe Operating
Region
50
25
2.5
3
65
HR
M
60
55
5
10
15
Resistive Load -- RL (kΩ)
Figure 18. Maximum Loading
DS473PP1
BR
M
125
Power (mW)
Capacitive Load -- C L (pF)
Figure 17. Output Test Load
20
50
30
40
50
60
70
80
Sample Rate (kHz)
90
100
Figure 19. Power vs. Sample Rate (VA = 5V)
29
CS43L41
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
I2S, Up to 24-Bit data and INT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 20. CS43L41 Format 0 (I2S)
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
I2
S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2
S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 21. CS43L41 Format 1 (I2S)
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
Left Justified, up to 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit DataData Valid on Rising
Edge of SCLK
Figure 22. CS43L41 Format 2
30
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CS43L41
LRCK
Right Channel
Left Channel
SCLK
SDATA
0
23 22 21 20 19 18
7 6 5 4 3 2 1 0
23 22 21 20 19 18
7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 24-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 48 Cycles per LRCK
Period
Figure 23. CS43L41 Format 3
LRCK
Right Channel
Left Channel
SCLK
SDATA
1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 20-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 20-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 40 Cycles per LRCK
Period
Figure 24. CS43L41 Format 4
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit DataINT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 16-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 32 Cycles per LRCK
Period
Figure 25. CS43L41 Format 5
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31
CS43L41
LRCK
Right Channel
Left Channel
SCLK
SDATA
1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 18-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 18-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 36 Cycles per LRCK
Period
Figure 26. CS43L41 Format 6
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 27. De-Emphasis Curve
A Channel
Volume
Control
Left Channel
Audio Data
Σ
Right Channel
Audio Data
MUTE
AoutA
MUTE
AoutB
Σ
B Channel
Volume
Control
Figure 28. ATAPI Block Diagram
32
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CS43L41
8.
PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
9.
REFERENCES
1) “How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB43L41 Evaluation Board Datasheet
3) “The I2C Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
DS473PP1
33
CS43L41
10. PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.034
0.008
0.193
0.248
0.169
-0.020
0°
MILLIMETERS
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
0.026
0.028
8°
MIN
-0.05
0.85
0.19
4.90
6.30
4.30
-0.50
0°
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
0.65
0.70
8°
NOTE
2,3
1
1
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
34
DS473PP1
• Notes •
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