CS5396-KS

CS5396 CS5397 120 dB, 96 kHz Audio A/D Converter Features l 24-Bit General Description The CS5396 and CS5397 are complete analog-to-digital converters for stereo digital audio systems. They perform sampling, analog-to-digital conversion and antialias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 100 kHz per channel. The CS5396/97 use a patented 7th-order, tri-level deltasigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADCs use a differential architecture which provides excellent noise rejection. The CS5396 has a linear phase filter optimized for audio applications with ±0.005 dB passband ripple and >117 dB stopband rejection. The CS5397 has a nonaliasing filter response with ±0.005 passband ripple and >117 dB stopband attenuation. Other features available in both the CS5396 and CS5397 are an optional low group delay filter and a unique psychoacoustic noise shaping filter which subjectively truncates the output to 16, 18 or 20 bits while 24-bit sound quality is preserved. The CS5396/97 are targeted for the highest performance professional audio systems requiring wide dynamic range, negligible distortion and low noise. ORDERING INFORMATION CS5396-KS -10° to 50° C CS5397-KS -10° to 50° C CDB5396/97 VCOM MCLKA ADCTL DACTL CAL SCLK LRCK SDATA1 SDATA2 MCLKD Conversion l 120 dB Dynamic Range (A-Weighted) l Low Noise and Distortion >105 dB THD + N l Complete CMOS Stereo A/D System Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference l CS5396 - digital filter optimized for audio l CS5397 - non-aliasing digital filter l Adjustable System Sampling Rates including 32, 44.1, 48 & 96 kHz l Differential Analog Architecture l Linear Phase Digital Anti-Alias Filtering l 10 Tap Programmable Psychoacoustic Noise Shaping Filter l Single +5 V Power Supply 28-pin SOIC 28-pin SOIC Evaluation Board VREF Voltage Reference Serial Output Interface Serial Control Port CS CDIN CCLK AINLAINL+ S/H + - LP Filter + - DAC AINRAINR+ S/H DAC Comparator Digital Decimation Filter (with Low Group Delay Options) Digital Decimation Filter (with Low Group Delay Options) Calibration Microcontroller Psychoacoustic Filter + - LP Filter + - Comparator Calibration SRAM VA AGND1 AGND2 AGND0 VL LGND TST0 TST1 VD DGND Preliminary Product Information Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 1997 (All Rights Reserved) SEP ‘97 DS229PP2 1 CS5396 CS5397 TABLE OF CONTENTS TABLE OF CONTENTS.......................................................................................................2 ANALOG CHARACTERISTICS ..........................................................................................4 DIGITAL FILTER CHARACTERISTICS ..............................................................................5 POWER AND THERMAL CHARACTERISTICS .................................................................6 DIGITAL CHARACTERISTICS............................................................................................6 ABSOLUTE MAXIMUM RATINGS......................................................................................6 RECOMMENDED OPERATING CONDITIONS ..................................................................7 SWITCHING CHARACTERISTICS .....................................................................................7 SPI CONTROL PORT SWITCHING CHARACTERISTICS.................................................9 I2C CONTROL PORT SWITCHING CHARACTERISTICS ...............................................10 GENERAL DESCRIPTION ...............................................................................................12 Stand-Alone vs. Control Port Mode ........................................................................12 STAND-ALONE MODE ....................................................................................................12 Master Clock - Stand-Alone Mode ..........................................................................12 Serial Data Interface - Stand-Alone Mode ..............................................................12 Serial Data- Stand-Alone Mode .......................................................................13 Serial Clock - Stand-Alone Mode ....................................................................13 Left/Right Clock - Stand-Alone Mode ..............................................................13 Master Mode - Stand-Alone Mode ..........................................................................13 Slave Mode - Stand-Alone Mode ............................................................................13 High Pass Filter - Stand-Alone Mode .....................................................................13 Power-up and Calibration - Stand-Alone Mode ......................................................13 Synchronization of Multiple Devices - Stand Alone Mode ......................................14 CONTROL PORT MODE ..................................................................................................14 Access to Control Port Mode ..................................................................................14 Internal Power-On Reset .................................................................................14 Master Clock - Control Port Mode ..........................................................................15 64× vs. 128× Oversampling Modes ........................................................................15 Serial Data Interface - Control Port Mode ..............................................................15 Serial Data - Control Port Mode ......................................................................15 Serial Clock - Control Port Mode .....................................................................15 Left/Right Clock -Control Port Mode ................................................................15 Master Mode- Control Port Mode ...........................................................................17 Slave Mode - Control Port Mode ............................................................................17 Synchronization of Multiple Devices - Control Port Mode ......................................17 Power-up and Calibration - Control Port Mode .......................................................17 High Pass Filter -Control Port Mode .......................................................................17 Input Level Monitoring - Control Port Mode ............................................................18 High Resolution Mode .....................................................................................18 Bar Graph Mode ..............................................................................................18 Dual Digital Audio Outputs .....................................................................................18 Psychoacoustic Filter ..............................................................................................19 Low Group Delay Filter ...........................................................................................19 µC Interface Formats ..............................................................................................19 SPI Mode .........................................................................................................19 I2C Mode .........................................................................................................19 Establishing the Chip Address in I2C Mode ....................................................19 ANALOG CONNECTIONS - ALL MODES .......................................................................19 GROUNDING AND POWER SUPPLY DECOUPLING - ALL MODES ............................20 DIGITAL FILTER PLOTS .................................................................................................21 REGISTER DESCRIPTION ...............................................................................................25 PIN DESCRIPTIONS .........................................................................................................31 Power Supply Connections .....................................................................................31 Analog Inputs...........................................................................................................31 Analog Outputs........................................................................................................32 Digital Inputs............................................................................................................32 2 DS229PP2 CS5396 CS5397 Digital Input Pin Definitions for Stand-Alone MODE ............................................... 32 Digital Pin Definitions for CONTROL-PORT MODE................................................ 33 Digital Outputs......................................................................................................... 33 Digital Inputs or Outputs.......................................................................................... 34 Miscellaneous ......................................................................................................... 34 PARAMETER DEFINITIONS............................................................................................. 35 ADDITIONAL INFORMATION........................................................................................... 36 PACKAGE DIMENSIONS ................................................................................................. 37 DS229PP2 3 CS5396 CS5397 ANALOG CHARACTERISTICS (TA = 25°C; VA, VL,VD = 5V; Full-scale Input Sinewave, 997 Hz; Analog connections as shown in Figure 1; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD; Parameter Symbol Dynamic Performance Dynamic Range MCLK equal to 24.576 MHz Fs = 48 kHz in 128x Oversampling Mode (A-weighted) Fs = 48 kHz in 128x mode Fs = 96 kHz in 64x mode (A-weighted) Fs = 96 kHz in 64x mode (40 kHz Bandwidth) MCLK equal to 12.288 MHz Fs = 48 kHz in 64x mode (A-weighted) Fs = 48 kHz in 64x mode Total Harmonic Distortion + Noise THD+N Fs = 48 kHz in 128x mode -1 dB (Note 1) -20 dB (Note 1) -60 dB (Note 1) Fs = 96 kHz in 64x mode -1 dB (Note 1) (40 kHz bandwidth) -20 dB (Note 1) -60 dB (Note 1) Fs = 48 kHz in 64x mode -1 dB (Note 1) -20 dB (Note 1) -60 dB (Note 1) Total Harmonic Distortion -1 dB (Note 1) THD Interchannel Phase Deviation Interchannel Isolation Dynamic Range Performance Drift (following calibration) dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error (With high pass filter enabled) Analog Input VIN Full-scale Differential Input Voltage (Note 2) ZIN Input Impedance Differential Common-mode Common-Mode Rejection Ratio CMRR Notes: 1. Referenced to typical full-scale differential input voltage (4.0 Vpp). 2. Specified for a fully differential input ±{(AINR+)-(AINR-)}.The ADC accepts input voltages up to the analog supplies (VA and AGND). Full-scale outputs will be produced for differential inputs beyond VIN. * Refer to Parameter Definitions at the end of this data sheet. Specifications are subject to change without notice. Min TBD TBD TBD TBD TBD TBD Typ Max Units 120 117 120 114 117 114 105 97 57 105 97 57 105 97 57 0.00056 0.0001 120 0.05 0.05 ±5 ±100 0 4 4.5 TBD 82 TBD TBD - dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % deg dB dB/°C dB % ppm/°C LSB Vpp kΩ kΩ dB TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - 4 DS229PP2 CS5396 CS5397 DIGITAL FILTER CHARACTERISTICS Parameter (TA = 25 °C; VA, VL,VD = 5V ± 5%; Fs = 48 kHz) CS5396 Symbol Min 0 0.5542 117 tgd ∆tgd 0 0 0.646 0.323 86 tgd ∆tgd (Note 3) (Note 3) (Note 3) 34/Fs 34/Fs 10/Fs 1.8 20 5.3 0.0 0 0.0 0.375 0.188 0.015 0 0 34/Fs 34/Fs 10/Fs 1.8 20 5.3 0.0 0 0.0 0.375 0.188 0.015 127.35 63.68 Typ Max 0.4604 ±0.005 Min 0 117 CS5397 Typ Max 0.3958 ±0.005 63.50 Unit Fs dB Fs dB µs µs µs Fs Fs dB Fs Fs dB µs µs Hz Hz Deg dB High-Performance Filter Passband(-0.01 dB) Passband Ripple Stopband Stopband Attenuation Group Delay (Fs = Output Sample Rate) 128x Oversampling Mode 64x Oversampling Mode Group Delay Variation vs. Frequency 63.45 0.4979 Low Group Delay Filter Passband(-0.01 dB) 128x Oversampling Mode 64x Oversampling Mode Passband Ripple Stopband 128x Oversampling Mode 64x Oversampling Mode Stopband Attenuation Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency 127.35 0.646 63.68 0.323 86 - High Pass Filter Characteristics Frequency Response-3.0 dB -0.036 dB Phase Deviation@ 20Hz Passband Ripple Notes: 3. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS229PP2 5 CS5396 CS5397 POWER AND THERMAL CHARACTERISTICS (TA = 25 °C; VA, VL,VD = 5V±5%; Fs = 48 kHz; Master Mode) 64X oversampling MCLK=12.288 MHz Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) Power Consumption(Normal Operation) (Power-Down Mode) Power Supply Rejection Ratio (1 kHz) Allowable Junction Temperature Junction to Ambient Thermal Impedance TJA PSRR VA+VL VD VA+VL VD Symbol IA ID IA ID Min Typ 150 65 2 2 1075 20 65 45 Max TBD TBD TBD 135 128X oversampling MCLK=24.576 MHz Min Typ 160 125 3 3.5 1425 33 65 45 Max TBD TBD TBD 135 Unit mA mA mA mA mW mW dB °C °C/W DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = -20 µA Low-Level Output Voltage at Io = 20 µA Input Leakage Current (TA = 25 °C; VA, VL,VD = 5V ± 5%) Symbol VIH VIL VOH VOL Iin Min 2.4 VD - 1.0 Typ Max 0.8 0.4 ±10 Units V V V V µA ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, All voltages with respect to ground.) Parameter DC Power Supplies: Analog Logic Digital |VA - VD| (Note 6) |VA - VL| (Note 6) |VD - VL| (Note 6) (Note 4) (Note 5) (Note 5) Symbol VA VL VD Min -0.3 -0.3 -0.3 Typ Max +6.0 +6.0 +6.0 0.4 0.4 0.4 Units V V V V V V Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature Iin VIN VIND TA Tstg AGND-0.7 -0.3 -55 -65 - ±10 VA+0.7 VD+0.7 +50 +150 mA V V °C °C Notes: 4. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 5. The maximum over/under voltage is limited by the input current. 6. Applies to normal operation. Greater differences during power up/down will not cause SCR latch-up. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS229PP2 CS5396 CS5397 RECOMMENDED OPERATING CONDITIONS to ground.) Parameter Positive Digital Positive Logic Positive Analog |VA - VD| (Note 6) Ambient Operating Temperature (Power Applied) DC Power Supplies: Symbol VD VL VA Min 4.75 4.75 4.75 -10 Typ 5.0 5.0 5.0 Max 5.25 5.25 5.25 0.4 +50 Units V V V V °C (AGND, DGND = 0V, all voltages with respect TA Specifications are subject to change without notice. SWITCHING CHARACTERISTICS (TA = 25 °C; VA = 5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VA = VD; CL = 20 pF) Parameter Output Sample Rate MCLK Period MCLK Low MCLK High MCLK Fall Time Master Mode SCLK falling to LRCK SCLK falling to SDATA valid SCLK duty cycle Slave Mode LRCK Period LRCK duty cycle SCLK Period SCLK Pulse Width Low SCLK Pulse Width High SCLK falling to SDATA valid LRCK edge to MSB valid SCLK rising to LRCK edge delay LRCK edge to rising SCLK setup time Symbol Fs tclkw tclkl tclkh tclkft tmslr tsdo Min 2 39.06 26 26 -20 10 4 x tclw 2 x tclw 60 tclw + 20 ns tclw + 20 ns Typ 50 50 Max 100 1950 8 +20 20 500 tclw + 20 ns tclw + 20 ns Units kHz ns ns ns ns ns ns % µs % ns ns ns ns ns ns ns 1/Fs tsclkw tsclkl tclkh tdss tlrdss tslr1 tslr2 DS229PP2 7 CS5396 CS5397 t slr1 t slr2 t sclkh t sclkl SCLK output t mslr LRCK output t sdo SDATA MSB MSB-1 SCLK input t sclkw LRCK input t lrdss SDATA MSB MSB-1 t dss MSB-2 SCLK to SDATA & LRCK - MASTER mode Serial Data Format, Left Justified SCLK to LRCK & SDATA - SLAVE mode Serial Data Format, Left Justified t slr1 t slr2 SCLK output t mslr LRCK output t sdo SDATA MSB t sclkh t sclkl SCLK input t sclkw LRCK input t dss SDATA MSB MSB-1 SCLK to SDATA & LRCK - MASTER mode Serial Data Format, I2S compatible SCLK to LRCK & SDATA - SLAVE mode Serial Data Format, I2S compatible 8 DS229PP2 CS5396 CS5397 SPI CONTROL PORT SWITCHING CHARACTERISTICS Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 20 pF) Parameter Symbol fsck tcsh tcss tscl tsch tdsu (Note 7) (Note 8) (Note 8) tdh tr2 tf2 Min 1.0 20 66 66 40 15 Max 6 100 100 Unit MHz µs ns ns ns ns ns ns ns (TA = 25 °C; VD, VA = 5V ±5%; SPI Mode CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: 7. Data must be held for sufficient time to bridge the transition time of CCLK. 8. For FSCK < 1 MHz. CS t css CCLK t r2 CDIN t scl t sch t csh t f2 t dsu t dh DS229PP2 9 CS5396 CS5397 I2C CONTROL PORT SWITCHING CHARACTERISTICS Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 20 pF) Parameter Symbol Min 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 Unit kHz µs µs µs µs µs µs ns µs ns µs (TA = 25 °C; VD, VA = 5V ±5%; I2C® Mode (Note 9) fscl tbuf thdst tlow thigh tsust (Note 10) thdd tsud tr tf tsusp CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition CDIN Hold Time from CCLK Falling CDIN Setup Time to CCLK Rising Rise Time of Both CDIN and CCLK Lines Fall Time of Both CDIN and CCLK Lines Setup Time for Stop Condition Notes: 9. Use of the I2C® bus interface requires a license from Philips. 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Stop CDIN t buf Start Repeated Start Stop t hdst t high t hdst tf t susp CCLK t t t sud t sust tr low hdd 10 DS229PP2 CS5396 CS5397 +5V Analog + 1 µF 0.1 µF 24 1 470 µF + 0.1 µF 2 100 µF 0.1 µF 5Ω 23 VL 0.1 µF + +5V Digital 1 µF 11 VD CS/PDN CDIN/DFS 19 18 17 10 16 15 µ-Controller/ Configuration VA VREF CCLK/SM VCOM CAL SDATA1 AINL+ + 0.1 µF Left Analog Input + 4 39 Ω 6.8nF 39 Ω Left Analog Input Right Analog Input + 27 39 Ω CS5396/7 A/D CONVERTER SDATA2 Audio Data Processor 5 13 LRCK SCLK MCLKA MCLKD 20 9 14 Timing Logic & Clock AINL- 7 AINR+ DACTL 26 AINRADCTL TSTO1 TSTO2 AGND0 LGND DGND AGND1 AGND2 3 22 12 28 25 6 8 21 TSTO pins should be left floating, with no trace attached 6.8nF 39 Ω Right Analog Input - Figure 1. Typical Connection Diagram DS229PP2 11 CS5396 CS5397 GENERAL DESCRIPTION The CS5396/97 is a 24-bit, stereo A/D converter designed for stereo digital audio applications. The analog input channels are simultaneously sampled by separate, patented, 7th-order tri-level delta-sigma modulators at either 128 or 64 times the output sample rate (64× Fs or 128× Fs) of the device. The resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (Fs) of up to 100 kHz. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters, and it does not require external sample-and-hold amplifiers or voltage references. Only normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for antialiasing are required, as shown in Figure 1. An onchip voltage reference provides for a differential input signal range of 4.0 Vpp. The device also contains a high pass filter, implemented digitally after the decimation filter, to completely eliminate any internal offsets in the converter or any offsets present at the input circuitry to the device. Output data is available in serial form, coded as 2’s complement 24-bit numbers. For more information on delta-sigma modulation techniques see the references at the end of this data sheet. • • • • • • • • 128× Oversampling Mode Reduction of 24-bit data to 20, 18 or 16-bit data with psychoacoustically optimized dither Programmability of psychoacoustic filter coefficients Peak Input Signal Level Monitor with either High Resolution or Bar Graph mode selection Signal inversion High pass filter defeat Mute Access to the digital filter to allow the input of external digital audio data to produce a two-toone decimated output and/or psychoacoustic bit reduction. STAND-ALONE MODE Master Clock - Stand-Alone Mode The master clock is the clock source for the deltasigma modulator sampling (MCLKA) and digital filters (MCLKD). The required MCLKA/D frequency is determined by the desired Fs and must be 256× Fs. Table 1 shows some common master clock frequencies. LRCK (kHz) 32 44.1 48 64 88.2 96 MCLKA/D (MHz) 8.192 11.2896 12.288 16.384 22.5792 24.576 SCLK (MHz) 2.048 2.822 3.072 4.096 5.6448 6.144 Stand-Alone vs. Control Port Mode The CS5396/97 can operate in either Stand-Alone or Control Port Mode. The functionality of pins 17, 18 and 19 is established upon entering either the Stand-Alone or Control Port mode, as described in the Pin Description section. The Control Port Mode requires a micro-controller and allows access to many additional features, which include: Table 1. Common Clock Frequencies for Stand-Alone Mode Serial Data Interface - Stand-Alone Mode The CS5396/97 supports two serial data formats which are selected via the digital format select pin, DFS. The digital output format determines the relationship between the serial data, left/right clock and serial clock. Figures 2 and 3 detail the interface forDS229PP2 12 CS5396 CS5397 mats. The serial data interface is accomplished via the serial data outputs; SDATA1 and SDATA2; serial data clock, SCLK, and the left/right clock, LRCK. The serial nature of the output data results in the left and right data words being read at different times. However, the samples within an LRCK cycle represent simultaneously sampled analog inputs. Internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 64× Fs and by 256 to generate a LRCK which is equal to Fs. The CS5396/97 is placed in the Master mode with the slave/master pin, S/M, low. Slave Mode - Stand-Alone Mode LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLKA/D and be equal to Fs. It is recommended that SCLK be equal to 64×. Other frequencies between 48× and 128× Fs are possible but may degrade system performance due to interference effects. The master clock frequency must be 256× Fs. The CS5396/97 is placed in the Slave mode with the slave/master pin, S/M, high. Serial Data- Stand-Alone Mode The serial data block consists of 24 bits of audio data presented in 2’s-complement format with the MSB-first. The data is clocked from SDATA1 and SDATA2 by the serial clock and the channel is determined by the Left/Right clock. The full precision 24-bit data is available on SDATA1 and the output from the low group delay filter is available on SDATA2. High Pass Filter - Stand-Alone Mode The CS5396/97 includes a high pass filter after the decimator to remove the DC offsets introduced by the analog buffer stage and the CS5396/97 analog modulator. The characteristics of this first-order high pass filter are outlined below, for Fs equal to 48 kHz. This filter response scales linearly with sample rate. Frequency response: -3 dB @ 1.8 Hz -0.036 dB @ 20 Hz Phase deviation: 5.3 degrees @ 20 Hz Passband ripple: None Serial Clock - Stand-Alone Mode The serial clock shifts the digitized audio data from the internal data registers via the SDATA1 and SDATA2 pins. SCLK is an output in Master Mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64× Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48× and 128× Fs. However, it is recommended that SCLK be equal to 64×, though other frequencies are possible, to avoid potential interference effects which may degrade system performance. Power-up and Calibration - Stand-Alone Mode The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exiting the power-down mode. However, the voltage reference will take a much longer time to reach a final value due to the presence of external capacitance on the VREF pin. A time delay of approximately 10ms/µF is required after applying power to the device or after exiting a power down state. Left/Right Clock - Stand-Alone Mode The Left/Right clock, LRCK, determines which channel, left or right, is to be output on SDATA1 and SDATA2. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to MCLKA/D. Master Mode - Stand-Alone Mode In Master mode, SCLK and LRCK are outputs which are internally derived from the master clock. DS229PP2 13 CS5396 CS5397 A calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external VREF capacitor to settle. This is required to minimize noise and distortion. It is also advised that the CS5396/97 be calibrated after the device has reached thermal equilibrium, approximately 10 seconds, to maximize performance. CONTROL PORT MODE Access to Control Port Mode The mode selection between Stand-Alone and Control Port Mode is determined by the state of the SDATA1 pin 250 MCLK cycles following the internal power-on reset. A 47 kΩ pull-up resistor on SDATA1 will select the Control Port Mode. However, the control port will not respond to CCLK and CDIN until the pull-up on the SDATA1 pin is released. Synchronization of Multiple Devices Stand Alone Mode In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. It is recommended that the rising edge of the CAL signal be timed with a falling edge of MCLK to ensure that all devices will initiate a calibration and synchronization sequence on the same rising edge of MCLK. The absence of re-timing of the CAL signal can result in a sampling difference of one MCLK period. Internal Power-On Reset The timing required to determine Control port mode and I2S/SPI mode is based on an internal power-on reset. The internal power-on reset requires the power supply to exceed a threshold voltage. However, there is no external indication of when the internal reset is activated. If precise timing of the Control port and I2S/SPI decisions is required, MCLK should not be applied until the power supply has stabilized. LRCK Left Right SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs Figure 2. Serial Data Format 0, Stand-Alone Mode, DFS low. Left Justified. LRCK Left Right SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 MASTER I2S 24-Bit Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE I 2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs Figure 3. Serial Data Format 1, Stand-Alone Mode, DFS High. I2S compatible 14 DS229PP2 CS5396 CS5397 Master Clock - Control Port Mode The master clock is the clock source for the deltasigma modulator sampling (MCLKA) and digital filters (MCLKD). The required MCLKA/D frequency is determined by the desired Fs and the chosen Oversampling Mode. Table 2 shows some common master clock frequencies. clock. Figures 4 - 7 detail the interface formats. The serial data interface is accomplished via the serial data outputs; SDATA1 and SDATA2, serial data clock, SCLK, and the left/right clock, LRCK. The serial nature of the output data results in the left and right data words being read at different times. However, the samples within an LRCK cycle represent simultaneously sampled analog inputs. 64× vs. 128× Oversampling Modes The CS5396/97 can operate in a 64× Oversampling Mode with a 256× master clock (MCLKA/D) at a maximum sample rate of 100 kHz. The device can also operate in a 128× Oversampling Mode with a 512× master clock (MCLKA/D) where the maximum Fs is 50 kHz. Notice that the required master clock is 24.576 MHz for Fs equal to either 48 kHz in the 128× Oversampling Mode or 96 kHz in the 64× Oversampling Mode. The sampling mode is set via the control register which alters the decimation ratio of the digital filter. The 64× Oversampling Mode is the default mode. Table 2 shows some common clock frequencies for both modes. Refer to Appendix A for additional discussion of 64× vs. 128× Oversampling Modes. LRCK (kHz) 32 44.1 48 32 44.1 48 64 88.2 96 Oversampling 64 64 64 128 128 128 64 64 64 MCLKA/D (MHz) 8.192 11.2896 12.288 16.384 22.5792 24.576 16.384 22.5792 24.576 SCLK (MHz) 2.048 2.822 3.072 4.096 5.6448 6.144 4.096 5.6448 6.144 Serial Data - Control Port Mode The serial data block is presented in 2’s-complement format with the MSB-first. The data is clocked from SDATA1 and SDATA2 by the serial clock and the channel is determined by the Left/Right clock. The full precision 24 bit data is available on SDATA1 and the output from the low group delay is available on SDATA2. The serial data can be followed by 8 Peak Signal Level, PSL, bits as shown in Figures 4 - 7 if the PKEN bit is set. Refer to the Dual Audio Output section of this data sheet for further discussion of SDATA1 and SDATA2 options. Serial Clock - Control Port Mode The serial clock shifts the digitized audio data from the internal data registers via SDATA1 and SDATA2. SCLK is an output in Master Mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64× Fs in the 64× Oversampling Mode. In the 128× Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 128× Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48× and 128× Fs. It is recommended that SCLK be equal to 64× in the 64× Oversampling Mode and equal to 128× in the 128× Oversampling Mode to avoid possible system performance degradation due to interference effects. Table 2. Common Clock Frequencies Serial Data Interface - Control Port Mode The CS5396/97 supports two serial data formats which are selected via the control register. The digital output format determines the relationship between the serial data, left/right clock and serial Left/Right Clock -Control Port Mode The Left/Right clock, LRCK, determines which channel, left or right, is to be output on SDATA1 DS229PP2 15 CS5396 CS5397 LRCK Left Right SCLK SDATA 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs Figure 4. Control Port Mode, Serial Data. Left Justified. 64x Oversampling Mode The peak signal level bits are available only if Bit 6 of Byte 7 is set. LRCK Left Right SCLK SDATA 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 MASTER I2S 24-Bit Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE I 2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs Figure 5. Control Port Mode, Serial Data. I2S Compatible. 64x Oversampling Mode. The peak signal level bits are available only if Bit 6 of Byte 7 is set. LRCK Left Right SCLK SDATA 23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0 23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0 23 22 MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 128x SCLK MCLK equal to 512x Fs SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 512x Fs Figure 6. Control Port Mode, Serial Data. Left Justified. 128x Oversampling Mode The peak signal level bits are available only if Bit 6 of Byte 7 is set. LRCK Left Right SCLK SDATA 23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0 23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0 23 22 MASTER I2S 24-Bit Data Data Valid on Rising Edge of 128x SCLK MCLK equal to 512x Fs SLAVE I2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 512x Fs Figure 7. Control Port Mode, Serial Data. I2S Compatible. 128x Oversampling Mode. The peak signal level bits are available only if Bit 6 of Byte 7 is set. 16 DS229PP2 CS5396 CS5397 and SDATA2. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to MCLKA/D. devices to have individual addresses, synchronization can be accomplished by; 1) Disable the address enable bit (ADDREN) in register 7 2) Issue a system broadcast FSTART command synchronized with CCLK. 3) Reset the ADDREN bit. Master Mode- Control Port Mode In Master mode, SCLK and LRCK are outputs which are internally derived from the master clock. In the 64× Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 64× Fs and by 256 to generate a LRCK which is equal to Fs. In the 128× Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 128× Fs and by 512 to generate a LRCK which is equal to Fs. The CS5396/97 is placed in the Master mode via the control register. Power-up and Calibration - Control Port Mode The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exiting the power-down mode. However, the voltage reference will take a much longer time to reach a final value due to the presence of external capacitance on the VREF pin. A time delay of approximately 10ms/µF is required after applying power to the device or after exiting a power down state. A calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external VREF capacitor to settle. This is required to minimize noise and distortion. It is also advised that the CS5396/97 be calibrated after the device has reached thermal equilibrium to maximize performance. A calibration sequence requires the following commands; 1) set the FSTART bit 2) set the GND CAL bit 3) set the CAL bit 4) Wait a minimum of 2050 LRCK periods in the 128x mode or 4100 LRCK periods in the 64x mode. 5) Remove GND CAL Slave Mode - Control Port Mode LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLKA/D and be equal to Fs. It is recommended that SCLK be equal to 64× in the 64× Oversampling Mode and equal to 128× in the 128× Oversampling Mode. Other frequencies are possible but may degrade system performance due to interference effects. The CS5396/97 is placed in the Slave mode via the control register. Synchronization of Multiple Devices Control Port Mode In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. The FSTART bit in register 1 controls the synchronization of the internal clocks and sampling process between the analog modulator and the digital filter. Multiple ADCs can be synchronized if the FSTART command is initiated on the same edge of MCLK. This can be accomplished by re-timing the CCLK clock with the falling edge of MCLK. This is a relatively simple matter if the ADCs have the same address. However, if the system requires the High Pass Filter -Control Port Mode The CS5396/97 includes a high pass filter after the decimator to remove the DC offsets introduced by 17 DS229PP2 CS5396 CS5397 the analog buffer stage and the CS5396/97 analog modulator. The high pass filter can be defeated with the control register. It is also possible to write to the left/right offset registers to establish a predetermined offset. The characteristics of this first-order high pass filter are outlined below for Fs equal to 48 kHz. The filter response scales linearly with sample rate. Frequency response: -3 dB @ 1.8 Hz -0.036 dB @ 20 Hz Phase deviation: 5.3 degrees @ 20 Hz Passband ripple: None P7 - Overrange 0 - Analog input less than full-scale level 1 - Analog input greater than full-scale P6 - Idle channel 0 - Analog input >-60 dB from full-scale 1 - Analog input