FTS375-010.0M

Available at Digi-Key www.digikey.com 125 Series FTS375 Disciplined Reference and Synchronous Clock Generator 2111 Comprehensive Drive Connor-Winfield’s GPS Disciplined Oscillators (GPSDOs) were Aurora, Illinois 60505 created specifically for all precision timing and synchronization applications requiring higher end, cost sensitive solutions. By combining our uniquely designed GPS timing receivers with our high-quality oscillators, Connor-Winfield is able to offer a wide variety of superior, cost-effective GPS timing solutions. The 125 Series modules provide customer applications with the precise timing capabilities needed to optimize critical system performance. Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com General Description The FTS375 module is a GPS driven, mixed-signal phase lock loop, providing a 1 PPS CMOS output from a Connor-Winfield GPS timing receiver. The FTS375 generates a 10 MHz CMOS and a 10 MHz SINE output from an intrinsically low jitter voltage controlled crystal oscillator. The FTS375 can lock to a 10 MHz reference derived from the on-board GPS receiver or an external 10 MHz reference or to an external 1 PPS reference. Alarms are provided to indicate Loss-of-Lock, Holdover, and Antenna Fault. The on-board GPS receiver requires an outdoor mounted GPS antenna for the best stability and consistent performance. The mode control inputs are used to manually switch between references and/or holdover. The user application should monitor the alarm outputs and manually switch modes as needed. Serial I/O lines provide access to the NMEA messages from the GPS receiver (referenced in the Connor-Winfield’s Wi125 User Manual. Contact Connor-Winfield Sales for a copy). The serial I/O lines can be used to access GPS timestamp information, or to verify that the receiver has recovered from an alarm condition. The reset is used to reset the GPS receiver (if needed). D A T A Features • Phase locked 10 MHz output • 1 PPS output • 3 selectable references: GPS, External 10 MHz or External 1 PPS • Holdover • Three alarm outputs. (Loss-of-Lock, Holdover and Antenna Fault) • Serial input and output ports (GPS receiver) • Master reset • +3.3 Volt power supply • Commercial Temp (0-70° C) • Mechanical Dimensions: 3.937” x 1.969” x 0.708” (100mm x 50mm x 17.98mm) • Package: 36-pin Through-Hole • Fixed Position Unit S H E E T Functional Block Diagram Figure 1 OCXO REFERENCE FTS375 Module SERIAL OUTPUT (A, B) MCX Connector BOOT SEL HOLDOVER STATUS LOCK STATUS ANTENNNA FAULT STATUS Wi125 (GPS Receiver) 1 PPS CMOS OUTPUT SERIAL IN (A, B) 33Ω 1 PPS ∆ GPS REF 10 MHz REF LOW JITTER DPFD 1 PPS REF RESET Bulletin Revision Date SG174 03 20 Oct 16 SYNC 1 CONTROL SYNC 2 CONTROL DISABLE JTAG (Programming Only) CPLD ANALOG FILTER OCVCXO 1/N DRIVER 33Ω DRIVER & TRANSLATION 10 MHz CMOS OUTPUT 10 MHz SINE OUTPUT Pin Description Table 1 Pin # 1 Pin Name 1 PPS Ref Input 2 GND 3 10 MHz Ref Input Description Ground Externally provided LVCMOS 10 MHz reference 4 No Connect Used for factory programming 5 10 MHz CMOS Output 10 MHz low jitter CMOS output 6 GND 7 10 MHz Sine Output 8 No Connect Used for factory programming 9 No Connect Used for factory programming 10 No Connect Used for factory programming 11 *Reset 12 TXA RS-232 transmit signal for UART0 13 TXB RS-232 transmit signal for UART1 14 GND Ground 15 RXA RS-232 receive signal for UART0 16 RXB RS-232 receive signal for UART1 17 GND Ground 18 *Bootsel 19 GND 20 Antenna Supply Voltage 21 Vcc1 3.3V supply voltage for the GPS circuitry 22 GND Ground 23 Unused 24 Unused 27 Antenna Fault Status Note Externally provided LVCMOS 1 PPS reference Ground 10 MHz AC coupled low jitter SINE output Pull low to reset GPS receiver Normally high. Pull low to reprogram the GPS receiver Ground Antenna Supply voltage. Limit continuous current to 45mA Spare CPLD connection Spare CPLD connection High = A fault has been detected on pin 20 (Ant Supply Voltage) 28 1 PPS Out 29 Lock Status 1 PPS CMOS output 30 Holdover Status High = Unit is in holdover 31 SYNC2 Control Lock mode control signal 32 SYNC1 Control Lock mode control signal High = Unit is locked to the selected reference 33 Unused Spare CPLD connection 34 *Disable Pull low to disable the 10 MHz CMOS and SINE outputs 35 GND Ground 36 Vcc2 3.3V supply voltage for PLL and interfacing circuitry Note: Vcc1 and Vcc2 should not be connected; otherwise phase noise performance will degrade. FTS375 Data Sheet #: SG174 Page 2 of 8 Rev: 03 Date: 10/20/16 Specifications subject to change without notification. See Connor-Winfield’s website for latest revision. All dimensions in inches. © Copyright 2016 The Connor-Winfield Corporation Not intended for life support applications. Absolute Maximum Rating Table 2 Symbol Parameter Minimum Maximum Units N otes VCC Power Supply Voltage -0.3 3.7 Volts 1 VIN Input Voltage -0.3 4.6 Volts 1 VPREAMP Antenna Supply Voltage 2.7 13.2 Volts 1 TS Storage Temperature -30 80 °C 1 Operating Specifications Table 3 Symbol Parameter VCC1 Supply Voltage 1 ICC1 Supply Current 1 VCC2 Supply Voltage 2 ICC2 Supply Current 2 TO Temperature Range tJTOL Input Jitter Tolerance tAQ_GPS GPS Input Acquisition Time Minimum Nominal Maximum 3.135 3.3 3.465 V .480 1.2 A 3.135 3.3 3.465 V .380 1.0 A 0 70 °C 30 ns 150 sec 3 120 sec 3 tAQ_EXT External Input Acquisition Time Oscillator Performance FCAP Capture/Pull-in Range ±45 ppb FBW Jitter Filter Bandwidth 0.1 Hz Typ. DC Duty Cycle 45/55% RMS RMS Phase Noise 10 Hz - 2 MHz 12 kHz - 2 MHz 1 ps Typ. 0.6 ps Typ. Holdover/Wander Generation Performance TSTA Temperature Stability ±20 ppb VSTA Vcc Stability ±5 ppb ADAILY Daily Aging 2 ppb AYEARLY Yearly Aging 80 ppb Wander Generation Specification ETSI-PRC Units Notes 2 4 NOTES: 1. Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the module. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “Operating Specifications” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. Requires external regulation and supply decoupling. 3. Cold Power-up. 4. Holdover will be re-calculated with each successful lock. Yearly aging represents 1 continuous year in Holdover. Mode Control Table Table 4 SYNC 1 0 0 1 1 SYNC 2 0 1 0 1 Operating Mode Force Holdover Lock to External 10 MHz reference* Lock to External 1 PPS reference (Default) Lock to GPS Signal * Note: Holdover is not supported in this mode; loss of the 10 MHz reference will rail the PLL output until the reference returns or another mode is selected FTS375 Data Sheet #: SG174 Page 3 of 8 Rev: 03 Date: 10/20/16 Specifications subject to change without notification. See Connor-Winfield’s website for latest revision. All dimensions in inches. © Copyright 2016 The Connor-Winfield Corporation Not intended for life support applications. Input And Output Characteristics Table 5 LVCMOS Inputs and Outputs Minimum Maximum Symbol Parameter VIH High Level Input Voltage 1.7 4.0 V VIL Low Level Input Voltage -0.5 0.8 V VOH High Level Output Voltage 2.4 V VOL Low Level Output Voltage 0.4 V CO Output Capacitance 10 pF Symbol Parameter Load Output Power Total Harmonic Distortion 10MHz Sine Output Typical Units Units 50 ohms 9 dBm 2.2 % Notes Notes GPS Receiver Specifications Table 6 Parameter Specifications Acquisition/Tracking Sensitivity -155dBm/-156dBm Notes Acquisition Time: Hot Start w/ Network Assist Outdoor: