7C192-15

92 CY7C192 64K x 4 Static RAM with Separate I/O Features • High speed — 12 ns • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected pansion is provided by active LOW Chip Enable (CE) and three-state drivers. It has an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and write enable (WE) inputs are both LOW. Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW while the Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins. The output pins stay in high-impedance state when Write Enable (WE) is LOW, or Chip Enable (CE) is HIGH. A die coat is used to insure alpha immunity. Functional Description The CY7C192 is a high-performance CMOS static RAM organized as 65,536 x 4 bits with separate I/O. Easy memory ex- Logic Block Diagram I0 I1 I2 I3 INPUT BUFFER Pin Configurations DIP/SOJ Top View A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I0 I1 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 I3 I2 O3 O2 O1 O0 WE C191–2 A9 A10 A11 A12 A13 A14 A15 I0 I1 LCC Top View A8 A7 A6 V CC A5 3 2 1 28 27 4 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 18 1314151617 CE GND WE O0 O1 A4 A3 A2 A1 A0 I3 I2 O3 O2 C191–3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER O0 SENSE AMPS 1024 x 64 x 4 ARRAY O1 O2 O3 COLUMN DECODER POWER DOWN A10 A11 A12 A13 A14 A15 CE 7C192 ONLY WE C191–1 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C192-12 12 155 30 7C192-15 15 145 30 7C192-20 20 135 30 7C192-25 25 115 30 Cypress Semiconductor Corporation Document #: 38-05047 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C192 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................... −0.5V to VCC + 0.5V DC Input Voltage[1].................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range 7C192-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE PowerDown Current— TTL Inputs Automatic CE PowerDown Current—CMOS Inputs [1] 7C192-15 Min. 2.4 Max. 0.4 2.2 −0.5 −5 −5 VCC + 0.3V 0.8 +5 +5 −300 145 30 Unit V V V V µA µA mA mA mA Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 Max. 0.4 2.2 −0.5 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f=0 −5 −5 VCC + 0.3V 0.8 +5 +5 −300 155 30 ISB2 10 10 mA Notes: 1. Minimum voltage is equal to − 2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05047 Rev. ** Page 2 of 10 CY7C192 Electrical Characteristics Over the Operating Range 7C192-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX CE > VCC – 0.3V, VIN ≤ VCC – 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.2 −0.5 −5 −5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 135 30 15 2.2 −3.0 −5 −5 Max. 7C192-25 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 115 30 15 Max. Unit V V V V µA µA mA mA mA mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 10 Unit pF pF AC Test Loads and Waveforms[5] 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω R1 481Ω ALL INPUT PULSES 3.0V GND 10% < tr 90% 90% 10% < tr C191–5 (a) (b) C191–4 THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tr = < 3 ns for the -12 and -15 speeds. T.r = < 5 ns for the -20 and slower speeds. Document #: 38-05047 Rev. ** Page 3 of 10 CY7C192 Switching Characteristics Over the Operating Range[6] 7C192-12 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[7] CE HIGH to High Z[7,8] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z (7C192)[7] WE LOW to High Z (7C192)[7,8] WE LOW to Data Valid (7C191) Data Valid to Output Valid (7C191) CE LOW to Data Valid (7C191) 12 9 9 0 0 8 8 0 3 7 12 12 12 0 12 3 5 0 15 3 12 3 7 0 20 12 12 3 15 3 9 0 25 15 15 3 20 3 11 20 20 3 25 25 25 ns ns ns ns ns ns ns ns Description Min. Max. 7C192-15 Min. Max. 7C192-20 Min. Max. 7C192-25 Min. Max. Unit WRITE CYCLE[9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tDWE tADV tDCE 15 10 10 0 0 9 9 0 3 7 15 15 15 20 15 15 0 0 15 10 0 3 10 20 20 20 25 18 20 0 0 18 10 0 3 11 25 20 25 ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 through -25 speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZWE is less than tLZWE for any given device. These parameters are guaranteed by design and not 100% tested. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05047 Rev. ** Page 4 of 10 CY7C192 Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C191–6 Read Cycle No. 2[10, 12] CE tRC tACE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT ICC 50% ISB C191–7 Write Cycle No. 1 (WE Controlled)[9] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA C191–8 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. 12. Address valid prior to or coincident with CE transition LOW. Document #: 38-05047 Rev. ** Page 5 of 10 CY7C192 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[9, 13] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN tHZWE DATA OUT (7C192) HIGH IMPEDANCE DATA VALID tHD tHA tSCE C191–9 Notes: 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05047 Rev. ** Page 6 of 10 CY7C192 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C ICC ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 AMBIENT TEMPERATURE(°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 VCC =5.0V VIN =5.0V NORMALIZED I, I CC NORMALIZED I, I CC SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 -55 25 125 SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 DELTA t AA (ns) NORMALIZED IPO 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25°C 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05047 Rev. ** Page 7 of 10 CY7C192 Ordering Information Speed (ns) 12 15 20 25 Ordering Code CY7C192-12PC CY7C192-12VC CY7C192-15PC CY7C192-15VC CY7C192-20PC CY7C192-20VC CY7C192-25PC CY7C192-25VC Package Name P21 V21 P21 V21 P21 V21 P21 V21 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ Commercial Commercial Commercial Operating Range Commercial Document #: 38-05047 Rev. ** Page 8 of 10 CY7C192 Package Diagrams 28-Lead (300-Mil) Molded DIP P21 51-85014-B 28-Lead (300-Mil) Molded SOJ V21 51-85031-B Document #: 38-05047 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C192 Document Title: CY7C192 64K x 4 Static RAM with Separate I/O Document Number: 38-05047 REV. ** ECN NO. 107149 Issue Date 09/10/01 Orig. of Change SZV Description of Change Change Spec number from: 38-00076 to 38-05047 Document #: 38-05047 Rev. ** Page 10 of 10