CY14B256K-SP25XIT

CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock Features ■ ■ ■ ■ 25 ns, 35 ns, and 45 ns access times Pin compatible with STK17T88 Data integrity of Cypress nvSRAM combined with full featured Real Time Clock ❐ Low power, 350 nA RTC current ❐ Capacitor or battery backup for RTC Watchdog timer Clock alarm with programmable interrupts Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap™ initiated by software, device pin, or on power down RECALL to SRAM initiated by software or on power up Infinite READ, WRITE, and RECALL cycles ■ ■ ■ High reliability ❐ Endurance to 200K cycles ❐ Data retention: 20 years at 55°C Single 3V operation with tolerance of +20%, -10% Commercial and industrial temperature 48-Pin SSOP (ROHS compliant) Functional Description The Cypress CY14B256K combines a 256 Kbit nonvolatile static RAM with a full-featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. The real time clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarms or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control. ■ ■ ■ ■ ■ ■ Logic Block Diagram QuantumTrap 512 X 512 A5 A6 A7 A8 A9 A 11 A 12 A 13 A 14 V CC V CAP V RTCbat V RTCcap HSB STORE POWER CONTROL STORE/ RECALL CONTROL ROW DECODER STATIC RAM ARRAY 512 X 512 RECALL SOFTWARE DETECT COLUMN IO A13 - A0 DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS DQ 1 COLUMN DEC RTC A 0 A 1 A 2 A 3 A 4 A 10 x1 x2 INT MUX A14 - A0 OE CE WE Cypress Semiconductor Corporation Document Number: 001-06431 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 24, 2009 [+] Feedback CY14B256K Pin Configurations Figure 1. 48-Pin SSOP V CAP NC A 14 A 12 A7 A6 A5 INT A4 NC NC NC V SS V RTCbat DQ0 A3 A2 A1 A0 DQ1 DQ2 X1 X2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 V CC NC HSB WE A 13 A8 A9 NC A 11 NC NC NC V SS NC V RTCcap DQ 6 OE A 10 CE DQ7 DQ5 DQ4 DQ3 V CC 48-SSOP Top View (Not To Scale) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pin Definitions Pin Name A0–A14 DQ0-DQ7 NC WE CE OE X1 X2 VRTCcap VRTCbat INT VSS VCC HSB W E G Alt IO Type Input No Connect Input Input Input Output Input Power Supply Power Supply Output Ground Power Supply Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. No Connects. This pin is not connected to the die. Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE high causes the IO pins to tri-state. Crystal Connection. Drives crystal on start up. Crystal Connection for 32.768 kHz Crystal. Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used) Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used) Interrupt Output. It is programmed to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain). Ground for the Device. It is connected to ground of the system. Power Supply Inputs to the Device. Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. Input or Output Hardware Store Busy (HSB). When low, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. VCAP Document Number: 001-06431 Rev. *H Page 2 of 28 [+] Feedback CY14B256K Device Operation The CY14B256K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14B256K supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the “Truth Table For SRAM Operations” on page 22 for a complete description of read and write modes. automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2. AutoStore Mode V CC V CAP V CAP V CC 10k Ohm WE SRAM READ The CY14B256K performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-14 determines which of the 32,752 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (see the section Figure 8 on page 17). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (see the section Figure 9 on page 17). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM WRITE A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs are stable before entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0–7 is written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of a CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 15 for the size of the VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tri-state during power up. Many MPUs tri-state their controls on power up. Verify this when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. AutoStore® Operation The CY14B256K stores data to nvSRAM using one of the three storage operations: 1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B256K. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part Hardware STORE (HSB) Operation The CY14B256K provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the CY14B256K conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the STORE (initiated by any means) is in progress. This pin is externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations, that are in progress when HSB is driven low by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B256K continues SRAM operations for tDELAY. During Document Number: 001-06431 Rev. *H Page 3 of 28 0.1UF [+] Feedback CY14B256K tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the CY14B256K continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14B256K remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for READ and WRITE operations. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. Hardware RECALL (Power Up) During power up or after any low power condition (VCC 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V DC Electrical Characteristics Over the Operating Range (VCC = 2.7V to 3.6V) [8, 9] Parameter ICC1 Description Test Conditions Commercial Min Max 65 55 50 70 60 55 3 10 Unit mA mA mA mA mA mA Average VCC Current tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. Average VCC Current All Inputs Do Not Care, VCC = Max during STORE Average current for duration tSTORE Average VCC Current WE > (VCC – 0.2V). All other inputs cycling. at tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate. Values obtained without output loads. 25°C Typical Average VCAP Current during AutoStore Cycle All Inputs Do Not Care, VCC = Max Average current for duration tSTORE Industrial ICC2 ICC3 ICC4 3 mA ISB VCC Standby Current WE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. Input Leakage Current Off State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOUT = –2 mA Output LOW Voltage IOUT = 4 mA Storage Capacitor Between VCAP pin and VSS, 5V Rated 17 VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH -1 -1 2.0 VSS – 0.5 2.4 3 mA IIX IOZ VIH VIL VOH VOL VCAP +1 +1 VCC + 0.5 0.8 μA μA V V V 0.4 120 V μF Notes 8. The HSB pin has IOUT = –10 μA for VOH of 2.4V, this parameter is characterized but not tested. 9. The INT pin is open drain and does not source or sink current when Interrupt register bit D3 is low. Document Number: 001-06431 Rev. *H Page 15 of 28 [+] Feedback CY14B256K Data Retention and Endurance Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 20 200 Unit Years K Capacitance These parameters are guaranteed but not tested. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Max 7 7 Unit pF pF Thermal Resistance These parameters are guaranteed but not tested. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA / JESD51. 48-SSOP 32.9 25.56 Unit °C/W °C/W ΘJA ΘJC Figure 7. AC Test Loads R1 577Ω 3.0V Output 30 pF R2 789Ω Output 5 pF 3.0V R1 577Ω For Tri-state Specs R2 789Ω AC Test Conditions Input Pulse Levels ..................................................0 V to 3 V Input Rise and Fall Times (10% - 90%) ........................